From: Sam Ravnborg Date: Sun, 7 Dec 2008 08:04:30 +0000 (-0800) Subject: sparc: unify kernel/cpu X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=d34dd82905fb8e1117b67ab6c32989f88cfa0ba8;p=deliverable%2Flinux.git sparc: unify kernel/cpu o use cpu_32.c as base o move all sparc64 definitions to the common cpu.c o use ifdef for the parts that differs and use cpu_32 as base o spitfire.h required a CONFIG_SPARC64 guard to fix build on 32 bit Signed-off-by: Sam Ravnborg Signed-off-by: David S. Miller --- diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h index 985ea7e31992..f0d0c40c44da 100644 --- a/arch/sparc/include/asm/spitfire.h +++ b/arch/sparc/include/asm/spitfire.h @@ -6,6 +6,8 @@ #ifndef _SPARC64_SPITFIRE_H #define _SPARC64_SPITFIRE_H +#ifdef CONFIG_SPARC64 + #include /* The following register addresses are accessible via ASI_DMMU @@ -338,5 +340,5 @@ static inline void cheetah_put_itlb_data(int entry, unsigned long data) } #endif /* !(__ASSEMBLY__) */ - +#endif /* CONFIG_SPARC64 */ #endif /* !(_SPARC64_SPITFIRE_H) */ diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile index 04c74d00f832..0ba314b7f111 100644 --- a/arch/sparc/kernel/Makefile +++ b/arch/sparc/kernel/Makefile @@ -27,7 +27,7 @@ obj-y += sys_sparc_$(BITS).o obj-$(CONFIG_SPARC32) += systbls_32.o obj-y += time_$(BITS).o obj-$(CONFIG_SPARC32) += windows.o -obj-y += cpu_$(BITS).o +obj-y += cpu.o obj-$(CONFIG_SPARC32) += devices.o obj-$(CONFIG_SPARC32) += tadpole.o obj-$(CONFIG_SPARC32) += tick14.o diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c new file mode 100644 index 000000000000..6c2da2420f76 --- /dev/null +++ b/arch/sparc/kernel/cpu.c @@ -0,0 +1,338 @@ +/* cpu.c: Dinky routines to look for the kind of Sparc cpu + * we are on. + * + * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "kernel.h" + +DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; + +struct cpu_info { + int psr_vers; + const char *name; +}; + +struct fpu_info { + int fp_vers; + const char *name; +}; + +#define NOCPU 8 +#define NOFPU 8 + +struct manufacturer_info { + int psr_impl; + struct cpu_info cpu_info[NOCPU]; + struct fpu_info fpu_info[NOFPU]; +}; + +#define CPU(ver, _name) \ +{ .psr_vers = ver, .name = _name } + +#define FPU(ver, _name) \ +{ .fp_vers = ver, .name = _name } + +static const struct manufacturer_info __initconst manufacturer_info[] = { +{ + 0, + /* Sun4/100, 4/200, SLC */ + .cpu_info = { + CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"), + /* borned STP1012PGA */ + CPU(4, "Fujitsu MB86904"), + CPU(5, "Fujitsu TurboSparc MB86907"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"), + FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"), + FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"), + /* SparcStation SLC, SparcStation1 */ + FPU(3, "Weitek WTL3170/2"), + /* SPARCstation-5 */ + FPU(4, "Lsi Logic/Meiko L64804 or compatible"), + FPU(-1, NULL) + } +},{ + 1, + .cpu_info = { + /* SparcStation2, SparcServer 490 & 690 */ + CPU(0, "LSI Logic Corporation - L64811"), + /* SparcStation2 */ + CPU(1, "Cypress/ROSS CY7C601"), + /* Embedded controller */ + CPU(3, "Cypress/ROSS CY7C611"), + /* Ross Technologies HyperSparc */ + CPU(0xf, "ROSS HyperSparc RT620"), + CPU(0xe, "ROSS HyperSparc RT625 or RT626"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0, "ROSS HyperSparc combined IU/FPU"), + FPU(1, "Lsi Logic L64814"), + FPU(2, "Texas Instruments TMS390-C602A"), + FPU(3, "Cypress CY7C602 FPU"), + FPU(-1, NULL) + } +},{ + 2, + .cpu_info = { + /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */ + /* Someone please write the code to support this beast! ;) */ + CPU(0, "Bipolar Integrated Technology - B5010"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(-1, NULL) + } +},{ + 3, + .cpu_info = { + CPU(0, "LSI Logic Corporation - unknown-type"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(-1, NULL) + } +},{ + 4, + .cpu_info = { + CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"), + /* SparcClassic -- borned STP1010TAB-50*/ + CPU(1, "Texas Instruments, Inc. - MicroSparc"), + CPU(2, "Texas Instruments, Inc. - MicroSparc II"), + CPU(3, "Texas Instruments, Inc. - SuperSparc 51"), + CPU(4, "Texas Instruments, Inc. - SuperSparc 61"), + CPU(5, "Texas Instruments, Inc. - unknown"), + CPU(-1, NULL) + }, + .fpu_info = { + /* SuperSparc 50 module */ + FPU(0, "SuperSparc on-chip FPU"), + /* SparcClassic */ + FPU(4, "TI MicroSparc on chip FPU"), + FPU(-1, NULL) + } +},{ + 5, + .cpu_info = { + CPU(0, "Matsushita - MN10501"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0, "Matsushita MN10501"), + FPU(-1, NULL) + } +},{ + 6, + .cpu_info = { + CPU(0, "Philips Corporation - unknown"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(-1, NULL) + } +},{ + 7, + .cpu_info = { + CPU(0, "Harvest VLSI Design Center, Inc. - unknown"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(-1, NULL) + } +},{ + 8, + .cpu_info = { + CPU(0, "Systems and Processes Engineering Corporation (SPEC)"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(-1, NULL) + } +},{ + 9, + .cpu_info = { + /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */ + CPU(0, "Fujitsu or Weitek Power-UP"), + CPU(1, "Fujitsu or Weitek Power-UP"), + CPU(2, "Fujitsu or Weitek Power-UP"), + CPU(3, "Fujitsu or Weitek Power-UP"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(3, "Fujitsu or Weitek on-chip FPU"), + FPU(-1, NULL) + } +},{ + 0x17, + .cpu_info = { + CPU(0x10, "TI UltraSparc I (SpitFire)"), + CPU(0x11, "TI UltraSparc II (BlackBird)"), + CPU(0x12, "TI UltraSparc IIi (Sabre)"), + CPU(0x13, "TI UltraSparc IIe (Hummingbird)"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0x10, "UltraSparc I integrated FPU"), + FPU(0x11, "UltraSparc II integrated FPU"), + FPU(0x12, "UltraSparc IIi integrated FPU"), + FPU(0x13, "UltraSparc IIe integrated FPU"), + FPU(-1, NULL) + } +},{ + 0x22, + .cpu_info = { + CPU(0x10, "TI UltraSparc I (SpitFire)"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0x10, "UltraSparc I integrated FPU"), + FPU(-1, NULL) + } +},{ + 0x3e, + .cpu_info = { + CPU(0x14, "TI UltraSparc III (Cheetah)"), + CPU(0x15, "TI UltraSparc III+ (Cheetah+)"), + CPU(0x16, "TI UltraSparc IIIi (Jalapeno)"), + CPU(0x18, "TI UltraSparc IV (Jaguar)"), + CPU(0x19, "TI UltraSparc IV+ (Panther)"), + CPU(0x22, "TI UltraSparc IIIi+ (Serrano)"), + CPU(-1, NULL) + }, + .fpu_info = { + FPU(0x14, "UltraSparc III integrated FPU"), + FPU(0x15, "UltraSparc III+ integrated FPU"), + FPU(0x16, "UltraSparc IIIi integrated FPU"), + FPU(0x18, "UltraSparc IV integrated FPU"), + FPU(0x19, "UltraSparc IV+ integrated FPU"), + FPU(0x22, "UltraSparc IIIi+ integrated FPU"), + FPU(-1, NULL) + } +}}; + +/* In order to get the fpu type correct, you need to take the IDPROM's + * machine type value into consideration too. I will fix this. + */ + +const char *sparc_cpu_type; +const char *sparc_fpu_type; + +unsigned int fsr_storage; + +static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers) +{ + sparc_cpu_type = NULL; + sparc_fpu_type = NULL; + if (psr_impl < ARRAY_SIZE(manufacturer_info)) + { + const struct cpu_info *cpu; + const struct fpu_info *fpu; + + cpu = &manufacturer_info[psr_impl].cpu_info[0]; + while (cpu->psr_vers != -1) + { + if (cpu->psr_vers == psr_vers) { + sparc_cpu_type = cpu->name; + sparc_fpu_type = "No FPU"; + break; + } + cpu++; + } + fpu = &manufacturer_info[psr_impl].fpu_info[0]; + while (fpu->fp_vers != -1) + { + if (fpu->fp_vers == fpu_vers) { + sparc_fpu_type = fpu->name; + break; + } + fpu++; + } + } + if (sparc_cpu_type == NULL) + { + printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n", + psr_impl, psr_vers); + sparc_cpu_type = "Unknown CPU"; + } + if (sparc_fpu_type == NULL) + { + printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n", + psr_impl, fpu_vers); + sparc_fpu_type = "Unknown FPU"; + } +} + +#ifdef CONFIG_SPARC32 +void __cpuinit cpu_probe(void) +{ + int psr_impl, psr_vers, fpu_vers; + int psr; + + psr_impl = ((get_psr() >> 28) & 0xf); + psr_vers = ((get_psr() >> 24) & 0xf); + + psr = get_psr(); + put_psr(psr | PSR_EF); + fpu_vers = ((get_fsr() >> 17) & 0x7); + put_psr(psr); + + set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers); +} +#else +static void __init sun4v_cpu_probe(void) +{ + switch (sun4v_chip_type) { + case SUN4V_CHIP_NIAGARA1: + sparc_cpu_type = "UltraSparc T1 (Niagara)"; + sparc_fpu_type = "UltraSparc T1 integrated FPU"; + break; + + case SUN4V_CHIP_NIAGARA2: + sparc_cpu_type = "UltraSparc T2 (Niagara2)"; + sparc_fpu_type = "UltraSparc T2 integrated FPU"; + break; + + default: + printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", + prom_cpu_compatible); + sparc_cpu_type = "Unknown SUN4V CPU"; + sparc_fpu_type = "Unknown SUN4V FPU"; + break; + } +} + +static int __init cpu_type_probe(void) +{ + if (tlb_type == hypervisor) { + sun4v_cpu_probe(); + } else { + unsigned long ver; + int manuf, impl; + + __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); + + manuf = ((ver >> 48) & 0xffff); + impl = ((ver >> 32) & 0xffff); + set_cpu_and_fpu(manuf, impl, impl); + } + return 0; +} + +arch_initcall(cpu_type_probe); +#endif diff --git a/arch/sparc/kernel/cpu_32.c b/arch/sparc/kernel/cpu_32.c deleted file mode 100644 index 60528227e591..000000000000 --- a/arch/sparc/kernel/cpu_32.c +++ /dev/null @@ -1,247 +0,0 @@ -/* cpu.c: Dinky routines to look for the kind of Sparc cpu - * we are on. - * - * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "kernel.h" - -DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; - -struct cpu_info { - int psr_vers; - const char *name; -}; - -struct fpu_info { - int fp_vers; - const char *name; -}; - -#define NOCPU 8 -#define NOFPU 8 - -struct manufacturer_info { - int psr_impl; - struct cpu_info cpu_info[NOCPU]; - struct fpu_info fpu_info[NOFPU]; -}; - -#define CPU(ver, _name) \ -{ .psr_vers = ver, .name = _name } - -#define FPU(ver, _name) \ -{ .fp_vers = ver, .name = _name } - -static const struct manufacturer_info __initconst manufacturer_info[] = { -{ - 0, - /* Sun4/100, 4/200, SLC */ - .cpu_info = { - CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"), - /* borned STP1012PGA */ - CPU(4, "Fujitsu MB86904"), - CPU(5, "Fujitsu TurboSparc MB86907"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(0, "Fujitsu MB86910 or Weitek WTL1164/5"), - FPU(1, "Fujitsu MB86911 or Weitek WTL1164/5 or LSI L64831"), - FPU(2, "LSI Logic L64802 or Texas Instruments ACT8847"), - /* SparcStation SLC, SparcStation1 */ - FPU(3, "Weitek WTL3170/2"), - /* SPARCstation-5 */ - FPU(4, "Lsi Logic/Meiko L64804 or compatible"), - FPU(-1, NULL) - } -},{ - 1, - .cpu_info = { - /* SparcStation2, SparcServer 490 & 690 */ - CPU(0, "LSI Logic Corporation - L64811"), - /* SparcStation2 */ - CPU(1, "Cypress/ROSS CY7C601"), - /* Embedded controller */ - CPU(3, "Cypress/ROSS CY7C611"), - /* Ross Technologies HyperSparc */ - CPU(0xf, "ROSS HyperSparc RT620"), - CPU(0xe, "ROSS HyperSparc RT625 or RT626"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(0, "ROSS HyperSparc combined IU/FPU"), - FPU(1, "Lsi Logic L64814"), - FPU(2, "Texas Instruments TMS390-C602A"), - FPU(3, "Cypress CY7C602 FPU"), - FPU(-1, NULL) - } -},{ - 2, - .cpu_info = { - /* ECL Implementation, CRAY S-MP Supercomputer... AIEEE! */ - /* Someone please write the code to support this beast! ;) */ - CPU(0, "Bipolar Integrated Technology - B5010"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(-1, NULL) - } -},{ - 3, - .cpu_info = { - CPU(0, "LSI Logic Corporation - unknown-type"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(-1, NULL) - } -},{ - 4, - .cpu_info = { - CPU(0, "Texas Instruments, Inc. - SuperSparc-(II)"), - /* SparcClassic -- borned STP1010TAB-50*/ - CPU(1, "Texas Instruments, Inc. - MicroSparc"), - CPU(2, "Texas Instruments, Inc. - MicroSparc II"), - CPU(3, "Texas Instruments, Inc. - SuperSparc 51"), - CPU(4, "Texas Instruments, Inc. - SuperSparc 61"), - CPU(5, "Texas Instruments, Inc. - unknown"), - CPU(-1, NULL) - }, - .fpu_info = { - /* SuperSparc 50 module */ - FPU(0, "SuperSparc on-chip FPU"), - /* SparcClassic */ - FPU(4, "TI MicroSparc on chip FPU"), - FPU(-1, NULL) - } -},{ - 5, - .cpu_info = { - CPU(0, "Matsushita - MN10501"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(0, "Matsushita MN10501"), - FPU(-1, NULL) - } -},{ - 6, - .cpu_info = { - CPU(0, "Philips Corporation - unknown"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(-1, NULL) - } -},{ - 7, - .cpu_info = { - CPU(0, "Harvest VLSI Design Center, Inc. - unknown"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(-1, NULL) - } -},{ - 8, - .cpu_info = { - CPU(0, "Systems and Processes Engineering Corporation (SPEC)"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(-1, NULL) - } -},{ - 9, - .cpu_info = { - /* Gallium arsenide 200MHz, BOOOOGOOOOMIPS!!! */ - CPU(0, "Fujitsu or Weitek Power-UP"), - CPU(1, "Fujitsu or Weitek Power-UP"), - CPU(2, "Fujitsu or Weitek Power-UP"), - CPU(3, "Fujitsu or Weitek Power-UP"), - CPU(-1, NULL) - }, - .fpu_info = { - FPU(3, "Fujitsu or Weitek on-chip FPU"), - FPU(-1, NULL) - } -}}; - -/* In order to get the fpu type correct, you need to take the IDPROM's - * machine type value into consideration too. I will fix this. - */ - -const char *sparc_cpu_type; -const char *sparc_fpu_type; - -unsigned int fsr_storage; - -static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers) -{ - sparc_cpu_type = NULL; - sparc_fpu_type = NULL; - if (psr_impl < ARRAY_SIZE(manufacturer_info)) - { - const struct cpu_info *cpu; - const struct fpu_info *fpu; - - cpu = &manufacturer_info[psr_impl].cpu_info[0]; - while (cpu->psr_vers != -1) - { - if (cpu->psr_vers == psr_vers) { - sparc_cpu_type = cpu->name; - sparc_fpu_type = "No FPU"; - break; - } - cpu++; - } - fpu = &manufacturer_info[psr_impl].fpu_info[0]; - while (fpu->fp_vers != -1) - { - if (fpu->fp_vers == fpu_vers) { - sparc_fpu_type = fpu->name; - break; - } - fpu++; - } - } - if (sparc_cpu_type == NULL) - { - printk(KERN_ERR "CPU: Unknown chip, impl[0x%x] vers[0x%x]\n", - psr_impl, psr_vers); - sparc_cpu_type = "Unknown CPU"; - } - if (sparc_fpu_type == NULL) - { - printk(KERN_ERR "FPU: Unknown chip, impl[0x%x] vers[0x%x]\n", - psr_impl, fpu_vers); - sparc_fpu_type = "Unknown FPU"; - } -} - -void __cpuinit cpu_probe(void) -{ - int psr_impl, psr_vers, fpu_vers; - int psr; - - psr_impl = ((get_psr() >> 28) & 0xf); - psr_vers = ((get_psr() >> 24) & 0xf); - - psr = get_psr(); - put_psr(psr | PSR_EF); - fpu_vers = ((get_fsr() >> 17) & 0x7); - put_psr(psr); - - set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers); -} diff --git a/arch/sparc/kernel/cpu_64.c b/arch/sparc/kernel/cpu_64.c deleted file mode 100644 index 4a81ed744477..000000000000 --- a/arch/sparc/kernel/cpu_64.c +++ /dev/null @@ -1,167 +0,0 @@ -/* cpu.c: Dinky routines to look for the kind of Sparc cpu - * we are on. - * - * Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "entry.h" -#include "kernel.h" - -DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 }; - -struct cpu_chip_info { - unsigned short manuf; - unsigned short impl; - const char *cpu_name; - const char *fp_name; -}; - -static const struct cpu_chip_info cpu_chips[] = { - { - .manuf = 0x17, - .impl = 0x10, - .cpu_name = "TI UltraSparc I (SpitFire)", - .fp_name = "UltraSparc I integrated FPU", - }, - { - .manuf = 0x22, - .impl = 0x10, - .cpu_name = "TI UltraSparc I (SpitFire)", - .fp_name = "UltraSparc I integrated FPU", - }, - { - .manuf = 0x17, - .impl = 0x11, - .cpu_name = "TI UltraSparc II (BlackBird)", - .fp_name = "UltraSparc II integrated FPU", - }, - { - .manuf = 0x17, - .impl = 0x12, - .cpu_name = "TI UltraSparc IIi (Sabre)", - .fp_name = "UltraSparc IIi integrated FPU", - }, - { - .manuf = 0x17, - .impl = 0x13, - .cpu_name = "TI UltraSparc IIe (Hummingbird)", - .fp_name = "UltraSparc IIe integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x14, - .cpu_name = "TI UltraSparc III (Cheetah)", - .fp_name = "UltraSparc III integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x15, - .cpu_name = "TI UltraSparc III+ (Cheetah+)", - .fp_name = "UltraSparc III+ integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x16, - .cpu_name = "TI UltraSparc IIIi (Jalapeno)", - .fp_name = "UltraSparc IIIi integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x18, - .cpu_name = "TI UltraSparc IV (Jaguar)", - .fp_name = "UltraSparc IV integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x19, - .cpu_name = "TI UltraSparc IV+ (Panther)", - .fp_name = "UltraSparc IV+ integrated FPU", - }, - { - .manuf = 0x3e, - .impl = 0x22, - .cpu_name = "TI UltraSparc IIIi+ (Serrano)", - .fp_name = "UltraSparc IIIi+ integrated FPU", - }, -}; - -#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips) - -const char *sparc_cpu_type; -const char *sparc_fpu_type; - -static void __init sun4v_cpu_probe(void) -{ - switch (sun4v_chip_type) { - case SUN4V_CHIP_NIAGARA1: - sparc_cpu_type = "UltraSparc T1 (Niagara)"; - sparc_fpu_type = "UltraSparc T1 integrated FPU"; - break; - - case SUN4V_CHIP_NIAGARA2: - sparc_cpu_type = "UltraSparc T2 (Niagara2)"; - sparc_fpu_type = "UltraSparc T2 integrated FPU"; - break; - - default: - printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n", - prom_cpu_compatible); - sparc_cpu_type = "Unknown SUN4V CPU"; - sparc_fpu_type = "Unknown SUN4V FPU"; - break; - } -} - -static const struct cpu_chip_info * __init find_cpu_chip(unsigned short manuf, - unsigned short impl) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(cpu_chips); i++) { - const struct cpu_chip_info *p = &cpu_chips[i]; - - if (p->manuf == manuf && p->impl == impl) - return p; - } - return NULL; -} - -static int __init cpu_type_probe(void) -{ - if (tlb_type == hypervisor) { - sun4v_cpu_probe(); - } else { - unsigned long ver, manuf, impl; - const struct cpu_chip_info *p; - - __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); - - manuf = ((ver >> 48) & 0xffff); - impl = ((ver >> 32) & 0xffff); - - p = find_cpu_chip(manuf, impl); - if (p) { - sparc_cpu_type = p->cpu_name; - sparc_fpu_type = p->fp_name; - } else { - printk(KERN_ERR "CPU: Unknown chip, manuf[%lx] impl[%lx]\n", - manuf, impl); - sparc_cpu_type = "Unknown CPU"; - sparc_fpu_type = "Unknown FPU"; - } - } - return 0; -} - -arch_initcall(cpu_type_probe);