From: Victor(Weiguo) Pan <wpan@nvidia.com>
Date: Wed, 22 Jun 2016 11:47:20 +0000 (+0530)
Subject: pwm: tegra: Allow 100 % duty cycle
X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=e0ee1a75f412cc9f3b16127742a30baf975ec51f;p=deliverable%2Flinux.git

pwm: tegra: Allow 100 % duty cycle

To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 097658e0751b..2026eaa932ae 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
 	 * nearest integer during division.
 	 */
-	c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
+	c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
 	do_div(c, period_ns);
 
 	val = (u32)c << PWM_DUTY_SHIFT;