From: Kokoris, Ioannis Date: Fri, 11 Nov 2011 16:05:11 +0000 (+0100) Subject: powerpc/qe: set IReady in QE Microcode Upload X-Git-Url: http://drtracing.org/?a=commitdiff_plain;h=e65650e6c3eb67226eda80a21f62b7aa145878f4;p=deliverable%2Flinux.git powerpc/qe: set IReady in QE Microcode Upload QE Microcode Initialization using qe_upload_microcode() does not work on P1021 if the IRAM-Ready register is not set after the microcode upload. Add a definition for the "I-RAM Ready" register and sets it upon microcode upload completion. Signed-off-by: Ioannis Kokkoris Signed-off-by: Kumar Gala --- diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 0edb6842b13d..61e8490786b8 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -26,7 +26,9 @@ struct qe_iram { __be32 iadd; /* I-RAM Address Register */ __be32 idata; /* I-RAM Data Register */ - u8 res0[0x78]; + u8 res0[0x04]; + __be32 iready; /* I-RAM Ready Register */ + u8 res1[0x70]; } __attribute__ ((packed)); /* QE Interrupt Controller */ diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 5e0b6d511e14..229571a49391 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h @@ -499,6 +499,7 @@ enum comm_dir { /* I-RAM */ #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 /* Ready */ /* UPC */ #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index 818e763f8265..b04367529729 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -395,6 +395,9 @@ static void qe_upload_microcode(const void *base, for (i = 0; i < be32_to_cpu(ucode->count); i++) out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i])); + + /* Set I-RAM Ready Register */ + out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY)); } /*