Enable Intel AVX512_VPOPCNTDQ instructions
[deliverable/binutils-gdb.git] / gas / config /
2017-01-12  Igor TsimbalistEnable Intel AVX512_VPOPCNTDQ instructions
2017-01-09  Andrew WatermanRISC-V/GAS: Support more relocs against constant addresses
2017-01-09  Andrew WatermanRISC-V/GAS: Improve handling of invalid relocs
2017-01-09  Andrew WatermanRISC-V/GAS: Correct branch relaxation for weak symbols.
2017-01-04  Szabolcs Nagy[AArch64] Add separate feature flag for weaker release...
2017-01-03  Kito ChengAdd support for the Q extension to the RISCV ISA.
2017-01-03  Dimitar DimitrovFix PRU GAS for 32-bit hosts
2017-01-02  Alan ModraUpdate year range in copyright notice of all files.
2016-12-31  Dimitar DimitrovPRU GAS Port
2016-12-23  Maciej W. RozyckiMIPS16: Simplify extended operand handling
2016-12-23  Maciej W. RozyckiMIPS16/GAS: Clean up invalid unextended operand handling
2016-12-23  Maciej W. RozyckiMIPS16: Reassign `0' and `4' operand codes
2016-12-23  Maciej W. RozyckiMIPS16: Handle non-extensible instructions correctly
2016-12-23  Maciej W. RozyckiMIPS16: Remove "extended" BREAK/SDBBP handling
2016-12-23  Maciej W. RozyckiMIPS16/GAS: Fix forced size suffixes with argumentless...
2016-12-23  Joe Seymour[msp430] Sync tc-msp430.c with devices.csv
2016-12-21  Andrew WatermanSupport aligning text section from odd addresses
2016-12-21  Tim NewsomeFix a const-safety issue on GCC-4.9 and above
2016-12-20  Maciej W. RozyckiMIPS16: Switch to 32-bit opcode table interpretation
2016-12-20  Andrew WatermanDon't define RISC-V .p2align
2016-12-20  Andrew WatermanRe-work RISC-V gas flags: now we just support -mabi...
2016-12-20  Andrew WatermanRework RISC-V relocations
2016-12-20  Andrew WatermanFormatting changes for RISC-V
2016-12-14  Maciej W. RozyckiMIPS16/GAS: Fix assertion failures with relocations...
2016-12-13  Renlin Li[Binutils][AARCH64]Remove Cn register for coprocessor...
2016-12-09  Maciej W. RozyckiMIPS16: Remove unused `>' operand code
2016-12-08  Maciej W. RozyckiARC/GAS: Correct a `spaces' global shadowing error
2016-12-08  Maciej W. RozyckiARM/GAS: Correct an `index' global shadowing error
2016-12-07  Maciej W. RozyckiMIPS/GAS: Use local `isa' consistently in `is_opcode_valid'
2016-12-05  Szabolcs Nagy[ARM] Add ARMv8.3 VCMLA and VCADD instructions
2016-12-05  Claudiu Zissulescu[ARC] Don't check extAuxRegister second argument for...
2016-12-05  Szabolcs Nagy[ARM] Add ARMv8.3 VJCVT instruction
2016-12-05  Szabolcs Nagy[ARM] Add ARMv8.3 command line option and feature flag
2016-12-02  Claudiu Zissulescu[ARC] Sync cpu names with the ones accepted by GCC.
2016-11-29  Claudiu Zissulescu[ARC] Add checking for LP_COUNT reg usage, improve...
2016-11-27  Ambrogino ModiglianiFix spelling in comments in .l files (gas)
2016-11-27  Ambrogino ModiglianiFix spelling in comments in C source files (gas)
2016-11-25  Jose E. Marchesigas: fix CBCOND diagnostics for invalid immediate operands.
2016-11-23  Kuan-Lin ChenRISCV/GAS Add missing break in md_apply_fix.
2016-11-22  Jose E. Marchesigas,opcodes: fix hardware capabilities bumping in the...
2016-11-22  Alan ModraPR20744, Incorrect PowerPC VLE relocs
2016-11-21  Renlin Li[GAS][ARM][PR20827]Fix gas error for two register form...
2016-11-18  Claudiu Zissulescu[ARC] Fix and extend features of .cpu directive.
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-15  Nick CliftonFix SPARC relocations generated for the .eh_frame section.
2016-11-13  Anthony GreenAssemble 'bad' moxie instruction
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 command line option and feature...
2016-11-11  Szabolcs Nagy[AArch64] Fix feature dependencies for +simd and +crypto
2016-11-04  Andrew Burgessarc/nps400: Validate address type operands correctly
2016-11-04  Andreas KrebbelS/390: Fix 16 bit pc relative relocs.
2016-11-04  Thomas Preud'hommeAdd support for ARM Cortex-M33 processor
2016-11-04  Thomas Preud'hommeAdd support for ARM Cortex-M23 processor
2016-11-03  Andrew Burgessarc: Change max instruction length to 64-bits
2016-11-03  Graham Markallarc: Replace ARC_SHORT macro with arc_opcode_len function
2016-11-03  Graham Markallgas/arc: Replace short_insn flag with insn length field
2016-11-03  Siddhesh PoyarekarNew option falkor for Qualcomm server part
2016-11-03  Jiong Wang[ARM] Allow MOV/MOV.W to accept all possible immediates
2016-11-02  Igor TsimbalistEnable Intel AVX512_4VNNIW instructions
2016-11-02  Igor TsimbalistEnable Intel AVX512_4FMAPS instructions
2016-11-01  Nick CliftonAdd support for RISC-V architecture.
2016-10-27  Andrew Burgessgas/arc: Don't rely on bfd list of cpu type for cpu...
2016-10-26  Alan ModraRevert "bison warning fixes"
2016-10-21  H.J. LuX86: Remove pcommit instruction
2016-10-19  Renlin Li[GAS][ARM]Generate unpredictable warning for pc used...
2016-10-06  Claudiu Zissulescu[ARC] Fix parsing leave_s and enter_s mnemonics.
2016-10-05  Alan Modra-Wimplicit-fallthrough warning fixes
2016-10-05  Alan Modra-Wimplicit-fallthrough error fixes
2016-10-05  Alan Modrabison warning fixes
2016-09-29  Alan ModraDisallow 3-operand cmp[l][i] for ppc64
2016-09-26  Trevor Saunderstc-xtensa.c: fixup xg_reverse_shift_count typo
2016-09-26  Alan ModraPowerPC .gnu.attributes
2016-09-22  Thomas Preud'hommeRemove legacy basepri_mask MRS/MSR special reg
2016-09-21  Richard Sandiford[AArch64] Print spaces after commas in addresses
2016-09-21  Richard Sandiford[AArch64] Use "must" rather than "should" in error...
2016-09-21  Richard Sandiford[AArch64] Add SVE condition codes
2016-09-21  Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21  Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21  Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21  Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21  Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21  Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21  Richard Sandiford[AArch64][SVE 22/32] Add qualifiers for merging and...
2016-09-21  Richard Sandiford[AArch64][SVE 21/32] Add Zn and Pn registers
2016-09-21  Richard Sandiford[AArch64][SVE 20/32] Add support for tied operands
2016-09-21  Richard Sandiford[AArch64][SVE 13/32] Add an F_STRICT flag
2016-09-21  Richard Sandiford[AArch64][SVE 12/32] Remove boolean parameters from...
2016-09-21  Richard Sandiford[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64...
2016-09-21  Richard Sandiford[AArch64][SVE 10/32] Move range check out of parse_aarc...
2016-09-21  Richard Sandiford[AArch64][SVE 09/32] Improve error messages for invalid...
2016-09-21  Richard Sandiford[AArch64][SVE 08/32] Generalise aarch64_double_precisio...
2016-09-21  Richard Sandiford[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYP...
2016-09-21  Richard Sandiford[AArch64][SVE 06/32] Generalise parse_neon_reg_list
2016-09-21  Richard Sandiford[AArch64][SVE 05/32] Rename parse_neon_type_for_operand
2016-09-21  Richard Sandiford[AArch64][SVE 04/32] Rename neon_type_el to vector_type_el
2016-09-21  Richard Sandiford[AArch64][SVE 03/32] Rename neon_el_type to vector_el_type
2016-09-21  Richard Sandiford[AArch64][SVE 01/32] Remove parse_neon_operand_type
next
This page took 0.05163 seconds and 7 git commands to generate.