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[deliverable/binutils-gdb.git] / gas / config /
2018-01-29  Eric BotcazouFix PR gas/22738 (.dc.a directive has wrong size on...
2018-01-24  Renlin Li[GAS][AARCH64]Add group relocations to create PC-relati...
2018-01-23  Maciej W. RozyckiMIPS/GAS: Remove a stale OPTION_COMPAT_ARCH_BASE option...
2018-01-23  Igor TsimbalistEnable Intel PCONFIG instruction.
2018-01-23  Igor TsimbalistEnable Intel WBNOINVD instruction.
2018-01-23  Maciej W. RozyckiMIPS/GAS: Correct `as --help' always reporting `o32...
2018-01-23  Maciej W. RozyckiMIPS/GAS: Add missing `-mmips16e2'/`-mno-mips16e2'...
2018-01-22  Oleg EndoFix the RX assembler so that it can handle escaped...
2018-01-19  Thomas Preud'homme[gas/ARM] Remove spurious comments
2018-01-17  Jim WilsonRISC-V: Fix bug in prior addi/c.nop patch.
2018-01-17  Igor TsimbalistReplace CET bit with IBT and SHSTK bits.
2018-01-15  Thomas Preud'homme[ARM] Add new macro for Thumb-only opcodes
2018-01-15  Thomas Preud'homme[ARM] Enable conditional Armv8-M instructions
2018-01-15  Thomas Preud'homme[ARM] No IT usage deprecation for ARMv8-M
2018-01-12  Gunther NiklFix compile time warning building aout targeted archite...
2018-01-10  Alan Modragas tc-arm.c warning fix
2018-01-09  James Greenhalgh[Arm] Add CSDB instruction
2018-01-03  Alan ModraUpdate year range in copyright notice of binutils files
2018-01-02  Nick CliftonFix typo in do_mrs function in ARM assembler.
2017-12-20  Jim WilsonRISC-V: Add compressed instruction hints, and a few...
2017-12-19  Tamar ChristinaCorrect disassembly of dot product instructions.
2017-12-19  Tamar ChristinaAdd support for V_4B so we can properly reject it.
2017-12-18  Nick CliftonResolve PR 22493 - the encoding to be used when pushing...
2017-12-18  Jan Beulichx86: fold certain AVX and AVX2 templates
2017-12-18  Jan Beulichx86: fold RegXMM/RegYMM/RegZMM into RegSIMD
2017-12-18  Jan Beulichx86: drop FloatReg and FloatAcc
2017-12-18  Jan Beulichx86: replace Reg8, Reg16, Reg32, and Reg64
2017-12-17  H.J. Lux86: Check pseudo prefix without instruction
2017-12-15  Jan Beulichx86: correct operand type checks
2017-12-15  Jan Beulichx86: correct abort check
2017-12-14  Nick CliftonUpdate the address of the FSF in the copyright notice...
2017-12-12  Alan ModraDon't mask X_add_number containing a register number
2017-12-08  Max Filippovgas: xtensa: fix comparison of trampoline chain symbols
2017-12-01  Peter BergnerUse consistent types for holding instructions, instruct...
2017-11-30  Jan Beulichx86: drop Vec_Disp8
2017-11-30  Jan Beulichx86/Intel: issue diagnostics for redundant segment...
2017-11-30  Jan BeulichRevert "x86: Update segment register check in Intel...
2017-11-29  Jim WilsonFix riscv malloc error on small alignment after norvc.
2017-11-29  Renlin Li[GAS][AARCH64]Fix a typo for IP1 register alias.
2017-11-29  Nick CliftonUse the record_alignment function when creating a ...
2017-11-28  Jim WilsonCompress loads/stores with implicit 0 offset.
2017-11-27  Max Filippovgas: xtensa: speed up find_trampoline_seg
2017-11-27  Max Filippovgas: xtensa: implement trampoline coalescing
2017-11-27  Max Filippovgas: xtensa: reuse trampoline placement code
2017-11-27  Max Filippovgas: xtensa: rewrite xg_relax_trampoline
2017-11-27  Max Filippovgas: xtensa: merge trampoline_frag into xtensa_frag_type
2017-11-27  Max Filippovgas: xtensa: reuse find_trampoline_seg
2017-11-27  Max Filippovgas: xtensa: extract jump assembling for trampolines
2017-11-27  Max Filippovgas: extract xg_relax_trampoline from xtensa_relax_frag
2017-11-27  Nick CliftonWhen creating a .note section to contain a version...
2017-11-24  Jan Beulichx86: reject further invalid AVX-512 masking constructs
2017-11-23  Jim WilsonFix build error with --enable-targets=all.
2017-11-23  Jan Beulichx86: fix AVX-512 16-bit addressing
2017-11-23  Jan Beulichx86-64: always use unsigned 32-bit reloc for 32-bit...
2017-11-23  Jan Beulichx86: drop redundant VSIB handling code
2017-11-23  Jan Beulichx86/Intel: don't report multiple errors for a single...
2017-11-22  Jim WilsonRiscv ld-elf/stab failure and fake label cleanup.
2017-11-22  Thomas Preud'homme[GAS/ARM] Clarify relation between reg_expected_msgs...
2017-11-21  Alan Modraxtensa error message
2017-11-16  Tamar ChristinaAdd new AArch64 FP16 FM{A|S} instructions.
2017-11-16  Jan Beulichix86/Intel: don't require memory operand size specifier...
2017-11-15  Tamar ChristinaSeparate the new FP16 instructions backported from...
2017-11-13  Jan Beulichgas/arm64: don't emit stack pointer symbol table entries
2017-11-13  Jan Beulichx86: don't default variable shift count insns to 8...
2017-11-13  Jan Beulichx86/Intel: don't mistake riz/eiz as base register
2017-11-13  Jan Beulichx86-64/Intel: issue diagnostic for out of range displac...
2017-11-09  Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09  Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
2017-11-08  Nick CliftonSplit the AArch64 Crypto instructions for AES and SHA1...
2017-11-08  Jiong WangAdds command line support for Armv8.4-A, via the new...
2017-11-08  Alan Modraxtensa message pluralization
2017-11-07  Jim WilsonRISC-V: Fix riscv g++ testsuite EH failures.
2017-11-07  Palmer DabbeltRISC-V: Add satp as an alias for sptbr
2017-11-07  Tamar ChristinaThis patch similarly to the AArch64 one enables Dot...
2017-11-07  Alan Modragas and ld pluralization fixes
2017-11-03  Siddhesh PoyarekarAdd option for Qualcomm Saphira part
2017-11-01  James BowmanFT32B is a new FT32 family member. It has a code compre...
2017-11-01  Thomas Preud'homme[ARM] Fix Coprocessor instructions availability
2017-10-26  H.J. Lux86: Check invalid XMM register in AVX512 gathers
2017-10-25  Alan ModraPR22348, conflicting global vars in crx and cr16
2017-10-24  H.J. Lui386: Support .code64 directive only with 64-bit bfd
2017-10-24  Palmer DabbeltRISC-V: Don't emit 2-byte NOPs if the C extension is...
2017-10-23  Maciej W. RozyckiMIPS: Preset EF_MIPS_ABI2 with n32 ELF objects
2017-10-23  Igor TsimbalistEnable Intel AVX512_BITALG instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VNNI instructions.
2017-10-23  Igor TsimbalistEnable Intel VPCLMULQDQ instruction.
2017-10-23  Igor TsimbalistEnable Intel VAES instructions.
2017-10-23  Igor TsimbalistEnable Intel GFNI instructions.
2017-10-23  Igor TsimbalistEnable Intel AVX512_VBMI2 instructions.
2017-10-20  Nick CliftonImprove handling of REPT pseudo op with a negative...
2017-10-19  Palmer DabbeltRISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*
2017-10-19  Nick CliftonFix the AVR assembler so that it will correctly issue...
2017-10-17  Sandra LoosemoreFix segfault processing nios2 pseudo-instructions with...
2017-10-13  James BowmanFT32: support for FT32B processor - part 1
2017-10-05  Nick CliftonFix the MSP430 assembler so that it detects and reports...
2017-10-04  Alan ModraPR21167, relocation sections not included in groups
2017-09-21  James CowgillPR gas/21762: MIPS: Fix .stabs directive marking labels...
2017-09-21  Alan ModraReduce excessive .eh_frame alignment for powerpc
2017-09-09  H.J. Lux86: Remove restriction on NOTRACK prefix position
2017-09-07  Palmer DabbeltRISC-V: Avoid emitting invalid instructions in mixed...
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