2018-01-04 | Jim Wilson | RISC-V: Add 2 missing privileged registers. | blob | commitdiff | raw |
2017-12-28 | Jim Wilson | RISC-V: Add missing privileged spec registers. | blob | commitdiff | raw | diff to current |
2017-11-07 | Palmer Dabbelt | RISC-V: Add satp as an alias for sptbr | blob | commitdiff | raw | diff to current |
2017-03-31 | Andrew Waterman | RISC-V: Add physical memory protection CSRs | blob | commitdiff | raw | diff to current |
2017-02-24 | Andrew Waterman | Add new counter-enable CSRs | blob | commitdiff | raw | diff to current |
2017-02-15 | Andrew Waterman | Add SFENCE.VMA instruction | blob | commitdiff | raw | diff to current |
2017-01-03 | Kito Cheng | Add support for the Q extension to the RISCV ISA. | blob | commitdiff | raw | diff to current |
2016-11-01 | Nick Clifton | Add support for RISC-V architecture. | blob | commitdiff | raw | diff to current |