2020-07-21 |
Jan Beulich | Revert "x86: Don't display eiz with no scale" |
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2020-07-15 |
H.J. Lu | x86: Don't display eiz with no scale |
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2020-07-15 |
Jan Beulich | x86: move putop() case labels to restore alphabetic... |
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2020-07-15 |
Jan Beulich | x86: make PUSH/POP disassembly uniform |
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2020-07-15 |
Jan Beulich | x86: avoid attaching suffixes to unambiguous insns |
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2020-07-14 |
H.J. Lu | x86-64: Zero-extend lower 32 bits displacement to 64... |
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2020-07-14 |
Claudiu Zissulescu | arc: Detect usage of illegal double register pairs |
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2020-07-14 |
Jan Beulich | x86/Intel: debug registers are named DRn |
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2020-07-14 |
Jan Beulich | x86: drop Rm and the 'L' macro |
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2020-07-14 |
Jan Beulich | x86: drop Rdq, Rd, and MaskR |
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2020-07-14 |
Jan Beulich | x86: simplify decode of opcodes valid only without... |
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2020-07-14 |
Jan Beulich | x86: also use %BW / %DQ for kshift* |
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2020-07-14 |
Jan Beulich | x86: simplify decode of opcodes valid with (embedded... |
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2020-07-14 |
Jan Beulich | x86: drop further EVEX table entries that can be served... |
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2020-07-14 |
Jan Beulich | x86: drop need_vex_reg |
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2020-07-14 |
Jan Beulich | x86: drop Vex128 and Vex256 |
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2020-07-14 |
Jan Beulich | x86: replace %LW by %DQ |
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2020-07-14 |
Jan Beulich | x86: merge/move logic determining the EVEX disp8 shift |
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2020-07-14 |
Jan Beulich | x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W} |
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2020-07-14 |
Jan Beulich | x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel... |
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2020-07-14 |
Jan Beulich | x86: fold VCMP_Fixup() into CMP_Fixup() |
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2020-07-14 |
Jan Beulich | x86: don't disassemble MOVBE with two suffixes |
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2020-07-14 |
Jan Beulich | x86: avoid attaching suffix to register-only CRC32 |
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2020-07-14 |
Jan Beulich | x86-64: don't hide an empty but meaningless REX prefix |
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2020-07-14 |
Jan Beulich | x86: drop dead code from OP_IMREG() |
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2020-07-10 |
Lili Cui | x86: Add support for Intel AMX instructions |
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2020-07-08 |
Jan Beulich | x86: various XOP insns lack L and/or W bit decoding |
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2020-07-08 |
Jan Beulich | x86: FMA4 scalar insns ignore VEX.L |
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2020-07-08 |
Jan Beulich | x86: re-work operand swapping for XOP shift/rotate... |
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2020-07-08 |
Jan Beulich | x86: re-work operand handling for 5-operand XOP insns |
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2020-07-08 |
Jan Beulich | x86: re-work operand swapping for FMA4 and 4-operand... |
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2020-07-07 |
Claudiu Zissulescu | arc: Update vector instructions. |
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2020-07-07 |
Jan Beulich | x86: introduce %BW to avoid going through vex_w_table[] |
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2020-07-06 |
Jan Beulich | x86: adjust/correct VFRCZ{P,S}{S,D} decoding |
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2020-07-06 |
Jan Beulich | x86: use %LW / %XW instead of going through vex_w_table[] |
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2020-07-06 |
Jan Beulich | x86: most VBROADCAST{F,I}{32,64}x* only accept memory... |
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2020-07-06 |
Jan Beulich | x86: adjust/correct V*{F,I}{32x8,64x4} |
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2020-07-06 |
Jan Beulich | x86: drop EVEX table entries that can be made served... |
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2020-07-06 |
Jan Beulich | x86: AVX512 VPERM{D,Q,PS,PD} insns need to honor EVEX.L'L |
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2020-07-06 |
Jan Beulich | x86: AVX512 extract/insert insns need to honor EVEX.L'L |
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2020-07-06 |
Jan Beulich | x86: honor VEX.W for VCVT{PH2PS,PS2PH} |
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2020-07-06 |
Jan Beulich | x86: drop EVEX table entries that can be served by... |
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2020-07-06 |
Jan Beulich | x86: replace EXqScalarS by EXqVexScalarS |
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2020-07-06 |
Jan Beulich | x86: replace EX{d,q}Scalar by EXxmm_m{d,q} |
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2020-07-06 |
Nick Clifton | Fix spelling mistakes in some of the binutils sub-direc... |
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2020-07-06 |
Nick Clifton | Updated translations for various binutils sub-directories |
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2020-07-04 |
Nick Clifton | Update version to 2.35.50 and regenerate files |
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2020-07-04 |
Nick Clifton | Add markers for binutils 2.35 branch |
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2020-07-02 |
H.J. Lu | x86: Add SwapSources |
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2020-06-30 |
Nelson Chu | RISC-V: Support debug and float CSR as the unprivileged... |
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2020-06-29 |
Alan Modra | C++ comments |
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2020-06-26 |
H.J. Lu | i386-opc.tbl: Add a blank line |
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2020-06-26 |
H.J. Lu | x86: Correct VexSIB128 to VecSIB128 |
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2020-06-26 |
H.J. Lu | x86: Rename VecSIB to SIB for Intel AMX |
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2020-06-26 |
Jan Beulich | x86: make I disassembler macro available for new use |
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2020-06-26 |
Jan Beulich | x86: fix processing of -M disassembler option |
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2020-06-25 |
Jan Beulich | x86: make J disassembler macro available for new use |
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2020-06-25 |
Jan Beulich | x86: drop left-over 4-way alternative disassembler... |
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2020-06-25 |
Jan Beulich | x86: fix SYSRET disassembly, improve {,V}CVTSI2S{S... |
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2020-06-22 |
Nelson Chu | RISC-V: Report warning when linking the objects with... |
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2020-06-18 |
Jan Beulich | x86: also test alternative VMGEXIT encoding |
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2020-06-17 |
Cui,Lili | x86: Delete incorrect vmgexit entry in prefix_table |
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2020-06-14 |
H.J. Lu | x86: Correct xsusldtrk mnemonic |
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2020-06-12 |
Nelson Chu | RISC-V: Drop the privileged spec v1.9 support. |
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2020-06-11 |
Alex Coplan | [PATCH]: aarch64: Refactor representation of system... |
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2020-06-09 |
H.J. Lu | i386-dis.c: Fix a typo in comments |
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2020-06-09 |
Jan Beulich | x86: consistently print prefixes explicitly which are... |
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2020-06-09 |
Jan Beulich | x86: fix {,V}MOV{L,H}PD disassembly |
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2020-06-09 |
Jan Beulich | x86: utilize X macro in EVEX decoding |
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2020-06-09 |
Jan Beulich | x86: correct decoding of packed-FP-only AVX encodings |
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2020-06-09 |
Jan Beulich | x86: correct mis-named MOD_0F51 enumerator |
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2020-06-08 |
Alex Coplan | [PATCH] arm: Add DFB instruction for ARMv8-R |
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2020-06-08 |
Jan Beulich | x86: restrict use of register aliases |
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2020-06-06 |
Alan Modra | Power10 tidies |
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2020-06-05 |
Alan Modra | bpf stack smashing detected |
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2020-06-04 |
Jose E. Marchesi | cpu,gas,opcodes: remove no longer needed workaround... |
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2020-06-04 |
Jose E. Marchesi | opcodes: discriminate endianness and insn-endianness... |
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2020-06-04 |
Jose E. Marchesi | opcodes: support insn endianness in cgen_cpu_open |
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2020-06-03 |
Nick Clifton | Updated Serbian translation for the opcodes sub-directory |
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2020-06-03 |
Nelson Chu | RISC-V: Fix the error when building RISC-V linux native... |
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2020-06-01 |
Alan Modra | Regen opcodes/bpf-desc.c |
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2020-05-28 |
Jose E. Marchesi | cpu,opcodes: add instruction semantics to bpf.cpu and... |
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2020-05-28 |
Alan Modra | ubsan: nios2: undefined shift |
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2020-05-28 |
Alan Modra | asan: ns32k: use of uninitialized value |
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2020-05-28 |
Nick Clifton | Fix a potential use of an uninitialised value in the... |
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2020-05-27 |
Sandra Loosemore | Fix extraction of signed constants in nios2 disassemble... |
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2020-05-26 |
Stefan Schulze Fri... | ChangeLog entries for f687f5f563 |
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2020-05-21 |
Alan Modra | Replace "if (x) free (x)" with "free (x)", opcodes |
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2020-05-20 |
Nelson Chu | [PATCH v2 0/9] RISC-V: Support version controling for... |
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2020-05-19 |
Peter Bergner | Power10 dcbf, sync, and wait extensions. |
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2020-05-19 |
Stafford Horne | or1k: Regenerate opcodes after removing 32-bit support |
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2020-05-11 |
Alan Modra | Power10 VSX scalar min-max-compare quad precision opera... |
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2020-05-11 |
Alan Modra | Power10 VSX load/store rightmost element operations |
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2020-05-11 |
Alan Modra | Power10 test lsb by byte operation |
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2020-05-11 |
Alan Modra | Power10 string operations |
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2020-05-11 |
Peter Bergner | Power10 Set boolean extension |
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2020-05-11 |
Alan Modra | Power10 bit manipulation operations |
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2020-05-11 |
Alan Modra | Power10 VSX PCV generate operations |
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2020-05-11 |
Alan Modra | Power10 VSX Mask Manipulation Operations |
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2020-05-11 |
Alan Modra | Power10 Reduced precision outer product operations |
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