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ChangeLog formatting fixes
[deliverable/binutils-gdb.git]
/
opcodes
/
ChangeLog
2016-12-21
Alan Modra
ChangeLog formatting fixes
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2016-12-21
Andrew Waterman
Avoid creating symbol table entries for registers
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2016-12-20
Maciej W. Rozycki
MIPS16/opcodes: Respect ISA and ASE in disassembly
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2016-12-20
Maciej W. Rozycki
MIPS16: Switch to 32-bit opcode table interpretation
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2016-12-20
Maciej W. Rozycki
MIPS16/opcodes: Correct 64-bit macros' ISA membership
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2016-12-20
Maciej W. Rozycki
MIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
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2016-12-20
Andrew Waterman
Correct assembler mnemonic for RISC-V aqrl AMOs
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2016-12-20
Andrew Waterman
Fix disassembly of RISC-V CSR instructions under -Mno...
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2016-12-20
Andrew Waterman
Add canonical JALR for RISC-V
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2016-12-20
Andrew Waterman
Re-work RISC-V gas flags: now we just support -mabi...
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2016-12-20
Andrew Waterman
Formatting changes for RISC-V
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2016-12-20
Alan Modra
Add opcodes RISC-V dependencies
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2016-12-19
Maciej W. Rozycki
MIPS/opcodes: Only examine ELF file structures if SYMTA...
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2016-12-19
Maciej W. Rozycki
MIPS/opcodes: Only call `bfd_mips_elf_get_abiflags...
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2016-12-16
Nick Clifton
Fix compile time warning building arm-dis.c
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2016-12-14
Maciej W. Rozycki
MIPS/opcodes: Also set disassembler's ASE flags from...
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2016-12-14
Maciej W. Rozycki
MIPS/opcodes: Reorder ELF file header flag handling...
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2016-12-14
Maciej W. Rozycki
MIPS16: Fix SP-relative SD instruction annotation
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2016-12-14
Maciej W. Rozycki
MIPS16/opcodes: Fix and clarify MIPS16e commentary
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2016-12-13
Renlin Li
[Binutils][AARCH64]Remove Cn register for coprocessor...
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2016-12-12
Yao Qi
Handle memory error in print_insn_rx
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2016-12-12
Yao Qi
Handle memory error in print_insn_rl78_common
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2016-12-09
Maciej W. Rozycki
MIPS16: Remove unused `>' operand code
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2016-12-09
Maciej W. Rozycki
MIPS16/opcodes: Use hexadecimal interpretation for...
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2016-12-09
Maciej W. Rozycki
MIPS16/opcodes: Reformat raw EXTEND and undecoded output
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2016-12-08
Maciej W. Rozycki
MIPS16/opcodes: Fix off-by-one indentation in `print_mi...
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2016-12-08
Maciej W. Rozycki
MIPS16/opcodes: Fix PC-relative operation delay-slot...
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2016-12-08
Maciej W. Rozycki
AArch64/opcodes: Correct another `index' global shadowi...
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2016-12-08
Luis Machado
Fix crash when disassembling invalid range on powerpc vle
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2016-12-07
Maciej W. Rozycki
MIPS/opcodes: Correct an `interaction' comment typo
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2016-12-07
Maciej W. Rozycki
MIPS16/opcodes: Update opcode table comment
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2016-12-07
Maciej W. Rozycki
MIPS/opcodes: Reformat `-M' disassembler option's help...
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2016-12-05
Szabolcs Nagy
[ARM] Add ARMv8.3 VCMLA and VCADD instructions
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2016-12-05
Szabolcs Nagy
[ARM] Add ARMv8.3 VJCVT instruction
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2016-12-01
Nick Clifton
Fix abort in x86 disassembler.
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2016-11-29
Claudiu Zissulescu
[ARC] Add checking for LP_COUNT reg usage, improve...
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2016-11-29
Claudiu Zissulescu
[ARC] Fix disassembler option.
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2016-11-28
Amit Pawar
X86: Ignore REX_B bit for 32-bit XOP instructions
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2016-11-22
Ambrogino Modigliani
Fix spelling mistakes in comments in configure scripts
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2016-11-22
Jose E. Marchesi
gas,opcodes: fix hardware capabilities bumping in the...
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2016-11-22
Claudiu Zissulescu
[ARC] Fix printing 'b' mnemonics.
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2016-11-18
Szabolcs Nagy
[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
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2016-11-18
Szabolcs Nagy
[AArch64] Add ARMv8.3 weaker release consistency load...
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2016-11-18
Szabolcs Nagy
[AArch64] Add ARMv8.3 javascript floating-point convers...
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2016-11-18
Szabolcs Nagy
[AArch64] Add ARMv8.3 combined pointer authentication...
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2016-11-11
Szabolcs Nagy
[AArch64] Add ARMv8.3 combined pointer authentication...
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2016-11-11
Szabolcs Nagy
[AArch64] Add ARMv8.3 PACGA instruction
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2016-11-11
Szabolcs Nagy
[AArch64] Add ARMv8.3 single source PAC instructions
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2016-11-11
Szabolcs Nagy
[AArch64] Add ARMv8.3 pointer authentication key registers
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2016-11-11
Szabolcs Nagy
[AArch64] Add ARMv8.3 instructions which are in the...
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2016-11-11
Szabolcs Nagy
[AArch64] Increase max_num_aliases in aarch64-gen
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2016-11-09
H.J. Lu
X86: Remove the .s suffix from EVEX vpextrw
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2016-11-09
H.J. Lu
Update opcodes/ChangeLog
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2016-11-09
H.J. Lu
X86: Merge AVX512F vmovq
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2016-11-08
H.J. Lu
X86: Remove the THREE_BYTE_0F7A entry
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2016-11-07
H.J. Lu
X86: Properly handle bad FPU opcode
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2016-11-04
Andrew Burgess
arc/nps400: Validate address type operands correctly
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2016-11-03
Graham Markall
arc: Implement NPS-400 dcmac instruction
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2016-11-03
Andrew Burgess
arc: Change max instruction length to 64-bits
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2016-11-03
Graham Markall
arc: Swap highbyte and lowbyte in print_insn_arc
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2016-11-03
Graham Markall
arc: Replace ARC_SHORT macro with arc_opcode_len function
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2016-11-03
Andrew Burgess
arc/opcodes/nps400: Fix some instruction masks
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2016-11-03
H.J. Lu
X86: Reuse opcode 0x80 decoder for opcode 0x82
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2016-11-03
H.J. Lu
X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
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2016-11-03
H.J. Lu
X86: Rename REG_82 to REG_83
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2016-11-02
Igor Tsimbalist
Enable Intel AVX512_4VNNIW instructions
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2016-11-02
Igor Tsimbalist
Enable Intel AVX512_4FMAPS instructions
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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2016-10-21
H.J. Lu
X86: Remove pcommit instruction
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2016-10-20
H.J. Lu
Check invalid mask registers
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2016-10-18
H.J. Lu
Check addr32flag instead of sizeflag for rip/eip
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2016-10-18
H.J. Lu
Remove the remaining SSE5 support
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2016-10-18
Maciej W. Rozycki
AArch64/opcodes: Correct an `index' global shadowing...
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2016-10-17
Cupertino Miranda
Removed pseudo invalid instructions opcodes.
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2016-10-14
Claudiu Zissulescu
[ARC] Disassembler: fix LIMM detection for short instru...
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2016-10-11
Jiong Wang
[AArch64] PR target/20666, fix wrong encoding of new...
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2016-10-07
Jiong Wang
[AArch64] PR target/20667, fix disassembler for the...
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2016-10-07
Alan Modra
bfd_merge_private_bfd_data tidy
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2016-10-05
Alan Modra
-Wimplicit-fallthrough warning fixes
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2016-10-05
Alan Modra
-Wimplicit-fallthrough error fixes
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2016-10-05
Alan Modra
Don't use boolean OR in arithmetic expressions
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2016-09-30
H.J. Lu
Don't assign alt twice
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2016-09-30
Jiong Wang
[AArch64] PR target/20553, fix opcode mask for SIMD...
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2016-09-29
Alan Modra
Disallow 3-operand cmp[l][i] for ppc64
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2016-09-26
Vlad Zakharov
When building target binaries, ensure that the warning...
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2016-09-26
Claudiu Zissulescu
[ARC] ISA alignment.
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2016-09-21
Richard Sandiford
[AArch64] Print spaces after commas in addresses
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2016-09-21
Richard Sandiford
[AArch64] Use "must" rather than "should" in error...
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2016-09-21
Richard Sandiford
[AArch64] Add SVE condition codes
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2016-09-21
Richard Sandiford
[AArch64][SVE 31/32] Add SVE instructions
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2016-09-21
Richard Sandiford
[AArch64][SVE 30/32] Add SVE instruction classes
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2016-09-21
Richard Sandiford
[AArch64][SVE 29/32] Add new SVE core & FP register...
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2016-09-21
Richard Sandiford
[AArch64][SVE 28/32] Add SVE FP immediate operands
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2016-09-21
Richard Sandiford
[AArch64][SVE 27/32] Add SVE integer immediate operands
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2016-09-21
Richard Sandiford
[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
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2016-09-21
Richard Sandiford
[AArch64][SVE 25/32] Add support for SVE addressing...
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2016-09-21
Richard Sandiford
[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
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2016-09-21
Richard Sandiford
[AArch64][SVE 23/32] Add SVE pattern and prfop operands
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2016-09-21
Richard Sandiford
[AArch64][SVE 22/32] Add qualifiers for merging and...
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2016-09-21
Richard Sandiford
[AArch64][SVE 21/32] Add Zn and Pn registers
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