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x86-64: don't accept supposedly disabled MOVQ forms
[deliverable/binutils-gdb.git]
/
opcodes
/
ChangeLog
2021-03-26
Jan Beulich
x86-64: don't accept supposedly disabled MOVQ forms
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2021-03-25
Hafiz Abid Qadeer
[NIOS2] Fix disassembly of br.n instruction.
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2021-03-25
Jan Beulich
x86: flag bad S/G insn operand combinations
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2021-03-25
Jan Beulich
x86: flag as bad AVX512 insns with EVEX.z set but EVEX...
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2021-03-25
Jan Beulich
x86: fix AMD Zen3 insns
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2021-03-25
Alan Modra
PR27647 PowerPC extended conditional branch mnemonics
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2021-03-24
Jan Beulich
x86: derive opcode length from opcode value
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2021-03-24
Jan Beulich
x86: derive mandatory prefix attribute from base opcode
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2021-03-24
Jan Beulich
x86: don't use opcode_length to identify pseudo prefixes
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2021-03-23
Jan Beulich
x86: re-number PREFIX_0X<nn>
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2021-03-23
Jan Beulich
x86: re-order two fields of struct insn_template
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2021-03-23
Jan Beulich
x86: split opcode prefix and opcode space representation
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2021-03-22
Martin Liska
Add startswith function and use it instead of CONST_STRNEQ.
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2021-03-16
Kuan-Lin Chen
RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions
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2021-03-12
Przemyslaw Wirkus
aarch64: Add few missing system registers
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2021-03-12
Alan Modra
Re: x86: correct decoding of nop/reserved space (0f18...
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2021-03-11
Jan Beulich
x86: re-order logic in OP_XMM()
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2021-03-11
Jan Beulich
x86: drop a few redundant EVEX-related checks
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2021-03-11
Jan Beulich
x86: remove stray uses of xmmq_mode
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2021-03-10
Jan Beulich
x86/Intel: correct AVX512 S/G disassembly
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2021-03-10
Jan Beulich
x86: re-arrange enumerator and table entry order
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2021-03-10
Jan Beulich
x86: reuse further VEX entries for EVEX
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2021-03-10
Jan Beulich
x86: reuse VEX entries for EVEX vperm{q,pd}
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2021-03-10
Jan Beulich
x86: re-arrange order of decode for various EVEX opcodes
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2021-03-10
Jan Beulich
x86: re-arrange order of decode for various mask reg...
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2021-03-10
Jan Beulich
x86: re-arrange order of decode for various VEX opcodes
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2021-03-10
Jan Beulich
x86: re-arrange order of decode for various legacy...
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2021-03-10
Jan Beulich
x86: correct decoding of nop/reserved space (0f18 ...
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2021-03-09
Jan Beulich
x86: fold some prefix related attributes into a single one
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2021-03-09
Jan Beulich
x86-64: make SYSEXIT handling similar to SYSRET's
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2021-03-03
Jan Beulich
x86: infer operand count of templates
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2021-02-19
Nelson Chu
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL...
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2021-02-18
Nelson Chu
RISC-V: Add bfd/cpu-riscv.h to support all spec version...
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2021-02-17
Alan Modra
read_leb128 overflow checking
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2021-02-16
Jan Beulich
x86: CVTPI2PD has special behavior
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2021-02-16
Jan Beulich
x86: have preprocessor expand macros
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2021-02-15
Andreas Krebbel
IBM Z: Implement instruction set extensions
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2021-02-10
Nick Alcock
bfd, opcodes, libctf: support --with-included-gettext
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2021-02-08
Mike Frysinger
opcodes: tic54x: namespace exported variables
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2021-02-04
Nelson Chu
RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct...
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2021-01-26
Alan Modra
Segmentation fault i386-gen
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2021-01-15
Nelson Chu
RISC-V: Indent and GNU coding standards tidy, also...
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2021-01-15
Nelson Chu
RISC-V: Error and warning messages tidy.
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2021-01-15
Nelson Chu
RISC-V: Comments tidy and improvement.
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2021-01-13
Alan Modra
Regen Makefile.in for jobserver.m4 aclocal.m4 dependency
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2021-01-12
H.J. Lu
Implement a workaround for GNU mak jobserver
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2021-01-12
Nick Clifton
Updated translations for some subdirectories
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2021-01-12
H.J. Lu
Binutils: Check if AR works with --plugin and rc
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2021-01-11
Kyrylo Tkachov
aarch64: Remove support for CSRE
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2021-01-11
Nick Clifton
Updated translations for multiple subdirectories
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2021-01-09
H.J. Lu
Binutils: Pass --plugin to AR and RANLIB
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2021-01-09
Nick Clifton
Change version number to 2.36.50 and regenerate files
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2021-01-09
Nick Clifton
Add Changelog entries and NEWS entries for 2.36 branch
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2021-01-09
Peter Bergner
POWER10: Add Return-Oriented Programming instructions
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2021-01-09
Alan Modra
configure regen
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2021-01-08
Nick Clifton
Updated Swedish translation for the opcodes/ subdirectory
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2021-01-08
Nick Clifton
Fix places in the AArch64 opcodes library code where...
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2021-01-08
Nick Clifton
Treat the AArch64 register id_aa64mmfr2_el1 as a core...
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2021-01-07
Samuel Thibault
libtool.m4: update GNU/Hurd test from upstream. In...
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2021-01-07
Nick Clifton
Updated French translation for the opcodes/ subdirectory.
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2021-01-07
Fredrik Noring
m68k: Require m68020up rather than m68000up for CHK...
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2021-01-07
Philipp Tomsich
RISC-V: Add pause hint instruction.
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2021-01-07
Claire Xenia Wolf
RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr...
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2021-01-01
Alan Modra
Update year range in copyright notice of binutils files
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2021-01-01
Alan Modra
ChangeLog rotation
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2020-12-10
Nelson Chu
RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
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2020-12-10
Nelson Chu
RISC-V: Dump CSR according to the elf privileged spec...
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2020-12-10
Nelson Chu
RISC-V: Control fence.i and csr instructions by zifence...
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2020-12-04
Andreas Krebbel
IBM Z: Add risbgz and risbgnz extended mnemonics
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2020-12-03
Andreas Krebbel
IBM Z: Add support for HLASM extended mnemonics
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2020-12-01
Nelson Chu
RISC-V: Remove the unimplemented extensions.
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2020-12-01
Nelson Chu
RISC-V: Add zifencei and prefixed h class extensions.
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2020-11-29
Borislav Petkov
x86: Do not dump DS/CS segment overrides for branch...
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2020-11-16
Przemyslaw Wirkus
aarch64: Extract Condition flag manipulation feature...
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2020-11-14
Borislav Petkov
x86: Ignore CS/DS/ES/SS segment-override prefixes in...
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2020-11-11
Przemyslaw Wirkus
aarch64: Allow LS64 feature with Armv8.6
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2020-11-09
Spencer E. Olson
Add support for the LMBD (left-most bit detect) instruc...
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2020-11-09
Przemyslaw Wirkus
aarch64: Update LS64 feature with system register
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2020-11-09
Przemyslaw Wirkus
aarch64: Limit Rt register number for LS64 load/store...
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2020-11-06
Przemyslaw Wirkus
aarch64: Extract Pointer Authentication feature from...
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2020-11-04
Przemyslaw Wirkus
aarch64: Update feature RAS system registers
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2020-11-03
Przemyslaw Wirkus
[PATCH][GAS] aarch64: Add atomic 64-byte load/store...
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2020-11-03
Przemyslaw Wirkus
[PATCH] aarch64: Update missing ChangeLog for AArch64...
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2020-10-26
Cooper Qu
CSKY: Change plsl.u16 to plsl.16.
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2020-10-26
Cooper Qu
CSKY: Fix and add some instructions for VDSPV1.
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2020-10-26
Cui,Lili
Change avxvnni disassembler output from {vex3} to ...
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2020-10-22
H.J. Lu
opcodes/po/es.po: Remove the duplicated entry
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2020-10-22
Dr. David Alan Gilbert
Fix printf formatting errors where "0x" is used as...
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2020-10-20
Ganesh Gopalasubra...
Add AMD znver3 processor support
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2020-10-16
Cui,Lili
Enhancement for avx-vnni patch
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2020-10-14
H.J. Lu
x86: Support Intel AVX VNNI
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2020-10-14
Lili Cui
x86: Add support for Intel HRESET instruction
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2020-10-14
Lili Cui
x86: Support Intel UINTR
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2020-10-14
H.J. Lu
x86: Remove the prefix byte from non-VEX/EVEX base_opcode
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2020-10-14
H.J. Lu
x86: Rename VexOpcode to OpcodePrefix
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2020-10-05
Samanta Navarro
Fix spelling mistakes
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2020-10-05
H.J. Lu
x86-64: Always display suffix for %LQ in 64bit
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2020-10-05
H.J. Lu
x86: Clear modrm if not needed
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2020-09-28
Przemyslaw Wirkus
This patch introduces ETMv4 (Embedded Trace Macrocell...
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2020-09-28
Przemyslaw Wirkus
This patch introduces ETE (Embedded Trace Extension...
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