[ARM] Don't warn on REG_SP when used in CRC32 instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
2017-08-09  Jiong Wang[ARM] Don't warn on REG_SP when used in CRC32 instructions
2017-08-07  H.J. LuMark big and mach with ATTRIBUTE_UNUSED
2017-08-07  Maciej W. RozyckiGDB/opcodes: Remove arch/mach/endian disassembler asser...
2017-07-25  Nick CliftonFix typos in error and option messages in OPCODES library.
2017-07-24  Jiong Wang[AArch64] Fix the bit pattern order in the comments...
2017-07-21  Andreas KrebbelS/390: Support z14 as CPU name.
2017-07-20  Nick CliftonUpdate the German translation for the opcodes library.
2017-07-19  claziss[ARC] Add SecureShield AUX registers
2017-07-19  Claudiu Zissulescu[ARC] Add SJLI instruction.
2017-07-19  John Eric Martin[ARC] Add JLI support.
2017-07-18  Yuri ChornovianFix spelling typos.
2017-07-14  Ravi Bangoriabinutils/objdump: Fix disassemble for huge elf sections
2017-07-12  Alan ModraUpdate PO files
2017-07-11  Alan ModraMark generated cgen files read-only
2017-07-07  Alan ModraMove print_insn_XXX to an opcodes internal header,...
2017-07-05  Borislav PetkovX86: Disassemble primary opcode map's group 2 ModRM...
2017-07-05  Ramana RadhakrishnanFixup changelog entries for previous commit
2017-07-04  Tristan GingoldRegenerate configure.
2017-07-03  Tristan GingoldRegenerate pot files.
2017-06-30  Maciej W. RozyckiMIPS/opcodes: Reorder LSA and DLSA instructions
2017-06-30  Maciej W. RozyckiMIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
2017-06-30  Maciej W. RozyckiMIPS: Add microMIPS XPA support
2017-06-30  Maciej W. RozyckiMIPS: Add microMIPS R5 support
2017-06-30  Maciej W. RozyckiMIPS: Fix XPA base and Virtualization ASE instruction...
2017-06-29  Maciej W. RozyckiMIPS/opcodes: Correctly combine ASE flags for ASE_MIPS1...
2017-06-29  Anton Kolesov[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over...
2017-06-29  Anton Kolesov[ARC] Fix handling of cpu=... disassembler option value
2017-06-28  Tamar Christina[AArch64] Add dot product support for AArch64 to binutils
2017-06-28  Jiong Wang[ARM] Assembler and disassembler support Dot Product...
2017-06-28  Maciej W. RozyckiMIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
2017-06-23  Andrew WatermanRISC-V: Fix SLTI disassembly
2017-06-21  H.J. Lux86: CET v2.0: Update incssp and setssbsy
2017-06-21  H.J. Lux86: CET v2.0: Rename savessp to saveprevssp
2017-06-21  H.J. Lux86: CET v2.0: Update NOTRACK prefix
2017-06-19  Nick CliftonPrevent address violation when attempting to disassembl...
2017-06-16  Alan ModraRegen rx-decode.c
2017-06-15  H.J. Lui386-dis: Check valid bnd register
2017-06-15  Nick CliftonPrevent address violation problem when disassembling...
2017-06-15  Nick CliftonFix address violation when disassembling a corrupt...
2017-06-15  Nick CliftonPrevent invalid array accesses when disassembling a...
2017-06-14  Nick CliftonFix seg-fault when trying to disassemble a corrupt...
2017-06-14  Yao QiDon't use print_insn_XXX in GDB
2017-06-14  Nick CliftonFix address violation problems when disassembling a...
2017-06-14  Andre Vieira[opcodes][arm] Remove bogus entry added by accident...
2017-05-30  Anton Kolesov[ARC] Allow CPU to be enforced via disassemble_info...
2017-05-24  Yao QiMove print_insn_XXX to an opcodes internal header
2017-05-24  Yao QiUse disassemble.c:disassembler select rl78 disassembler
2017-05-24  Yao QiRefactor disassembler selection
2017-05-22  H.J. Lux86: Add NOTRACK prefix support
2017-05-19  Jose E. Marchesibinutils: support for the SPARC M8 processor
2017-05-18  Alan ModraDon't compare boolean values against TRUE or FALSE
2017-05-15  Maciej W. RozyckiMIPS16e2: Add MIPS16e2 ASE support
2017-05-15  Maciej W. RozyckiMIPS/opcodes: Remove an incorrect MT ASE reference...
2017-05-12  Maciej W. RozyckiMIPS16/opcodes: Make the handling of BREAK and SDBBP...
2017-05-11  Maciej W. RozyckiMIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
2017-05-10  Claudiu Zissulescu[ARC] Object attributes.
2017-05-04  Kito ChengRISC-V: Fix disassemble for c.li, c.andi and c.addiw
2017-05-02  Michael ClarkRISC-V: Change CALL macro to use ra as the temporary...
2017-05-02  Maciej W. RozyckiMIPS16/opcodes: Keep the LSB of PC-relative offsets...
2017-05-02  Bernd EdlingerFix value in comment of disassembled ARM type A opcodes.
2017-04-25  Claudiu Zissulescu[ARC] Enhance enter/leave mnemonics.
2017-04-25  Claudiu Zissulescu[ARC] Prefer NOP instead of MOV 0,0
2017-04-25  Maciej W. RozyckiMIPS16/opcodes: Add `-M no-aliases' disassembler option...
2017-04-25  Maciej W. RozyckiMIPS16/opcodes: Annotate instruction aliases
2017-04-24  Tamar ChristinaFix snafu in aarch64 opcodes debugging statement.
2017-04-22  Alan ModraPowerPC VLE insn set additions
2017-04-21  Jose E. Marchesiopcodes: mark SPARC RETT instructions as v6notv9.
2017-04-21  Nick CliftonFix detection of illegal AArch64 opcodes that resemble...
2017-04-13  Alan ModraRegen cgen files
2017-04-10  Alan ModraReorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
2017-04-10  Alan ModraBye bye PPC_OPCODE_HTM and -mhtm
2017-04-10  Alan ModraBye Bye PPC_OPCODE_VSX3
2017-04-10  Alan ModraBye bye PPC_OPCODE_ALTIVEC2
2017-04-10  Alan ModraTidy ppc476 opcodes
2017-04-10  Pip CetWebAssembly disassembler support
2017-04-07  Alan ModraRemove E6500 insns from PPC_OPCODE_ALTIVEC2
2017-04-06  Pip CetAdd support for disassembling WebAssembly opcodes.
2017-04-05  Pedro Alves-Wwrite-strings: Constify struct disassemble_info's...
2017-04-04  Palmer DabbeltRISC-V: Resurrect GP-relative disassembly hints
2017-03-30  Pip CetAdd support for the WebAssembly file format and the...
2017-03-29  Jose E. Marchesiopcodes: sparc: support missing SPARC ASIs from UA2005...
2017-03-29  Alan ModraPowerPC -Mraw disassembly
2017-03-27  Alan ModraPR21303, objdump doesn't show e200z4 insns
2017-03-27  Rinat ZeligImplement ARC NPS-400 Ultra Ip and Miscellaneous instru...
2017-03-21  Andreas KrebbelS/390: Remove vx2 facility flag
2017-03-21  Rinat Zeligarc/nps400: Add cp16/cp32 instructions to opcodes library
2017-03-17  Alan ModraE6500 spr mnemonics
2017-03-15  Kito ChengRISC-V: Fix assembler for c.li, c.andi and c.addiw
2017-03-15  Kito ChengRISC-V: Fix assembler for c.addi, rd can be x0
2017-03-14  Andrew WatermanRISC-V: Fix [dis]assembly of srai/srli
2017-03-09  H.J. LuX86: Add pseudo prefixes to control encoding
2017-03-09  H.J. LuUse CpuCET on rdsspq
2017-03-09  Peter BergnerUpdate -maltivec and -mvsx options to only enable their...
2017-03-08  Peter BergnerAdd support for the new 'lnia' extended mnemonic.
2017-03-06  H.J. LuAdd support for Intel CET instructions
2017-03-06  Alan ModraDon't decode powerpc insns with invalid fields
2017-02-28  Peter BergnerGDB: Add support for the new set/show disassembler...
2017-02-28  Jan Beulichx86: fix handling of 64-bit operand size VPCMPESTR...
2017-02-24  Richard Sandiford[AArch64] Additional SVE instructions
2017-02-24  Richard Sandiford[AArch64] Add a "compnum" feature
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