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[ARM] Don't warn on REG_SP when used in CRC32 instructions
[deliverable/binutils-gdb.git]
/
opcodes
/
ChangeLog
2017-08-09
Jiong Wang
[ARM] Don't warn on REG_SP when used in CRC32 instructions
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2017-08-07
H.J. Lu
Mark big and mach with ATTRIBUTE_UNUSED
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2017-08-07
Maciej W. Rozycki
GDB/opcodes: Remove arch/mach/endian disassembler asser...
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2017-07-25
Nick Clifton
Fix typos in error and option messages in OPCODES library.
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2017-07-24
Jiong Wang
[AArch64] Fix the bit pattern order in the comments...
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2017-07-21
Andreas Krebbel
S/390: Support z14 as CPU name.
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2017-07-20
Nick Clifton
Update the German translation for the opcodes library.
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2017-07-19
claziss
[ARC] Add SecureShield AUX registers
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2017-07-19
Claudiu Zissulescu
[ARC] Add SJLI instruction.
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2017-07-19
John Eric Martin
[ARC] Add JLI support.
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2017-07-18
Yuri Chornovian
Fix spelling typos.
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2017-07-14
Ravi Bangoria
binutils/objdump: Fix disassemble for huge elf sections
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2017-07-12
Alan Modra
Update PO files
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2017-07-11
Alan Modra
Mark generated cgen files read-only
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2017-07-07
Alan Modra
Move print_insn_XXX to an opcodes internal header,...
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2017-07-05
Borislav Petkov
X86: Disassemble primary opcode map's group 2 ModRM...
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2017-07-05
Ramana Radhakrishnan
Fixup changelog entries for previous commit
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2017-07-04
Tristan Gingold
Regenerate configure.
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2017-07-03
Tristan Gingold
Regenerate pot files.
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2017-06-30
Maciej W. Rozycki
MIPS/opcodes: Reorder LSA and DLSA instructions
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2017-06-30
Maciej W. Rozycki
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
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2017-06-30
Maciej W. Rozycki
MIPS: Add microMIPS XPA support
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2017-06-30
Maciej W. Rozycki
MIPS: Add microMIPS R5 support
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2017-06-30
Maciej W. Rozycki
MIPS: Fix XPA base and Virtualization ASE instruction...
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2017-06-29
Maciej W. Rozycki
MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS1...
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2017-06-29
Anton Kolesov
[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over...
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2017-06-29
Anton Kolesov
[ARC] Fix handling of cpu=... disassembler option value
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2017-06-28
Tamar Christina
[AArch64] Add dot product support for AArch64 to binutils
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2017-06-28
Jiong Wang
[ARM] Assembler and disassembler support Dot Product...
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2017-06-28
Maciej W. Rozycki
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor...
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2017-06-23
Andrew Waterman
RISC-V: Fix SLTI disassembly
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2017-06-21
H.J. Lu
x86: CET v2.0: Update incssp and setssbsy
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2017-06-21
H.J. Lu
x86: CET v2.0: Rename savessp to saveprevssp
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2017-06-21
H.J. Lu
x86: CET v2.0: Update NOTRACK prefix
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2017-06-19
Nick Clifton
Prevent address violation when attempting to disassembl...
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2017-06-16
Alan Modra
Regen rx-decode.c
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2017-06-15
H.J. Lu
i386-dis: Check valid bnd register
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2017-06-15
Nick Clifton
Prevent address violation problem when disassembling...
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2017-06-15
Nick Clifton
Fix address violation when disassembling a corrupt...
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2017-06-15
Nick Clifton
Prevent invalid array accesses when disassembling a...
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2017-06-14
Nick Clifton
Fix seg-fault when trying to disassemble a corrupt...
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2017-06-14
Yao Qi
Don't use print_insn_XXX in GDB
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2017-06-14
Nick Clifton
Fix address violation problems when disassembling a...
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2017-06-14
Andre Vieira
[opcodes][arm] Remove bogus entry added by accident...
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2017-05-30
Anton Kolesov
[ARC] Allow CPU to be enforced via disassemble_info...
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2017-05-24
Yao Qi
Move print_insn_XXX to an opcodes internal header
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2017-05-24
Yao Qi
Use disassemble.c:disassembler select rl78 disassembler
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2017-05-24
Yao Qi
Refactor disassembler selection
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2017-05-22
H.J. Lu
x86: Add NOTRACK prefix support
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2017-05-19
Jose E. Marchesi
binutils: support for the SPARC M8 processor
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2017-05-18
Alan Modra
Don't compare boolean values against TRUE or FALSE
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2017-05-15
Maciej W. Rozycki
MIPS16e2: Add MIPS16e2 ASE support
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2017-05-15
Maciej W. Rozycki
MIPS/opcodes: Remove an incorrect MT ASE reference...
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2017-05-12
Maciej W. Rozycki
MIPS16/opcodes: Make the handling of BREAK and SDBBP...
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2017-05-11
Maciej W. Rozycki
MIPS/opcodes: Mark descriptive SYNC mnemonics as aliases
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2017-05-10
Claudiu Zissulescu
[ARC] Object attributes.
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2017-05-04
Kito Cheng
RISC-V: Fix disassemble for c.li, c.andi and c.addiw
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2017-05-02
Michael Clark
RISC-V: Change CALL macro to use ra as the temporary...
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2017-05-02
Maciej W. Rozycki
MIPS16/opcodes: Keep the LSB of PC-relative offsets...
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2017-05-02
Bernd Edlinger
Fix value in comment of disassembled ARM type A opcodes.
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2017-04-25
Claudiu Zissulescu
[ARC] Enhance enter/leave mnemonics.
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2017-04-25
Claudiu Zissulescu
[ARC] Prefer NOP instead of MOV 0,0
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2017-04-25
Maciej W. Rozycki
MIPS16/opcodes: Add `-M no-aliases' disassembler option...
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2017-04-25
Maciej W. Rozycki
MIPS16/opcodes: Annotate instruction aliases
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2017-04-24
Tamar Christina
Fix snafu in aarch64 opcodes debugging statement.
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2017-04-22
Alan Modra
PowerPC VLE insn set additions
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2017-04-21
Jose E. Marchesi
opcodes: mark SPARC RETT instructions as v6notv9.
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2017-04-21
Nick Clifton
Fix detection of illegal AArch64 opcodes that resemble...
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2017-04-13
Alan Modra
Regen cgen files
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2017-04-10
Alan Modra
Reorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
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2017-04-10
Alan Modra
Bye bye PPC_OPCODE_HTM and -mhtm
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2017-04-10
Alan Modra
Bye Bye PPC_OPCODE_VSX3
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2017-04-10
Alan Modra
Bye bye PPC_OPCODE_ALTIVEC2
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2017-04-10
Alan Modra
Tidy ppc476 opcodes
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2017-04-10
Pip Cet
WebAssembly disassembler support
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2017-04-07
Alan Modra
Remove E6500 insns from PPC_OPCODE_ALTIVEC2
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2017-04-06
Pip Cet
Add support for disassembling WebAssembly opcodes.
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2017-04-05
Pedro Alves
-Wwrite-strings: Constify struct disassemble_info's...
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2017-04-04
Palmer Dabbelt
RISC-V: Resurrect GP-relative disassembly hints
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2017-03-30
Pip Cet
Add support for the WebAssembly file format and the...
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2017-03-29
Jose E. Marchesi
opcodes: sparc: support missing SPARC ASIs from UA2005...
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2017-03-29
Alan Modra
PowerPC -Mraw disassembly
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2017-03-27
Alan Modra
PR21303, objdump doesn't show e200z4 insns
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2017-03-27
Rinat Zelig
Implement ARC NPS-400 Ultra Ip and Miscellaneous instru...
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2017-03-21
Andreas Krebbel
S/390: Remove vx2 facility flag
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2017-03-21
Rinat Zelig
arc/nps400: Add cp16/cp32 instructions to opcodes library
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2017-03-17
Alan Modra
E6500 spr mnemonics
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2017-03-15
Kito Cheng
RISC-V: Fix assembler for c.li, c.andi and c.addiw
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2017-03-15
Kito Cheng
RISC-V: Fix assembler for c.addi, rd can be x0
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2017-03-14
Andrew Waterman
RISC-V: Fix [dis]assembly of srai/srli
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2017-03-09
H.J. Lu
X86: Add pseudo prefixes to control encoding
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2017-03-09
H.J. Lu
Use CpuCET on rdsspq
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2017-03-09
Peter Bergner
Update -maltivec and -mvsx options to only enable their...
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2017-03-08
Peter Bergner
Add support for the new 'lnia' extended mnemonic.
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2017-03-06
H.J. Lu
Add support for Intel CET instructions
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2017-03-06
Alan Modra
Don't decode powerpc insns with invalid fields
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2017-02-28
Peter Bergner
GDB: Add support for the new set/show disassembler...
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2017-02-28
Jan Beulich
x86: fix handling of 64-bit operand size VPCMPESTR...
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2017-02-24
Richard Sandiford
[AArch64] Additional SVE instructions
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2017-02-24
Richard Sandiford
[AArch64] Add a "compnum" feature
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