RISC-V: Fix disassemble for c.li, c.andi and c.addiw
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
2017-05-04  Kito ChengRISC-V: Fix disassemble for c.li, c.andi and c.addiw
2017-05-02  Michael ClarkRISC-V: Change CALL macro to use ra as the temporary...
2017-05-02  Maciej W. RozyckiMIPS16/opcodes: Keep the LSB of PC-relative offsets...
2017-05-02  Bernd EdlingerFix value in comment of disassembled ARM type A opcodes.
2017-04-25  Claudiu Zissulescu[ARC] Enhance enter/leave mnemonics.
2017-04-25  Claudiu Zissulescu[ARC] Prefer NOP instead of MOV 0,0
2017-04-25  Maciej W. RozyckiMIPS16/opcodes: Add `-M no-aliases' disassembler option...
2017-04-25  Maciej W. RozyckiMIPS16/opcodes: Annotate instruction aliases
2017-04-24  Tamar ChristinaFix snafu in aarch64 opcodes debugging statement.
2017-04-22  Alan ModraPowerPC VLE insn set additions
2017-04-21  Jose E. Marchesiopcodes: mark SPARC RETT instructions as v6notv9.
2017-04-21  Nick CliftonFix detection of illegal AArch64 opcodes that resemble...
2017-04-13  Alan ModraRegen cgen files
2017-04-10  Alan ModraReorder PPC_OPCODE_* and set PPC_OPCODE_TMR for e6500
2017-04-10  Alan ModraBye bye PPC_OPCODE_HTM and -mhtm
2017-04-10  Alan ModraBye Bye PPC_OPCODE_VSX3
2017-04-10  Alan ModraBye bye PPC_OPCODE_ALTIVEC2
2017-04-10  Alan ModraTidy ppc476 opcodes
2017-04-10  Pip CetWebAssembly disassembler support
2017-04-07  Alan ModraRemove E6500 insns from PPC_OPCODE_ALTIVEC2
2017-04-06  Pip CetAdd support for disassembling WebAssembly opcodes.
2017-04-05  Pedro Alves-Wwrite-strings: Constify struct disassemble_info's...
2017-04-04  Palmer DabbeltRISC-V: Resurrect GP-relative disassembly hints
2017-03-30  Pip CetAdd support for the WebAssembly file format and the...
2017-03-29  Jose E. Marchesiopcodes: sparc: support missing SPARC ASIs from UA2005...
2017-03-29  Alan ModraPowerPC -Mraw disassembly
2017-03-27  Alan ModraPR21303, objdump doesn't show e200z4 insns
2017-03-27  Rinat ZeligImplement ARC NPS-400 Ultra Ip and Miscellaneous instru...
2017-03-21  Andreas KrebbelS/390: Remove vx2 facility flag
2017-03-21  Rinat Zeligarc/nps400: Add cp16/cp32 instructions to opcodes library
2017-03-17  Alan ModraE6500 spr mnemonics
2017-03-15  Kito ChengRISC-V: Fix assembler for c.li, c.andi and c.addiw
2017-03-15  Kito ChengRISC-V: Fix assembler for c.addi, rd can be x0
2017-03-14  Andrew WatermanRISC-V: Fix [dis]assembly of srai/srli
2017-03-09  H.J. LuX86: Add pseudo prefixes to control encoding
2017-03-09  H.J. LuUse CpuCET on rdsspq
2017-03-09  Peter BergnerUpdate -maltivec and -mvsx options to only enable their...
2017-03-08  Peter BergnerAdd support for the new 'lnia' extended mnemonic.
2017-03-06  H.J. LuAdd support for Intel CET instructions
2017-03-06  Alan ModraDon't decode powerpc insns with invalid fields
2017-02-28  Peter BergnerGDB: Add support for the new set/show disassembler...
2017-02-28  Jan Beulichx86: fix handling of 64-bit operand size VPCMPESTR...
2017-02-24  Richard Sandiford[AArch64] Additional SVE instructions
2017-02-24  Richard Sandiford[AArch64] Add a "compnum" feature
2017-02-24  Jan Beulichx86: also correctly support TEST opcode aliases
2017-02-23  Sheldon Loboopcodes,gas: associate SPARC ASIs with an architecture...
2017-02-23  Jan Beulichx86: drop stray VEX opcode 82 references
2017-02-22  Jan Beulichaarch64: actually copy first operand in convert_bfc_to_...
2017-02-15  Andrew WatermanAdd SFENCE.VMA instruction
2017-02-15  Richard Sandiford[AArch64] Add SVE system registers
2017-02-15  Claudiu Zissulescu[ARC] Fix assembler relaxation.
2017-02-15  Vineet GuptaDistinguish some of the registers different on ARC700...
2017-02-14  Alan ModraPowerPC register expression checks
2017-02-11  Alan ModraFix use after free in cgen instruction lookup
2017-02-10  Nicholas PigginPOWER9 add scv/rfscv instruction support
2017-02-03  Nick CliftonFix compile time warning messages when compiling binuti...
2017-01-27  Alexis DeruellFix disassembling of TIC6X parallel instructions where...
2017-01-25  Dimitar DimitrovClarify that include/opcode/ files are part of GNU...
2017-01-20  Nick CliftonUpdated Irish translation for the opcodes library.
2017-01-18  Szabolcs Nagy[ARM] Fix the decoding of indexed element VCMLA instruction
2017-01-13  Yao QiReturn -1 on memory error in print_insn_m68k
2017-01-13  Yao QiRemove magic numbers in m68k-dis.c:print_insn_arg
2017-01-12  Igor TsimbalistEnable Intel AVX512_VPOPCNTDQ instructions
2017-01-12  Yao QiReturn -1 on memory error in print_insn_msp430
2017-01-05  Nick CliftonPrevent an abort in the FRV disassembler if the target...
2017-01-04  Szabolcs Nagy[AArch64] Add separate feature flag for weaker release...
2017-01-03  Kito ChengAdd support for the Q extension to the RISCV ISA.
2017-01-03  Dilyan PalauzovAdd fall through comment.
2017-01-03  Nick CliftonAdd new Serbian translation for the opcodes library.
2017-01-02  Alan ModraRegen opcodes cgen files
2017-01-02  Alan ModraUpdate year range in copyright notice of all files.
2017-01-02  Alan ModraChangeLog rotation
2016-12-31  Alan ModraFix riscv breakage
2016-12-31  Dimitar DimitrovPRU Opcode Port
2016-12-29  Yao QiReturn 'int' rather than 'unsigned short' in avrdis_opcode
2016-12-28  Alan ModraCheck bfd support for bfd_mips_elf_get_abiflags in...
2016-12-23  Maciej W. RozyckiMIPS16: Add ASMACRO instruction support
2016-12-23  Maciej W. RozyckiMIPS16: Simplify extended operand handling
2016-12-23  Maciej W. RozyckiMIPS16: Reassign `0' and `4' operand codes
2016-12-23  Maciej W. RozyckiMIPS16: Handle non-extensible instructions correctly
2016-12-23  Maciej W. RozyckiMIPS16: Remove "extended" BREAK/SDBBP handling
2016-12-23  Maciej W. RozyckiMIPS16/GAS: Disallow EXTEND delay-slot scheduling
2016-12-23  Maciej W. Rozyckiopcodes: Use autoconf to check for `bfd_mips_elf_get_ab...
2016-12-23  Tristan GingoldBump version to 2.28.51
2016-12-23  Tristan GingoldRegenerate pot files.
2016-12-21  Alan ModraChangeLog formatting fixes
2016-12-21  Andrew WatermanAvoid creating symbol table entries for registers
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Respect ISA and ASE in disassembly
2016-12-20  Maciej W. RozyckiMIPS16: Switch to 32-bit opcode table interpretation
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Correct 64-bit macros' ISA membership
2016-12-20  Maciej W. RozyckiMIPS16/opcodes: Correct I64/SDRASP opcode's ISA membership
2016-12-20  Andrew WatermanCorrect assembler mnemonic for RISC-V aqrl AMOs
2016-12-20  Andrew WatermanFix disassembly of RISC-V CSR instructions under -Mno...
2016-12-20  Andrew WatermanAdd canonical JALR for RISC-V
2016-12-20  Andrew WatermanRe-work RISC-V gas flags: now we just support -mabi...
2016-12-20  Andrew WatermanFormatting changes for RISC-V
2016-12-20  Alan ModraAdd opcodes RISC-V dependencies
2016-12-19  Maciej W. RozyckiMIPS/opcodes: Only examine ELF file structures if SYMTA...
2016-12-19  Maciej W. RozyckiMIPS/opcodes: Only call `bfd_mips_elf_get_abiflags...
2016-12-16  Nick CliftonFix compile time warning building arm-dis.c
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