ubsan: bfin: shift exponent is too large
[deliverable/binutils-gdb.git] / opcodes / aarch64-tbl.h
2019-12-05  Jan BeulichArm64: simplify Crypto arch extension handling
2019-11-11  Jan BeulichArm64: SVE2's smaxp/sminp require operands 1 and 3...
2019-11-07  Matthew Malcomson[gas][aarch64] Add the v8.6 Data Gathering Hint mnemoni...
2019-11-07  Matthew Malcomson[binutils][aarch64] Matrix Multiply extension enablemen...
2019-11-07  Matthew Malcomson[binutils][aarch64] Bfloat16 enablement [2/X]
2019-11-07  Matthew Malcomson[gas][aarch64] Armv8.6-a option [1/X]
2019-10-30  Delia BurduvModify the ARNM assembler to accept the omission of...
2019-07-02  Richard Sandiford[AArch64] Allow MOVPRFX to be used with FMOV
2019-07-02  Richard Sandiford[AArch64] Add missing C_MAX_ELEM flags for SVE conversions
2019-07-01  Matthew Malcomson[gas][aarch64][SVE2] Fix pmull{t,b} requirement on...
2019-05-09  Matthew Malcomson[binutils][aarch64] Add SVE2 instructions.
2019-05-09  Matthew Malcomson[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] New SVE_Zm4_11_INDEX operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] New SVE_ADDR_ZX operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
2019-05-09  Matthew Malcomson[binutils][aarch64] SVE2 feature extension flags.
2019-05-01  Sudakshina Das[BINUTILS, AArch64] Enable Transactional Memory Extension
2019-04-11  Sudakshina Das[BINUTILS, AArch64, 2/2] Update Store Allocation Tag...
2019-04-11  Sudakshina Das[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instruction
2019-02-07  Tamar ChristinaAArch64: Add verifier for By elem Single and Double...
2019-01-25  Sudi DasAArch64: Update encodings for stg, st2g, stzg and st2zg.
2019-01-25  Sudi DasAArch64: Add new STZGM instruction for Armv8.5-A Memory...
2019-01-25  Sudi DasAArch64: Remove ldgv and stgv instructions from Armv8...
2019-01-01  Alan ModraUpdate year range in copyright notice of binutils files
2018-12-03  Egeyar Bagcioglu[aarch64] - Only use MOV for disassembly when shifter...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 6/8] Add Tag getting instruction...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 5/8] Add Tag getting instruction...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 4/8] Add Tag setting instructions...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instruc...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 2/8] Add Tag generation instruction...
2018-11-12  Sudakshina Das[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging...
2018-10-09  Sudakshina Das[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction
2018-10-09  Sudakshina Das[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data...
2018-10-09  Sudakshina Das[PATCH, BINUTILS, AARCH64, 3/9] Add instruction SB...
2018-10-09  Sudakshina Das[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing...
2018-10-09  Sudakshina Das[PATCH, BINUTILS, AARCH64, 1/9] Add -march=armv8.5...
2018-10-03  Tamar ChristinaAArch64: Mark sve instructions that require MOVPRFX...
2018-07-12  Nick CliftonThis patch adds support for the SSBB and PSSBB speculat...
2018-07-12  Tamar ChristinaAdd remainder of Em16 restrictions for AArch64 gas.
2018-07-06  Tamar ChristinaFix SBO bit in disassembly mask for ldrah on AArch64.
2018-06-29  Tamar ChristinaFix AArch64 encodings for by element instructions.
2018-06-22  Tamar ChristinaCorrect negs aliasing on AArch64.
2018-06-08  Egeyar BagciogluPrevent undefined FMOV instructions being accepted...
2018-05-16  Tamar ChristinaFix disassembly mask for vector sdot on AArch64.
2018-05-15  Tamar ChristinaImplement Read/Write constraints on system registers...
2018-04-25  Tamar ChristinaFix the mask for the sqrdml(a|s)h instructions.
2018-03-28  Nick CliftonEnhance the AARCH64 assembler to support LDFF1xx instru...
2018-01-09  James GreenhalghAdd support for the AArch64's CSDB instruction.
2018-01-03  Alan ModraUpdate year range in copyright notice of binutils files
2017-12-19  Tamar ChristinaCorrect disassembly of dot product instructions.
2017-11-16  Tamar ChristinaAdd new AArch64 FP16 FM{A|S} instructions.
2017-11-16  Tamar ChristinaCorrect AArch64 crypto dependencies.
2017-11-16  Tamar ChristinaAdd assembler and disassembler support for the new...
2017-11-09  Tamar ChristinaAdd the operand encoding types for the new Armv8.2...
2017-11-09  Tamar ChristinaAdds the new Fields and Operand types for the new instr...
2017-11-09  Tamar ChristinaSplit the ARM Crypto ISA extensions for AES and SHA1...
2017-11-08  Nick CliftonSplit the AArch64 Crypto instructions for AES and SHA1...
2017-06-28  Tamar Christina[AArch64] Add dot product support for AArch64 to binutils
2017-04-21  Nick CliftonFix detection of illegal AArch64 opcodes that resemble...
2017-02-24  Richard Sandiford[AArch64] Additional SVE instructions
2017-02-24  Richard Sandiford[AArch64] Add a "compnum" feature
2017-01-04  Szabolcs Nagy[AArch64] Add separate feature flag for weaker release...
2017-01-02  Alan ModraUpdate year range in copyright notice of all files.
2016-12-13  Renlin Li[Binutils][AARCH64]Remove Cn register for coprocessor...
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 weaker release consistency load...
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 javascript floating-point convers...
2016-11-18  Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 combined pointer authentication...
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 PACGA instruction
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 single source PAC instructions
2016-11-11  Szabolcs Nagy[AArch64] Add ARMv8.3 instructions which are in the...
2016-09-30  Jiong Wang[AArch64] PR target/20553, fix opcode mask for SIMD...
2016-09-21  Richard Sandiford[AArch64][SVE 31/32] Add SVE instructions
2016-09-21  Richard Sandiford[AArch64][SVE 29/32] Add new SVE core & FP register...
2016-09-21  Richard Sandiford[AArch64][SVE 28/32] Add SVE FP immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 27/32] Add SVE integer immediate operands
2016-09-21  Richard Sandiford[AArch64][SVE 26/32] Add SVE MUL VL addressing modes
2016-09-21  Richard Sandiford[AArch64][SVE 25/32] Add support for SVE addressing...
2016-09-21  Richard Sandiford[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
2016-09-21  Richard Sandiford[AArch64][SVE 23/32] Add SVE pattern and prfop operands
2016-09-21  Richard Sandiford[AArch64][SVE 21/32] Add Zn and Pn registers
2016-09-21  Richard Sandiford[AArch64][SVE 20/32] Add support for tied operands
2016-09-21  Richard Sandiford[AArch64][SVE 16/32] Use specific insert/extract method...
2016-08-23  Richard Sandiford[AArch64] Add V8_2_INSN macro
2016-08-23  Richard Sandiford[AArch64] Make more use of CORE/FP/SIMD_INSN
2016-08-23  Richard Sandiford[AArch64] Add OP parameter to aarch64-tbl.h macros
2016-05-03  Szabolcs NagyFix generation of AArhc64 instruction table.
2016-04-28  Nick CliftonAdd support to AArch64 disassembler for verifying instr...
2016-03-18  Nick CliftonFix the disassembly of the AArch64's OOR instruction...
2016-01-01  Alan ModraCopyright update for binutils
2015-12-14  Matthew Wahab[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar...
2015-12-14  Matthew Wahab[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift...
2015-12-14  Matthew Wahab[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar...
2015-12-14  Matthew Wahab[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified...
2015-12-14  Matthew Wahab[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across...
2015-12-14  Matthew Wahab[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Eleme...
2015-12-14  Matthew Wahab[AArch64][PATCH 6/14] Support FP16 Vector Indexed Eleme...
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