2019-12-04 |
Jan Beulich | x86-64: accept 64-bit LFS/LGS/LSS forms with suffix... |
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2019-12-04 |
Jan Beulich | x86: drop some stray/bogus DefaultSize |
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2019-11-14 |
Jan Beulich | x86: drop redundant SYSCALL/SYSRET templates |
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2019-11-14 |
Jan Beulich | x86: fold individual Jump* attributes into a single... |
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2019-11-14 |
Jan Beulich | x86: make JumpAbsolute an insn attribute |
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2019-11-14 |
Jan Beulich | x86: make AnySize an insn attribute |
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2019-11-12 |
Jan Beulich | x86: fold EsSeg into IsString |
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2019-11-12 |
Jan Beulich | x86: eliminate ImmExt abuse |
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2019-11-12 |
Jan Beulich | x86: introduce operand type "instance" |
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2019-11-08 |
H.J. Lu | i386: Only check suffix in instruction mnemonic |
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2019-11-08 |
Jan Beulich | x86: convert RegMask and RegBND from bitfield to enumerator |
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2019-11-08 |
Jan Beulich | x86: convert RegSIMD and RegMMX from bitfield to enumerator |
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2019-11-08 |
Jan Beulich | x86: convert Control/Debug/Test from bitfield to enumerator |
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2019-11-08 |
Jan Beulich | x86: convert SReg from bitfield to enumerator |
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2019-11-08 |
Jan Beulich | x86: introduce operand type "class" |
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2019-11-07 |
Jan Beulich | x86: support further AMD Zen2 instructions |
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2019-11-07 |
Jan Beulich | x86/Intel: drop IgnoreSize from operand-less MOVSD... |
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2019-10-30 |
Jan Beulich | x86: re-do "shorthand" handling |
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2019-10-30 |
Jan Beulich | x86: drop stray W |
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2019-10-07 |
Jan Beulich | x86/Intel: correct MOVSD and CMPSD handling |
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2019-09-20 |
Jan Beulich | x86-64: fix handling of PUSH/POP of segment register |
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2019-08-07 |
Jan Beulich | x86: drop stray FloatMF |
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2019-07-16 |
Jan Beulich | x86: make RegMem an opcode modifier |
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2019-07-16 |
Jan Beulich | x86: fold SReg{2,3} |
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2019-07-01 |
Jan Beulich | x86: drop Vec_Imm4 |
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2019-07-01 |
Jan Beulich | x86: limit ImmExt abuse |
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2019-07-01 |
Jan Beulich | x86: optimize AND/OR with twice the same register |
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2019-07-01 |
Jan Beulich | x86-64: optimize certain commutative VEX-encoded insns |
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2019-07-01 |
Jan Beulich | x86: optimize EVEX packed integer logical instructions |
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2019-07-01 |
Jan Beulich | x86: add missing pseudo ops for VPCLMULQDQ ISA extension |
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2019-07-01 |
Jan Beulich | x86: drop bogus Disp8MemShift attributes |
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2019-06-25 |
Jan Beulich | x86: fix (dis)assembly of certain SSE2 insns in 16... |
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2019-06-25 |
Jan Beulich | x86-64: also optimize ANDQ with immediate fitting in... |
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2019-06-04 |
H.J. Lu | Enable Intel AVX512_VP2INTERSECT insn |
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2019-06-04 |
H.J. Lu | Add support for Intel ENQCMD[S] instructions |
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2019-05-28 |
H.J. Lu | x86: Add CheckRegSize to AVX512_BF16 instructions with... |
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2019-04-08 |
H.J. Lu | x86: Consolidate AVX512 BF16 entries in i386-opc.tbl |
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2019-04-05 |
Xuepeng Guo | x86: Support Intel AVX512 BF16 |
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2019-03-18 |
H.J. Lu | x86: Optimize EVEX vector load/store instructions |
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2019-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
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2018-11-06 |
Jan Beulich | x86: adjust {,E}VEX.W handling for PEXTR* / PINSR* |
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2018-11-06 |
Jan Beulich | x86: adjust {,E}VEX.W handling outside of 64-bit mode |
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2018-11-06 |
Jan Beulich | x86: fix various non-LIG templates |
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2018-11-06 |
Jan Beulich | x86: allow {store} to select alternative {,}PEXTRW... |
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2018-11-06 |
Jan Beulich | x86: add more VexWIG |
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2018-11-06 |
Jan Beulich | x86: XOP VPHADD* / VPHSUB* are VEX.W0 |
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2018-10-10 |
Jan Beulich | x86: fold Size{16,32,64} template attributes |
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2018-10-05 |
H.J. Lu | x86: Add Intel ENCLV to assembler and disassembler |
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2018-09-17 |
H.J. Lu | x86: Set EVex=2 on EVEX.128 only vmovd and vmovq |
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2018-09-17 |
H.J. Lu | x86: Set Vex=1 on VEX.128 only vmovd and vmovq |
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2018-09-17 |
H.J. Lu | x86: Replace VexW=3 with VexWIG |
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2018-09-16 |
H.J. Lu | x86: Set VexW=3 on AVX vrsqrtss |
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2018-09-15 |
H.J. Lu | x86: Set Vex=1 on VEX.128 only vmovq |
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2018-09-14 |
H.J. Lu | x86: Support VEX/EVEX WIG encoding |
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2018-09-14 |
Jan Beulich | x86: fold CRC32 templates |
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2018-09-13 |
H.J. Lu | x86: Remove VexW=1 from WIG VEX movq and vmovq |
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2018-09-13 |
H.J. Lu | i386: Update VexW field for VEX instructions |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from a few further insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512_4* insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512DQ insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512BW insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512VL insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512ER insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX512F insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SHA insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from XOP and SSE4a insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX2 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AVX insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from GNFI insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from AES/VAES insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSE4.2 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSE4.1 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSSE3 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSE3 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSE2 insns |
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2018-09-13 |
Jan Beulich | x86: drop bogus IgnoreSize from SSE insns |
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2018-09-13 |
Jan Beulich | x86: drop unnecessary {,No}Rex64 |
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2018-09-13 |
Jan Beulich | x86: also allow D on 3-operand insns |
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2018-09-13 |
Jan Beulich | x86: use D attribute also for SIMD templates |
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2018-08-11 |
H.J. Lu | x86: Add CpuCMOV and CpuFXSR |
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2018-08-03 |
Jan Beulich | x86: drop NoRex64 from {,v}pmov{s,z}x* |
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2018-07-31 |
Jan Beulich | x86: also optimize KXOR{D,Q} and KANDN{D,Q} |
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2018-07-31 |
Jan Beulich | x86: fold various AVX512 templates with so far differin... |
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2018-07-31 |
Jan Beulich | x86/Intel: correct permitted operand sizes for AVX512... |
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2018-07-24 |
Jan Beulich | x86-64: correct AVX512F vcvtsi2s{d,s} handling |
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2018-07-19 |
Jan Beulich | x86: fold narrowing VCVT* templates |
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2018-07-19 |
Jan Beulich | x86: fold VFPCLASSP{D,S} templates |
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2018-07-19 |
Jan Beulich | x86: fold various AVX512* templates |
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2018-07-19 |
Jan Beulich | x86: fold various AVX512DQ templates |
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2018-07-19 |
Jan Beulich | x86: fold various AVX512BW templates |
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2018-07-19 |
Jan Beulich | x86: fold various AVX512CD templates |
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2018-07-19 |
Jan Beulich | x86: fold various AVX512VL templates into their AVX512F... |
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2018-07-19 |
Jan Beulich | x86: pre-process opcodes table before parsing |
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2018-07-18 |
H.J. Lu | x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq |
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2018-07-11 |
Jan Beulich | x86: adjust monitor/mwait templates |
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2018-07-11 |
Jan Beulich | x86/Intel: accept memory operand size specifiers for... |
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2018-06-01 |
Jan Beulich | x86: fold MOV to/from segment register templates |
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2018-06-01 |
Jan Beulich | x86: don't emit REX.W for SLDT and STR |
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2018-06-01 |
Jan Beulich | x86/Intel: accept "oword ptr" for INVPCID |
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