| 2017-12-18 |
 Jan Beulich | x86: fold certain AVX and AVX2 templates |
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| 2017-12-18 |
Jan Beulich | x86: fold RegXMM/RegYMM/RegZMM into RegSIMD |
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| 2017-12-18 |
Jan Beulich | x86: replace Reg8, Reg16, Reg32, and Reg64 |
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| 2017-12-15 |
Jan Beulich | x86: drop stray CheckRegSize uses |
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| 2017-11-30 |
Jan Beulich | x86: derive DispN from BaseIndex |
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| 2017-11-30 |
Jan Beulich | x86: drop Vec_Disp8 |
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| 2017-11-23 |
 Igor Tsimbalist | Add Disp8MemShift for AVX512 VAES instructions. |
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| 2017-11-23 |
Jan Beulich | x86: correct UDn |
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| 2017-11-22 |
Igor Tsimbalist | Remove Vec_Disp8 field for vgf2p8mulb for AVX flavor. |
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| 2017-11-22 |
Igor Tsimbalist | Remove Vec_Disp8 from vpcompressb and vpexpandb. |
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| 2017-11-14 |
Jan Beulich | x86: add support for AVX-512 VPCMP*{B,W} pseudo-ops |
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| 2017-11-14 |
Jan Beulich | x86: string insns don't allow displacements |
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| 2017-11-13 |
Jan Beulich | x86: {f,}xsave64 / {f,}xrstor64 / xsaveopt64 should... |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel AVX512_BITALG instructions. |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel AVX512_VNNI instructions. |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel VPCLMULQDQ instruction. |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel VAES instructions. |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel GFNI instructions. |
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| 2017-10-23 |
Igor Tsimbalist | Enable Intel AVX512_VBMI2 instructions. |
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| 2017-06-21 |
 H.J. Lu | x86: CET v2.0: Update incssp and setssbsy |
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| 2017-06-21 |
H.J. Lu | x86: CET v2.0: Rename savessp to saveprevssp |
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| 2017-05-22 |
H.J. Lu | x86: Add NOTRACK prefix support |
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| 2017-03-09 |
H.J. Lu | X86: Add pseudo prefixes to control encoding |
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| 2017-03-09 |
H.J. Lu | Use CpuCET on rdsspq |
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| 2017-03-06 |
H.J. Lu | Add support for Intel CET instructions |
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| 2017-02-28 |
Jan Beulich | x86: fix handling of 64-bit operand size VPCMPESTR... |
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| 2017-01-12 |
Igor Tsimbalist | Enable Intel AVX512_VPOPCNTDQ instructions |
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| 2017-01-02 |
 Alan Modra | Update year range in copyright notice of all files. |
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| 2016-11-09 |
H.J. Lu | X86: Remove the .s suffix from EVEX vpextrw |
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| 2016-11-09 |
H.J. Lu | X86: Merge AVX512F vmovq |
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| 2016-11-02 |
Igor Tsimbalist | Enable Intel AVX512_4VNNIW instructions |
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| 2016-11-02 |
Igor Tsimbalist | Enable Intel AVX512_4FMAPS instructions |
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| 2016-10-21 |
H.J. Lu | X86: Remove pcommit instruction |
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| 2016-08-24 |
H.J. Lu | X86: Add ptwrite instruction |
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| 2016-07-01 |
Jan Beulich | x86: allow suffix-less movzw and 64-bit movzb |
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| 2016-07-01 |
Jan Beulich | x86: remove stray instruction attributes |
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| 2016-07-01 |
Jan Beulich | x86/Intel: fix operand checking for MOVSD |
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| 2016-06-03 |
H.J. Lu | Handle indirect branches for AMD64 and Intel64 |
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| 2016-05-27 |
H.J. Lu | Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 |
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| 2016-05-10 |
 Alexander Fomin | Enable Intel RDPID instruction. |
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| 2016-01-01 |
Alan Modra | Copyright update for binutils |
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| 2015-12-09 |
H.J. Lu | Implement Intel OSPKE instructions |
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| 2015-06-30 |
 Amit Pawar | Add support for monitorx/mwaitx instructions |
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| 2015-06-01 |
Jan Beulich | x86/Intel: accept mandated operand order for vcvt{... |
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| 2015-05-18 |
H.J. Lu | Remove Disp32 from AMD64 direct call/jmp |
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| 2015-05-15 |
H.J. Lu | Support AMD64/Intel ISAs in assembler/disassembler |
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| 2015-05-11 |
H.J. Lu | Remove Disp16|Disp32 from 64-bit direct branches |
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| 2015-03-17 |
 Ganesh Gopalasubra... | Add znver1 processor |
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| 2015-01-01 |
Alan Modra | ChangeLog rotatation and copyright year update |
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| 2014-11-17 |
 Ilya Tocar | Add AVX512VBMI instructions |
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| 2014-11-17 |
Ilya Tocar | Add AVX512IFMA instructions |
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| 2014-11-17 |
Ilya Tocar | Add pcommit instruction |
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| 2014-11-17 |
Ilya Tocar | Add clwb instruction |
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| 2014-07-22 |
Ilya Tocar | Add AVX512DQ instructions and their AVX512VL variants. |
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| 2014-07-22 |
Ilya Tocar | Add support for AVX512BW instructions and their AVX512V... |
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| 2014-07-22 |
Ilya Tocar | Add support for AVX512VL versions of AVX512CD instructions. |
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| 2014-07-22 |
Ilya Tocar | Add support for AVX512VL. Add AVX512VL versions of... |
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| 2014-04-04 |
Ilya Tocar | Add support for Intel SGX instructions |
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| 2014-03-20 |
Ilya Tocar | Fix memory size for gather/scatter instructions |
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| 2014-03-05 |
Alan Modra | Update copyright years |
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| 2014-02-25 |
Ilya Tocar | Remove bogus vcvtps2ph variant. |
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| 2014-02-21 |
Ilya Tocar | Add support for CPUID PREFETCHWT1 |
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| 2014-02-20 |
Ilya Tocar | Change cpu for vptestnmd and vptestnmq instructions. |
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| 2014-02-12 |
Ilya Tocar | Add clflushopt, xsaves, xsavec, xrstors |
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| 2013-10-12 |
H.J. Lu | Only allow 32-bit/64-bit registers for bndcl/bndcu... |
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| 2013-10-08 |
Jan Beulich | opcodes/ |
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| 2013-09-30 |
H.J. Lu | Add Size64 to movq/vmovq with Reg64 operand |
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| 2013-07-26 |
H.J. Lu | Add Intel AVX-512 support |
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| 2013-07-25 |
H.J. Lu | Support Intel SHA |
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| 2013-07-24 |
H.J. Lu | Support Intel MPX |
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| 2013-07-08 |
H.J. Lu | Replace Xmmword with Qword on cvttps2pi |
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| 2013-04-08 |
Jan Beulich | gas/testsuite/ |
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| 2013-02-19 |
H.J. Lu | Implement Intel SMAP instructions |
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| 2012-11-20 |
H.J. Lu | Fix opcode for 64-bit jecxz |
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| 2012-09-20 |
H.J. Lu | Replace CpuSSE3 with CpuCX16 for cmpxchg16b |
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| 2012-08-17 |
H.J. Lu | Add AMD btver1 and btver2 support |
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| 2012-08-07 |
Jan Beulich | There were several cases where the registers in the... |
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| 2012-07-31 |
Jan Beulich | VMOVNTDQA was both misplaced and improperly tagged... |
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| 2012-07-16 |
H.J. Lu | Implement RDRSEED, ADX and PRFCHW instructions |
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| 2012-07-02 |
 Roland McGrath | gas/testsuite/ |
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| 2012-06-22 |
Roland McGrath | gas/ |
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| 2012-06-22 |
Roland McGrath | gas/ |
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| 2012-02-08 |
H.J. Lu | Implement Intel Transactional Synchronization Extensions |
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| 2012-01-13 |
H.J. Lu | Add vmfunc |
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| 2011-08-01 |
H.J. Lu | Add Disp32S to 64bit call. |
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| 2011-06-30 |
H.J. Lu | Fix rorx in BMI2. |
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| 2011-06-10 |
H.J. Lu | Support AVX Programming Reference (June, 2011). |
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| 2011-01-17 |
 Quentin Neill | Add support for TBM instructions. |
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| 2011-01-05 |
H.J. Lu | Implement BMI instructions. |
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| 2010-10-14 |
H.J. Lu | Remove CheckRegSize from movq. |
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| 2010-10-14 |
H.J. Lu | Remove CheckRegSize from instructions with 0, 1 or... |
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| 2010-10-14 |
H.J. Lu | Add CheckRegSize to instructions which require register... |
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| 2010-08-06 |
H.J. Lu | Don't generate multi-byte NOPs for i686. |
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| 2010-08-06 |
H.J. Lu | Add Cpu186 to ud1/ud2/ud2a/ud2b. |
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| 2010-08-06 |
H.J. Lu | Add ud1 to x86. |
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| 2010-07-05 |
H.J. Lu | Replace rdrnd with rdrand. |
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| 2010-07-01 |
H.J. Lu | Support AVX Programming Reference (June, 2010) |
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| 2010-03-23 |
 Sebastian Pop | 2010-03-22 Sebastian Pop <sebastian.pop@amd.com> |
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| 2010-02-11 |
H.J. Lu | Update copyright. |
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| 2010-02-11 |
Sebastian Pop | 2010-02-10 Quentin Neill <quentin.neill@amd.com> |
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projects / deliverable / binutils-gdb.git / history
Jan Beulich
Igor Tsimbalist
H.J. Lu
Alan Modra
Alexander Fomin
Amit Pawar
Ilya Tocar
Roland McGrath
Quentin Neill
Sebastian Pop