x86: Accept Intel64 only instruction by default
[deliverable/binutils-gdb.git] / opcodes / i386-opc.tbl
2020-02-10  H.J. Lux86: Accept Intel64 only instruction by default
2020-01-30  Jan Beulichx86-64: honor vendor specifics for near RET
2020-01-30  Jan Beulichx86: drop further pointless/bogus DefaultSize
2020-01-27  H.J. Lux86-64: Properly encode and decode movsxd
2020-01-21  Jan Beulichx86: improve handling of insns with ambiguous operand...
2020-01-21  Jan Beulichx86: VCVTNEPS2BF16{X,Y} should permit broadcasting
2020-01-17  H.J. Lux86: Add {vex} pseudo prefix
2020-01-16  Jan Beulichx86: drop stale Vec_Imm4 related comment
2020-01-16  Jan Beulichx86: add a few more missing VexWIG
2020-01-16  Jan Beulichx86: VPEXTRQ/VPINSRQ are unavailable outside of 64...
2020-01-09  Jan Beulichx86: SYSENTER/SYSEXIT are unavailable in 64-bit mode...
2020-01-01  Alan ModraUpdate year range in copyright notice of binutils files
2019-12-27  Jan Beulichx86: consolidate Disp<NN> handling a little
2019-12-04  Jan Beulichx86-64: accept 64-bit LFS/LGS/LSS forms with suffix...
2019-12-04  Jan Beulichx86: drop some stray/bogus DefaultSize
2019-11-14  Jan Beulichx86: drop redundant SYSCALL/SYSRET templates
2019-11-14  Jan Beulichx86: fold individual Jump* attributes into a single...
2019-11-14  Jan Beulichx86: make JumpAbsolute an insn attribute
2019-11-14  Jan Beulichx86: make AnySize an insn attribute
2019-11-12  Jan Beulichx86: fold EsSeg into IsString
2019-11-12  Jan Beulichx86: eliminate ImmExt abuse
2019-11-12  Jan Beulichx86: introduce operand type "instance"
2019-11-08  H.J. Lui386: Only check suffix in instruction mnemonic
2019-11-08  Jan Beulichx86: convert RegMask and RegBND from bitfield to enumerator
2019-11-08  Jan Beulichx86: convert RegSIMD and RegMMX from bitfield to enumerator
2019-11-08  Jan Beulichx86: convert Control/Debug/Test from bitfield to enumerator
2019-11-08  Jan Beulichx86: convert SReg from bitfield to enumerator
2019-11-08  Jan Beulichx86: introduce operand type "class"
2019-11-07  Jan Beulichx86: support further AMD Zen2 instructions
2019-11-07  Jan Beulichx86/Intel: drop IgnoreSize from operand-less MOVSD...
2019-10-30  Jan Beulichx86: re-do "shorthand" handling
2019-10-30  Jan Beulichx86: drop stray W
2019-10-07  Jan Beulichx86/Intel: correct MOVSD and CMPSD handling
2019-09-20  Jan Beulichx86-64: fix handling of PUSH/POP of segment register
2019-08-07  Jan Beulichx86: drop stray FloatMF
2019-07-16  Jan Beulichx86: make RegMem an opcode modifier
2019-07-16  Jan Beulichx86: fold SReg{2,3}
2019-07-01  Jan Beulichx86: drop Vec_Imm4
2019-07-01  Jan Beulichx86: limit ImmExt abuse
2019-07-01  Jan Beulichx86: optimize AND/OR with twice the same register
2019-07-01  Jan Beulichx86-64: optimize certain commutative VEX-encoded insns
2019-07-01  Jan Beulichx86: optimize EVEX packed integer logical instructions
2019-07-01  Jan Beulichx86: add missing pseudo ops for VPCLMULQDQ ISA extension
2019-07-01  Jan Beulichx86: drop bogus Disp8MemShift attributes
2019-06-25  Jan Beulichx86: fix (dis)assembly of certain SSE2 insns in 16...
2019-06-25  Jan Beulichx86-64: also optimize ANDQ with immediate fitting in...
2019-06-04  H.J. LuEnable Intel AVX512_VP2INTERSECT insn
2019-06-04  H.J. LuAdd support for Intel ENQCMD[S] instructions
2019-05-28  H.J. Lux86: Add CheckRegSize to AVX512_BF16 instructions with...
2019-04-08  H.J. Lux86: Consolidate AVX512 BF16 entries in i386-opc.tbl
2019-04-05  Xuepeng Guox86: Support Intel AVX512 BF16
2019-03-18  H.J. Lux86: Optimize EVEX vector load/store instructions
2019-01-01  Alan ModraUpdate year range in copyright notice of binutils files
2018-11-06  Jan Beulichx86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
2018-11-06  Jan Beulichx86: adjust {,E}VEX.W handling outside of 64-bit mode
2018-11-06  Jan Beulichx86: fix various non-LIG templates
2018-11-06  Jan Beulichx86: allow {store} to select alternative {,}PEXTRW...
2018-11-06  Jan Beulichx86: add more VexWIG
2018-11-06  Jan Beulichx86: XOP VPHADD* / VPHSUB* are VEX.W0
2018-10-10  Jan Beulichx86: fold Size{16,32,64} template attributes
2018-10-05  H.J. Lux86: Add Intel ENCLV to assembler and disassembler
2018-09-17  H.J. Lux86: Set EVex=2 on EVEX.128 only vmovd and vmovq
2018-09-17  H.J. Lux86: Set Vex=1 on VEX.128 only vmovd and vmovq
2018-09-17  H.J. Lux86: Replace VexW=3 with VexWIG
2018-09-16  H.J. Lux86: Set VexW=3 on AVX vrsqrtss
2018-09-15  H.J. Lux86: Set Vex=1 on VEX.128 only vmovq
2018-09-14  H.J. Lux86: Support VEX/EVEX WIG encoding
2018-09-14  Jan Beulichx86: fold CRC32 templates
2018-09-13  H.J. Lux86: Remove VexW=1 from WIG VEX movq and vmovq
2018-09-13  H.J. Lui386: Update VexW field for VEX instructions
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from a few further insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512_4* insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512DQ insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512BW insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512VL insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512ER insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX512F insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SHA insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from XOP and SSE4a insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX2 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AVX insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from GNFI insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from PCLMUL/VPCLMUL insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from AES/VAES insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSE4.2 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSE4.1 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSSE3 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSE3 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSE2 insns
2018-09-13  Jan Beulichx86: drop bogus IgnoreSize from SSE insns
2018-09-13  Jan Beulichx86: drop unnecessary {,No}Rex64
2018-09-13  Jan Beulichx86: also allow D on 3-operand insns
2018-09-13  Jan Beulichx86: use D attribute also for SIMD templates
2018-08-11  H.J. Lux86: Add CpuCMOV and CpuFXSR
2018-08-03  Jan Beulichx86: drop NoRex64 from {,v}pmov{s,z}x*
2018-07-31  Jan Beulichx86: also optimize KXOR{D,Q} and KANDN{D,Q}
2018-07-31  Jan Beulichx86: fold various AVX512 templates with so far differin...
2018-07-31  Jan Beulichx86/Intel: correct permitted operand sizes for AVX512...
2018-07-24  Jan Beulichx86-64: correct AVX512F vcvtsi2s{d,s} handling
2018-07-19  Jan Beulichx86: fold narrowing VCVT* templates
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