Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same register
[deliverable/binutils-gdb.git] / opcodes / s12z-dis.c
2019-10-29  Nick CliftonFix array overruns in the S12Z disassembler.
2019-04-12  John DarringtonS12Z: opcodes: Replace "operator" with "optr".
2019-01-09  John DarringtonS12Z: Don't crash when disassembling invalid instructions.
2019-01-09  John DarringtonS12Z: Fix disassembly of indexed OPR operands with...
2019-01-03  John DarringtonS12Z: opcodes: Separate the decoding of operations...
2019-01-01  Alan ModraUpdate year range in copyright notice of binutils files
2018-12-18  Alan ModraInclude bfd_stdint.h in bfd.h
2018-11-21  John DarringtonS12Z opcodes: Fix bug disassembling certain shift instr...
2018-10-22  John DarringtonS12Z: Disassembly: Fallback to show the address if...
2018-08-18  John DarringtonOpcodes: (BRCLR / BRSET) Disassemble reserved codes...
2018-08-18  John DarringtonS12Z: Move opcode header to public include directory.
2018-07-09  Maciej W. RozyckiS12Z/opcodes: Correct a `reg' global shadowing error...
2018-05-18  John DarringtonAdd support for the Freescale s12z processor.
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