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Microblaze: Add support for handling TLS symbol suffixes and generating
[deliverable/binutils-gdb.git]
/
sim
/
bfin
/
bfin-sim.c
2012-04-09
Mike Frysinger
sim: bfin: fix ASTAT issues in immediate shifts
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2012-04-09
Mike Frysinger
sim: bfin: fix ASTAT/correctness issues with arithmetic...
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2012-04-09
Mike Frysinger
sim: bfin: more parallel insn checks
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2012-04-09
Mike Frysinger
sim: bfin: keep track of the exact position of parallel...
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2012-04-08
Mike Frysinger
sim: bfin: drop excess space in negation insn
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2012-04-01
Mike Frysinger
sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1...
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2012-04-01
Mike Frysinger
sim: bfin: simplify field width processing and fix...
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2012-03-19
Mike Frysinger
sim: bfin: fix corner case Logical shift issues
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2012-01-04
Joel Brobecker
Copyright year update in most files of the GDB Project.
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2011-09-29
Mike Frysinger
sim: bfin: use store buffer for VIT_MAX insns
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2011-06-18
Mike Frysinger
sim: bfin: set ASTAT AV/AVS when shifting accumulators...
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2011-06-18
Mike Frysinger
sim: bfin: do not touch ASTAT[V] when shifting accumulators
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2011-06-18
Mike Frysinger
sim: bfin: do not extend accumulator in LSHIFT insns
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2011-06-18
Mike Frysinger
sim: bfin: tweak saturation handling with TFU/FU modes...
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2011-06-18
Mike Frysinger
sim: bfin: handle large shift values with accumulator...
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2011-06-18
Mike Frysinger
sim: bfin: handle odd shift values with shift insns
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2011-06-18
Mike Frysinger
sim: bfin: fix M_IH saturation size
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2011-06-18
Mike Frysinger
sim: bfin: handle V/VS saturation in dsp mac insns
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2011-06-18
Mike Frysinger
sim: bfin: handle the MM flag in M_IU/M_TFU modes with...
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2011-06-18
Mike Frysinger
sim: bfin: fix sign extension in dsp insns with MM...
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2011-06-18
Mike Frysinger
sim: bfin: fix dsp insns IH saturation/rounding behavior
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2011-06-18
Mike Frysinger
sim: bfin: fix accumulator edge case saturation
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2011-05-14
Mike Frysinger
sim: bfin: allow pushing of SP
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2011-04-16
Mike Frysinger
sim: bfin: use store buffer with more 32bit insns
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2011-04-15
Mike Frysinger
sim: bfin: handle implicit DISALGNEXCPT with video...
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2011-03-29
Mike Frysinger
sim: bfin: fix sign extension with 16bit acc add insns
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2011-03-27
Mike Frysinger
sim: bfin: handle saturation with RND12 sub insns
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2011-03-26
Mike Frysinger
sim: bfin: add missing VS set with add/sub insns
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2011-03-24
Mike Frysinger
sim: bfin: update VIT_MAX behavior to match hardware...
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2011-03-24
Mike Frysinger
sim: bfin: always do 16bit sign extension with the...
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2011-03-24
Mike Frysinger
sim: bfin: update AV and AC ASTAT bits with acc negation
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2011-03-24
Mike Frysinger
sim: bfin: allow byteop[123]p src regs to be the same
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2011-03-15
Mike Frysinger
sim: bfin: handle AZ updates with 16bit adds/subs
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2011-03-15
Mike Frysinger
sim: bfin: skip acc/ASTAT updates for moves
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2011-03-15
Mike Frysinger
sim: bfin: handle AN (negative overflows) in dsp mult...
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2011-03-15
Mike Frysinger
sim: bfin: handle V overflows in dsp mult insns
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2011-03-15
Mike Frysinger
sim: bfin: decode ASTAT on failure
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2011-03-15
Mike Frysinger
sim: bfin: handle saturation with fract multiplications
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2011-03-06
Mike Frysinger
sim: bfin: new port
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