Arnd Bergmann [Thu, 25 Sep 2014 22:14:31 +0000 (00:14 +0200)]
Merge branch 'at91/soc' into next/soc
The soc2 branch is based on this cleanup:
* at91/soc:
ARM: at91: Remove the support for the RSI EWS board
ARM: at91: remove board file for Acme Systems Fox G20
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 25 Sep 2014 22:00:02 +0000 (00:00 +0200)]
Merge tag 'soc-part2-for-v3.18' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
Pull "part 2 of omap SoC changes" from Tony Lindgren:
Few hwmod changes to support upcoming 8250 driver with DMA,
start using the SRAM driver for some omaps, and update the
defconfig.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'soc-part2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Remove static iotable mappings for SRAM
ARM: OMAP4+: Move SRAM data to DT
ARM: AM335x: Get rid of unused sram init function
ARM: omap2plus_defconfig: Enable some display features
ARM: omap2plus_defconfig: Enable battery and reset drivers
ARM: omap2plus_defconfig: Add support for distros with systemd
ARM: omap2plus_defconfig: Add cpufreq to defconfig
ARM: omap2plus_defconfig: Shrink with savedefconfig
ARM: OMAP3: Use manual idle for UARTs because of DMA errata
ARM: OMAP2+: Add hwmod flag for HWMOD_RECONFIG_IO_CHAIN
Arnd Bergmann [Thu, 25 Sep 2014 21:48:18 +0000 (23:48 +0200)]
Merge tag 'bcm63138-v4' of github.com/brcm/linux into next/soc
Merge "ARM: BCM: Broadcom BCM63138 support" from Florian Fainelli:
This patchset adds very minimal support for the BCM63138 SoC which is
a xDSL SoC using a dual Cortex A9 CPU complex.
* tag 'bcm63138-v4' of http://github.com/brcm/linux:
MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
ARM: BCM63XX: add BCM963138DVT Reference platform DTS
ARM: BCM63XX: add BCM63138 minimal Device Tree
ARM: BCM63XX: add low-level UART debug support
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
Conflicts:
arch/arm/Kconfig.debug
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Thu, 25 Sep 2014 16:10:40 +0000 (18:10 +0200)]
Merge tag 'renesas-soc5-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Fifth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* r8a7740: Fix documentation error copied from elsewhere
* r8a7794: Reserve memory for CMA in a manner consistent to
other R-Car Gen2 SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc5-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740 legacy: Fix copied bug in comment
ARM: shmobile: r8a7794: Reserve memory as other R-Car Gen2 SoCs
Arnd Bergmann [Thu, 25 Sep 2014 16:06:05 +0000 (18:06 +0200)]
Merge tag 'pxa3xx-ssp-name' of https://git./linux/kernel/git/hzhuang1/linux into next/soc
Pull "fix PXA3xx SSP naming issue" from Haojian Zhuang:
It's imported by
972a55b62 ASoC: fix pxa-ssp compiling issue under mach-mmp from v3.5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'pxa3xx-ssp-name' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux:
ARM: pxa3xx: provide specific platform_devices for all ssp ports
ARM: pxa: ssp: provide platform_device_id for PXA3xx
Arnd Bergmann [Thu, 25 Sep 2014 15:53:39 +0000 (17:53 +0200)]
Merge tag 'tegra-for-3.18-soc' of git://git./linux/kernel/git/swarren/linux-tegra into next/soc
Pull "ARM: tegra: core SoC code changes for 3.18" from Stephen Warren:
the primary change here gets its address information from DT rather than
iomap.h. This removes one more user of iomap.h, and will help allow the
code to move to a location that can be shared between arch/arm and
arch/arm64.
An unused header file was also removed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: remove unused tegra_emc.h
ARM: tegra: Initialize flow controller from DT
of: Add NVIDIA Tegra flow controller bindings
Arnd Bergmann [Thu, 25 Sep 2014 15:42:57 +0000 (17:42 +0200)]
Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc
Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:
- PM support
- Fix L2 useless setting
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Remove useless L2C AUX setting
ARM: zynq: Rename 'zynq_platform_cpu_die'
ARM: zynq: Remove hotplug.c
ARM: zynq: Synchronise zynq_cpu_die/kill
ARM: zynq: cpuidle: Remove pointless code
ARM: zynq: Remove invalidate cache for cpu die
ARM: zynq: PM: Enable DDR clock stop
ARM: zynq: DT: Add DDRC node
Documentation: devicetree: Add binding for Synopsys DDR controller
ARM: zynq: PM: Enable A9 internal clock gating feature
Carlo Caione [Wed, 10 Sep 2014 20:16:59 +0000 (22:16 +0200)]
ARM: meson: add basic support for MesonX SoCs
This patch adds the basic machine file for the MesonX SoCs. Only Meson6
is populated.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Carlo Caione [Tue, 9 Sep 2014 19:38:00 +0000 (21:38 +0200)]
ARM: meson: debug: add debug UART for earlyprintk support
Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Vincent Stehlé [Thu, 21 Aug 2014 23:31:20 +0000 (01:31 +0200)]
irq: Export handle_fasteoi_irq
Export handle_fasteoi_irq to be able to use it in e.g. the Zynq gpio driver
since commit
6dd859508336 ("gpio: zynq: Fix IRQ handlers").
This fixes the following link issue:
ERROR: "handle_fasteoi_irq" [drivers/gpio/gpio-zynq.ko] undefined!
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Vincent Stehle <vincent.stehle@laposte.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: http://lkml.kernel.org/r/1408663880-29179-1-git-send-email-vincent.stehle@laposte.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Olof Johansson [Wed, 24 Sep 2014 18:27:17 +0000 (11:27 -0700)]
Merge tag 'imx-soc-3.18' of git://git./linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo:
The i.MX SoC updates for 3.18:
- Add initial devicetree support for i.MX1
- Support GPT per clock source from OSC for i.MX6
- A couple of parent selection corrections for i.MX6SL clock driver
- Support more chip revision for i.MX6
- Convert pr_warning to pr_warn
- Add exclusive gate clock support
- Add BYPASS support for i.MX6 PLL clocks
- Update i.MX6 clock tree for audio use case
- A couple of VF610 clock driver updates
* tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits)
ARM: imx_v6_v7_defconfig updates
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
arm: mach-imx: Convert pr_warning to pr_warn
ARM: imx: source gpt per clk from OSC for system timer
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: imx: fix register offset of pll7_usb_host gate clock
ARM: clk-imx6sl: refine clock tree for SSI
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
ARM: imx6sx: add BYPASS support for PLL clocks
ARM: imx6sl: add BYPASS support for PLL clocks
ARM: imx6q: add BYPASS support for PLL clocks
ARM: imx: add an exclusive gate clock type
ARM: clk-imx6q: refine clock tree for SSI
ARM: clk-imx6q: refine clock tree for ASRC
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
ARM: clk-imx6q: refine clock tree for ESAI
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
ARM: imx: clk-vf610: Add USBPHY clocks
ARM: imx: add cpufreq support for i.mx6sx
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 18:17:26 +0000 (11:17 -0700)]
Merge tag 'renesas-soc4-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18
* r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
* tag 'renesas-soc4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
Signed-off-by: Olof Johansson <olof@lixom.net>
Matthias Brugger [Mon, 18 Aug 2014 14:58:00 +0000 (16:58 +0200)]
ARM: mediatek: Add earlyprintk support for mt6589
Enable low-level debug for Mediatek mt6589 SoC on UART0.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Wei Xu [Wed, 24 Sep 2014 09:07:48 +0000 (17:07 +0800)]
ARM: hisi: Fix platmcpm compilation when ARMv6 is selected
When compiling with "ARCH=arm" and "allmodconfig",
with commit:
9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation
we will get:
/tmp/cc6DjYjT.s: Assembler messages:
/tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8'
/tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb '
Fix platmcpm compilation when ARMv6 is selected.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:21:54 +0000 (22:21 -0700)]
ARM: debug: fix alphanumerical order on debug uarts
HIP04 was added out of order, but so was the previous HISI debug uart
support as well. Minor reshuffling of order.
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:20:10 +0000 (22:20 -0700)]
Merge tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi into next/soc
Merge "pull request for hisilicon hip04 soc and D01 board updates" from Wei Xu:
ARM: mach-hisi: Hisilicon hip04 soc and D01 board updates for 3.18
- Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number from 2 to 4
- Enable MCPM on HiP04 SoC
- Enable 16 cores on HiP04 SoC
- Add platform & Fabric controller devicetree binding document for HiP04 SoC
- Add hip04.dtsi & hip04-d01.dts for hip04 SoC platform and D01 board
- Enable HiP04 SoC in both hi3xxx_defconfig & multi_v7_defconfig
- Add the support of Hisilicon HiP04 debug uart
* tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi:
ARM: debug: add HiP04 debug uart
ARM: config: enable hisilicon hip04
ARM: dts: add hip04 dts
document: dt: add the binding on HiP04
ARM: hisi: enable HiP04
ARM: hisi: enable MCPM implementation
ARM: mcpm: support 4 clusters
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:15:16 +0000 (22:15 -0700)]
Merge tag 'renesas-clk2-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman.
* Add r8a7740, sh73a0 SoCs to MSTP bindings
* tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:04:19 +0000 (22:04 -0700)]
Merge tag 'soc-for-v3.18' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
SoC related changes for omaps for v3.18 merge window:
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
ARM: dts: OMAP3+: Add PRM interrupt
ARM: omap: Remove stray ARCH_HAS_OPP references
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
ARM: AM437x: use pdata quirks for pinctrl information
ARM: DRA7: use pdata quirks for pinctrl information
ARM: OMAP5: use pdata quirks for pinctrl information
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
ARM: OMAP4+: PM: use only valid low power state for suspend
ARM: OMAP4+: PM: Make logic state programmable
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
...
Josef Holzmayr [Fri, 19 Sep 2014 11:02:26 +0000 (13:02 +0200)]
ARM: at91: Remove the support for the RSI EWS board
The platform is end of life/support and should not clutter
the mach-at91 directory with non-DT files. It is therefore
removed.
Signed-off-by: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Daniel Mack [Wed, 13 Aug 2014 19:59:19 +0000 (21:59 +0200)]
ARM: pxa3xx: provide specific platform_devices for all ssp ports
Currently, devices for SSP ports 1, 2 and 3 are registered as compatible
devices to pxa27x-ssp. While the actual IP core is comparable, there are
some subtle differences which users of the SSP ports address by looking at
the 'type' field.
By registering devices of type 'pxa27x-ssp', this 'type' field is
incorrectly set to PXA27x_SSP which confuses the users.
To fix this, provide specific ssp port plaform devices which use
'pxa3xx-ssp' as driver name, an instantiate them from pxa3xx.c.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Daniel Mack [Wed, 13 Aug 2014 19:59:18 +0000 (21:59 +0200)]
ARM: pxa: ssp: provide platform_device_id for PXA3xx
Provide an explicit match string for PXA3xx SSP ports.
Without this match string, SSP0/SSP1/SSP2 in PXA3xxx will be consided as
PXA27x SSP Port.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Rajendra Nayak [Wed, 10 Sep 2014 16:04:04 +0000 (11:04 -0500)]
ARM: OMAP4+: Remove static iotable mappings for SRAM
In order to handle errata I688, a page of sram was reserved by doing a
static iotable map. Now that we use gen_pool to manage sram, we can
completely remove all of these static mappings and use gen_pool_alloc()
to get the one page of sram space needed to implement errata I688.
omap_bus_sync will be NOP until SRAM initialization happens.
Suggested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rajendra Nayak [Wed, 10 Sep 2014 16:04:03 +0000 (11:04 -0500)]
ARM: OMAP4+: Move SRAM data to DT
Use drivers/misc/sram.c driver to manage SRAM on all DT only
OMAP platforms (am33xx, am43xx, omap4 and omap5) instead of
the existing private plat-omap/sram.c
Address and size related data is removed from mach-omap2/sram.c
and now passed to drivers/misc/sram.c from DT.
Users can hence use general purpose allocator apis instead of
OMAP private ones to manage and use SRAM.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rajendra Nayak [Wed, 10 Sep 2014 16:04:02 +0000 (11:04 -0500)]
ARM: AM335x: Get rid of unused sram init function
Remove the empty am33xx_sram_init() function.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 16:01:08 +0000 (09:01 -0700)]
ARM: omap2plus_defconfig: Enable some display features
Now that we have panel support for DT based booting,
let's make it usable and enable most things as modules.
Note that omap3 boards need also the ads7847 module for
the panel that we're now changing to a loadable module.
And n900 seems to require setting the brightness via
sysfs for acx565akm/brightness after modprobe of
panel_sony_acx565akm and omapfb.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 16:01:08 +0000 (09:01 -0700)]
ARM: omap2plus_defconfig: Enable battery and reset drivers
Since many omaps run on battery, we should have the battery
drivers enabled. Let's also enable the reset driver.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 16:01:08 +0000 (09:01 -0700)]
ARM: omap2plus_defconfig: Add support for distros with systemd
Some distros are now using systemd, so let's enable most of
what's recommended at:
http://cgit.freedesktop.org/systemd/systemd/tree/README
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 16:01:07 +0000 (09:01 -0700)]
ARM: omap2plus_defconfig: Add cpufreq to defconfig
Note that we can now use the CONFIG_GENERIC_CPUFREQ_CPU0,
so let's only enable that. Let's use CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND
as suggested by Nishant.
And also let's enable thermal as explained by Nishant Menon:
Many TI SoCs using Highest frequency is not really too nice of an idea for
long periods of time. And not everything is upstream to support things
optimially - example avs class 0, 1.5 ABB consolidation with cpufreq etc..
We definitely need thermal enabled as well for device safety needs.
[tony@atomide.com: updated per Nishant's suggestions]
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 16:01:07 +0000 (09:01 -0700)]
ARM: omap2plus_defconfig: Shrink with savedefconfig
This saves few lines and makes it easier to make patches
against omap2plus_defconfig.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 15:58:49 +0000 (08:58 -0700)]
ARM: OMAP3: Use manual idle for UARTs because of DMA errata
In sprz318f.pdf "Usage Note 2.7" says that UARTs cannot acknowledge
idle requests in smartidle mode when configured for DMA operations.
This prevents L4 from going idle. So let's use manual idle mode
instead.
Otherwise systems using Sebastian's 8250 patches with DMA will
never enter deeper idle states because of the errata above.
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Thu, 18 Sep 2014 15:58:28 +0000 (08:58 -0700)]
ARM: OMAP2+: Add hwmod flag for HWMOD_RECONFIG_IO_CHAIN
Commit
cc824534d4fe ("ARM: OMAP2+: hwmod: Rearm wake-up interrupts
for DT when MUSB is idled") fixed issues with hung UART wake-up
events by calling _reconfigure_io_chain() when MUSB is connected
or disconnected.
As pointed out by Paul Walmsley, we may need to also call
_reconfigure_io_chain() in other cases, so it should be a separate
flag. Let's add HWMOD_RECONFIG_IO_CHAIN as suggested by Paul.
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Florian Fainelli [Wed, 5 Mar 2014 02:14:58 +0000 (18:14 -0800)]
MAINTAINERS: add entry for the Broadcom BCM63xx ARM SoCs
Add a MAINTAINERS entry covering all the Broadcom BCM63xx ARM DSL SoCs
files along with the relevant git tree and mailing-list.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Fri, 21 Feb 2014 00:47:00 +0000 (16:47 -0800)]
ARM: BCM63XX: add BCM963138DVT Reference platform DTS
Add a DTS file for the Broadcom BCM963138DVT reference platform board
which leverages the bcm63138.dtsi SoC DTSi file.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Fri, 21 Feb 2014 00:11:28 +0000 (16:11 -0800)]
ARM: BCM63XX: add BCM63138 minimal Device Tree
Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:
- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)
Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Wed, 8 Jan 2014 17:19:50 +0000 (09:19 -0800)]
ARM: BCM63XX: add low-level UART debug support
Broadcom BCM63xx DSL SoCs have a different UART implementation for which
we need specially crafted low-level debug assembly code to support. Add
support for this using the standard definitions provided in
include/linux/serial_bcm63xx.h (shared with their MIPS counterparts).
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Florian Fainelli [Thu, 20 Feb 2014 23:53:13 +0000 (15:53 -0800)]
ARM: BCM63XX: add basic support for the Broadcom BCM63138 DSL SoC
This patch adds basic support for the Broadcom BCM63138 DSL SoC which is
using a dual-core Cortex A9 system. Add the very minimum required code
boot Linux on this SoC.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Geert Uytterhoeven [Tue, 16 Sep 2014 19:58:03 +0000 (21:58 +0200)]
ARM: shmobile: r8a7740 legacy: Fix copied bug in comment
The corresponding bug in pm-sh7372.c was fixed in commit
70fe7b24672a988f ("ARM: shmobile: Do not access sh7372 A4S domain
internals directly").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Nicolas Ferre [Mon, 15 Sep 2014 13:18:50 +0000 (15:18 +0200)]
ARM: at91: remove board file for Acme Systems Fox G20
As Acme Systems Fox G20 is available in Device Tree flavor and that we plan to
remove all the board files soon, we can remove this one without problem.
If you use this board, please use a DT-enabled at91sam9g20 kernel with
at91-foxg20.dts.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Sergio Tanzilli <tanzilli@acmesystems.it>
Michal Simek [Fri, 29 Aug 2014 14:08:58 +0000 (16:08 +0200)]
ARM: zynq: Remove useless L2C AUX setting
AUX setting has no effect that's why remove it.
Warning log:
L2C: platform provided aux values match the hardware, so
have no effect. Please remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:14 +0000 (14:19 -0700)]
ARM: zynq: Rename 'zynq_platform_cpu_die'
Match the naming pattern of all other SMP ops and rename
zynq_platform_cpu_die --> zynq_cpu_die.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:13 +0000 (14:19 -0700)]
ARM: zynq: Remove hotplug.c
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:12 +0000 (14:19 -0700)]
ARM: zynq: Synchronise zynq_cpu_die/kill
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1:
2f3edfd7e27ad4206acbc2ae99c9df5f46353024)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Daniel Lezcano [Tue, 2 Sep 2014 21:19:11 +0000 (14:19 -0700)]
ARM: zynq: cpuidle: Remove pointless code
The core is not powered down, it is pointless to call the cpu_pm notifiers and
switch to the global timer.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Daniel Lezcano [Tue, 2 Sep 2014 21:19:10 +0000 (14:19 -0700)]
ARM: zynq: Remove invalidate cache for cpu die
As there is no Power management unit on this board, it is not possible to power
down a core, just WFI is allowed. There is no point to invalidate the cache and
exit coherency.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:09 +0000 (14:19 -0700)]
ARM: zynq: PM: Enable DDR clock stop
The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:08 +0000 (14:19 -0700)]
ARM: zynq: DT: Add DDRC node
Add the DDR controller to the Zynq devicetree.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:07 +0000 (14:19 -0700)]
Documentation: devicetree: Add binding for Synopsys DDR controller
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:06 +0000 (14:19 -0700)]
ARM: zynq: PM: Enable A9 internal clock gating feature
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Magnus Damm [Mon, 15 Sep 2014 13:35:36 +0000 (22:35 +0900)]
ARM: shmobile: r8a7794: Reserve memory as other R-Car Gen2 SoCs
Other R-Car Gen2 SoCs such as r8a7790 and r8a7791 reserve
the top 256 MiB of memory for use with CMA. Adjust the
board-less r8a7794 code to do the same.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabio Estevam [Wed, 10 Sep 2014 02:40:41 +0000 (23:40 -0300)]
ARM: imx_v6_v7_defconfig updates
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by
default.
The fsl sai driver is used by the vf610-twr board, so let's enable it by
default.
simple-audio-card driver is used by the vf610-twr board, so let's enable it by
default.
Generated this patch by doing:
- make imx_v6_v7_defconfig
- make menuconfig and manually select options
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Fri, 5 Sep 2014 14:34:23 +0000 (11:34 -0300)]
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Joe Perches [Sat, 13 Sep 2014 18:31:15 +0000 (11:31 -0700)]
arm: mach-imx: Convert pr_warning to pr_warn
Use the more common pr_warn.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Thu, 11 Sep 2014 03:29:42 +0000 (11:29 +0800)]
ARM: imx: source gpt per clk from OSC for system timer
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Thu, 11 Sep 2014 03:29:40 +0000 (11:29 +0800)]
ARM: imx: add gpt_3m clk for i.mx6qdl
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Fri, 12 Sep 2014 02:40:28 +0000 (10:40 +0800)]
ARM: imx: fix register offset of pll7_usb_host gate clock
There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Tue, 9 Sep 2014 09:13:25 +0000 (17:13 +0800)]
ARM: clk-imx6sl: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Tue, 26 Aug 2014 15:06:33 +0000 (23:06 +0800)]
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 07:15:57 +0000 (15:15 +0800)]
ARM: imx6sx: add BYPASS support for PLL clocks
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 06:29:53 +0000 (14:29 +0800)]
ARM: imx6sl: add BYPASS support for PLL clocks
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 06:17:48 +0000 (14:17 +0800)]
ARM: imx6q: add BYPASS support for PLL clocks
The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Tue, 26 Aug 2014 07:06:33 +0000 (15:06 +0800)]
ARM: imx: add an exclusive gate clock type
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Thu, 4 Sep 2014 09:48:59 +0000 (17:48 +0800)]
ARM: clk-imx6q: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Thu, 4 Sep 2014 09:48:58 +0000 (17:48 +0800)]
ARM: clk-imx6q: refine clock tree for ASRC
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share
the same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fancy Fang [Thu, 4 Sep 2014 08:33:12 +0000 (16:33 +0800)]
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Fri, 8 Aug 2014 07:02:47 +0000 (15:02 +0800)]
ARM: clk-imx6q: refine clock tree for ESAI
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename
'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'.
Make the clock for ESAI more clear and align them with imx6sx.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Tue, 19 Aug 2014 18:21:12 +0000 (15:21 -0300)]
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Tue, 19 Aug 2014 18:21:11 +0000 (15:21 -0300)]
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
Currently csi_lcdif_sels[] is a shared array for the providing the possible
clock parents for csi and lcdif blocks.
This is not correct, as csi and lcdif do not share the same clock parents.
Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in
order to describe the parents correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:12 +0000 (22:07 +0200)]
ARM: imx: clk-vf610: Add USBPHY clocks
This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.
Acked-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Wed, 25 Jun 2014 09:10:12 +0000 (17:10 +0800)]
ARM: imx: add cpufreq support for i.mx6sx
Add cpufreq support for i.MX6SX, using common
i.MX6Q cpufreq driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Tue, 29 Jul 2014 14:20:28 +0000 (16:20 +0200)]
ARM: imx: clk-vf610: introduce clks_init_on
At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).
To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.
With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Alexander Shiyan [Sat, 26 Jul 2014 09:45:28 +0000 (13:45 +0400)]
ARM: i.MX1: Add devicetree support
This patch adds basic devicetree support for i.MX1 based SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Jason Liu [Tue, 5 Nov 2013 04:03:18 +0000 (12:03 +0800)]
ARM: i.MX6: add more chip revision support
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Arnd Bergmann [Thu, 11 Sep 2014 07:45:18 +0000 (09:45 +0200)]
Merge tag 'renesas-dt-timers2-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Second Round of Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* kzm9g-reference: Enable CMT1 in device tree
* Use SoC-specific timer compat strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree
ARM: shmobile: sh73a0: Add CMT1 device to DT
ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string
ARM: shmobile: r8a7779: Use SoC-specific TMU compat string
ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string
ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string
ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
Simon Horman [Wed, 10 Sep 2014 00:43:31 +0000 (09:43 +0900)]
ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
The r8a7794 support is always compiled using ARCH_MULTIPLATFORM which
selects USE_OF. So #ifdef CONFIG_USE_OF is unnecessary.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabio Estevam [Tue, 9 Sep 2014 17:43:10 +0000 (14:43 -0300)]
ARM: imx: Remove mach-mxt_td60 board file
All the current support of mach-mxt_td60 board can be converted to devicetree.
Remove the board file.
Cc: Alan Carvalho de Assis <acassis@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Nishanth Menon [Tue, 9 Sep 2014 17:15:33 +0000 (12:15 -0500)]
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures.
These have been enabled in the previous patches, however, this also
means that OMAP5 or DRA7 only builds also need to build OMAP4 logic.
Update to reuse OMAP4 logic.
This fixes the 'undefined reference to 'omap4_pm_init_early'' in
OMAP5 or DRA7 only builds.
Fixes: 6af16a1dac5465c ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization")
Fixes: 628ed4717000789 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Ulrich Hecht [Tue, 2 Sep 2014 09:13:04 +0000 (11:13 +0200)]
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Arnd Bergmann [Tue, 9 Sep 2014 15:09:35 +0000 (17:09 +0200)]
Merge tag 'renesas-soc3-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Initial r8a7794 SoC support
ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
Arnd Bergmann [Tue, 9 Sep 2014 15:07:30 +0000 (17:07 +0200)]
Merge tag 'renesas-r8a7740-multiplatform-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC r8a7740 Multiplatform Updates for v3.18" from Simon Horman:
* Enable multiplatform support for r8a7740 SoC and remove
its DT-reference C board DTS files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-r8a7740-multiplatform-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: armadillo800eva reference: Remove DTS
ARM: shmobile: armadillo800eva reference: Remove C board code
ARM: shmobile: r8a7740: Add restart callback
ARM: shmobile: armadillo800eva: Build DTS for multiplatform
ARM: shmobile: armadillo800eva: Sync DTS
ARM: shmobile: r8a7740: Multiplatform support
Ulrich Hecht [Mon, 8 Sep 2014 00:57:08 +0000 (09:57 +0900)]
ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ulrich Hecht [Mon, 8 Sep 2014 00:57:06 +0000 (09:57 +0900)]
ARM: shmobile: sh73a0: Add CMT1 device to DT
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:44 +0000 (09:27 +0900)]
ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:48 +0000 (09:27 +0900)]
ARM: shmobile: r8a7779: Use SoC-specific TMU compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7779 TMU
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:46 +0000 (09:27 +0900)]
ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7791 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:47 +0000 (09:27 +0900)]
ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r7s72100 MTU2
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:45 +0000 (09:27 +0900)]
ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7790 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 9 Sep 2014 02:50:00 +0000 (11:50 +0900)]
Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-for-v3.18
Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Nishanth Menon [Fri, 22 Aug 2014 14:03:50 +0000 (09:03 -0500)]
ARM: dts: OMAP3+: Add PRM interrupt
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark Brown [Sat, 6 Sep 2014 10:14:16 +0000 (11:14 +0100)]
ARM: omap: Remove stray ARCH_HAS_OPP references
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rajendra Nayak [Fri, 22 Aug 2014 14:02:34 +0000 (09:02 -0500)]
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Mon, 8 Sep 2014 22:20:15 +0000 (15:20 -0700)]
Merge branch 'pull/v3.18/for-omap-soc' of https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
Tony Lindgren [Mon, 8 Sep 2014 22:04:24 +0000 (15:04 -0700)]
Merge branch 'pull/v3.18/powerdomain-fixes' of https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
Santosh Shilimkar [Tue, 20 May 2014 21:19:23 +0000 (16:19 -0500)]
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Mon, 27 May 2013 10:16:44 +0000 (15:46 +0530)]
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Fri, 6 Jun 2014 22:30:43 +0000 (17:30 -0500)]
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Fri, 3 May 2013 10:04:40 +0000 (15:34 +0530)]
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Thu, 12 Apr 2012 11:31:52 +0000 (17:01 +0530)]
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Fri, 8 Feb 2013 11:37:31 +0000 (17:07 +0530)]
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Wed, 6 Feb 2013 10:21:45 +0000 (15:51 +0530)]
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Wed, 6 Feb 2013 14:09:07 +0000 (19:39 +0530)]
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
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