Linus Walleij [Fri, 30 May 2014 07:52:43 +0000 (09:52 +0200)]
pinctrl: sirf: fix a bad conflict resolution
Commit
294d1351ff47726f0f110b88e816cbafe89512fb
"pinctrl: sirf: switch to using allocated state container"
caused a build conflict due to a bad conflict resolution
when cherry-picking the patch. Fix it up.
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Gross [Mon, 12 May 2014 22:16:08 +0000 (17:16 -0500)]
pinctrl: msm: Add more MSM8X74 pin definitions
This patch adds pin definitiones for the MSM8x74 TLMM.
New definitions include:
BLSP devices (I2C, UART, SPI, and UIM), mi2s, gp clk,
pdm, gcc clk, cci_timer, cci_i2c, cam_clk, hsic, tsif,
sdc3, sdc4, and other assorted pins.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Acked-By: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kumar Gala [Fri, 9 May 2014 18:08:25 +0000 (13:08 -0500)]
pinctrl: qcom: ipq8064: Fix naming convention
Drop underscore in spdif_groups to match all other groups.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Reviewed-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bjorn Andersson [Tue, 27 May 2014 20:47:55 +0000 (13:47 -0700)]
pinctrl: msm: Add missing sdc1 and sdc3 groups
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Wed, 23 Apr 2014 21:08:02 +0000 (23:08 +0200)]
pinctrl: sirf: switch to using allocated state container
This rewrites the SIRF pinctrl driver to allocate a state container
for the GPIO chip, just as is done for the pin controller, and
use the gpiochip_add_pin_range() to add the range from the gpiochip
side rather than adding the range from the pinctrl side.
All resulting changes are done in order to pass around a state
container rather than refer to a static global object.
Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Ivan T. Ivanov [Tue, 27 May 2014 06:27:36 +0000 (09:27 +0300)]
pinctrl: Enable "power-source" to be extracted from DT files
Add "power-source" property to generic options used for DT parsing files.
This enables drivers, which use generic pin configurations, to get the
value passed to this property.
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Mon, 26 May 2014 07:47:56 +0000 (09:47 +0200)]
pinctrl: sunxi: create irq/pin mapping during init
The irq/pin mapping is used to lookup the pin to mux to the irq
function when the irq is enabled. It is created when gpio_to_irq
is called. Creating the mapping during init allows us to map the
interrupts directly from the device tree.
Originally the IRQ to pin mapping was created when gpio_to_irq
was called with a GPIO handle. The mapping in turn is used to mux
the pin into EINT mode.
If the mapping is created during gpio_to_irq, we can't use the
interrupts directly, i.e. through the DT with "interrupts = <&pio A 4>".
Instead we'd have to use "gpios = <&pio A B>", then pass the gpio
through to gpio_to_irq.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Benoit Taine [Mon, 26 May 2014 15:21:27 +0000 (17:21 +0200)]
pinctrl: pinconf-generic: Use kmemdup instead of kmalloc + memcpy
This issue was reported by coccicheck using the semantic patch
at scripts/coccinelle/api/memdup.cocci
Signed-off-by: Benoit Taine <benoit.taine@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jingoo Han [Tue, 27 May 2014 06:29:17 +0000 (15:29 +0900)]
pinctrl: berlin: Use devm_ioremap_resource()
Use devm_ioremap_resource() because devm_request_and_ioremap() is
obsoleted by devm_ioremap_resource().
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Barry Song [Sun, 25 May 2014 08:54:23 +0000 (16:54 +0800)]
pinctrl: sirf: fix typo for GPIO bank number
The patch
7420d2d09b12: "pinctrl: sirf: switch driver to use gpiolib
irqchip helpers" from Apr 15, 2014, leads to the following static
checker warning:
drivers/pinctrl/sirf/pinctrl-sirf.c:578 sirfsoc_gpio_handle_irq()
warn: buffer overflow 'sgpio_chip.sgpio_bank' 5 <= 31
Cc: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Fri, 23 May 2014 18:50:43 +0000 (20:50 +0200)]
pinctrl: sunxi: depend on RESET_CONTROLLER
The A31 R_PIO driver depends on the reset framework in a mandatory way. Express
this by adding a depends on the reset framework in Kconfig
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Chen-Yu Tsai [Thu, 22 May 2014 15:20:55 +0000 (23:20 +0800)]
pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.
This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Anson Huang [Mon, 12 May 2014 15:10:35 +0000 (23:10 +0800)]
pinctrl: add pinctrl driver for imx6sx
Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexander Stein [Thu, 24 Apr 2014 17:55:39 +0000 (19:55 +0200)]
pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
With commit
80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 29 Apr 2014 18:00:40 +0000 (11:00 -0700)]
pinctrl: msm: switch to using generic GPIO irqchip helpers
This switches the Qualcomm MSM pin control driver over to using
the generic GPIO irqchip helpers.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Thu, 22 May 2014 14:25:27 +0000 (16:25 +0200)]
pinctrl: sunxi: Fix multiple registration issue
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.
Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Thu, 22 May 2014 14:47:12 +0000 (16:47 +0200)]
pinctrl: sunxi: Fix recursive dependency
Fix the following configuration error:
drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected!
drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10
drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI
Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI
one.
We still need to keep PINCTRL_SUNXI at the moment in order to preserve
bisectability. Indeed, during that merge window, we also introduced the
MACH_SUN* symbols. Since it's going through different trees, we can't rely on
the fact that the options will be there, while ARCH_SUNXI still select
PINCTRL_SUNXI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:32 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2CD pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:31 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2 pinctrl driver
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:30 +0000 (19:36 +0200)]
pinctrl: berlin: add the BG2Q pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Tenart [Mon, 19 May 2014 17:36:29 +0000 (19:36 +0200)]
pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs
The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.
Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:
Group Modes Offset Base Offset LSB Bit Width
GSM12 3 sm_base 0x40 0x10 0x2
Ball Group Mode 0 Mode 1 Mode 2
BK4 GSM12 UART0_RX IrDA0_RX GPIO9
BH6 GSM12 UART0_TX IrDA0_TX GPIO10
So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &=
ff3fffff.
As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Mika Westerberg [Fri, 16 May 2014 09:18:29 +0000 (12:18 +0300)]
pinctrl: baytrail: Add pull type, strength and open drain to debugfs output
In case of resolving power management or similar issues it might be useful
to have these properties included in the debugfs output.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jin Yao [Thu, 15 May 2014 15:28:47 +0000 (18:28 +0300)]
pinctrl: baytrail: Register GPIO chip after chip->to_irq is set
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event
handlers thus preventing any ACPI GPIO triggered events. Solve this by
calling gpiochip_add() after we have set up drivers chip->to_irq hook.
Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jin Yao [Thu, 15 May 2014 15:28:46 +0000 (18:28 +0300)]
pinctrl: baytrail: Add back Baytrail-T ACPI ID
Now that the x86 dynamic IRQ allocation problem has been resolved with
commmit
62a08ae2a576 (genirq: x86: Ensure that dynamic irq allocation does
not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver.
This makes the driver to work on Asus T100 where it is needed for several
things like ACPI GPIO events and SD card detection.
References: https://bugzilla.kernel.org/show_bug.cgi?id=68291
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Magnus Damm [Tue, 13 May 2014 11:37:49 +0000 (13:37 +0200)]
pinctrl: sh-pfc: r8a73a4: Allow Multiplatform Build
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed
to enable r8a73a4 Multiplatform support.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Magnus Damm [Tue, 13 May 2014 11:37:48 +0000 (13:37 +0200)]
pinctrl: sh-pfc: sh73a0: Allow Multiplatform Build
Add #ifdefs to allow sh73a0 Multiplatform build. Needed
to enable sh73a0 Multiplatform support.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Magnus Damm [Tue, 13 May 2014 11:37:47 +0000 (13:37 +0200)]
pinctrl: sh-pfc: r8a7740: Allow Multiplatform Build
Add #ifdefs to allow r8a7740 Multiplatform build. Needed
to enable r8a7740 Multiplatform support.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Laurent Pinchart [Tue, 13 May 2014 11:37:46 +0000 (13:37 +0200)]
pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatform
In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.
This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime Ripard [Tue, 13 May 2014 15:23:17 +0000 (17:23 +0200)]
pinctrl: sunxi: Enable the pinctrl Kconfig options by default
Enable the freshly introduced Kconfig options whenever their matching
architecture is enabled.
Since the Kconfig symbols for these machines are going through a different
tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig.
It should be removed eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 12:00:11 +0000 (14:00 +0200)]
dt-bindings: adapt rockchip-pinctrl doc to changed bindings
Introduce the syscons for grf and pmu and deprecate the previous register
areas.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:59:51 +0000 (13:59 +0200)]
pinctrl: rockchip: base regmap supplied by a syscon
This allows the basic registers of the general register files to be supplied
by a syscon instead of being mapped locally.
The GRF registers contain a lot more than pinctrl functions like dma, usb-phy
and general soc control and status registers, intermixed with the iomux, pull
and drive-strength registers.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:59:30 +0000 (13:59 +0200)]
pinctrl: rockchip: only map bank0-pull-region when pmu regmap missing
When the pmu registers are supplied through a syscon regmap we do not need
to map the registers ourself.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:59:09 +0000 (13:59 +0200)]
pinctrl: rockchip: let pmu registers be supplied by a syscon
Currently the pmu registers containing pin pull settings on the rk3188 are mapped
locally when bank0 is instantiated. Add an alternative that can resolve the pmu
from a syscon phandle.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:58:46 +0000 (13:58 +0200)]
pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_data
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because
later on we need to check a value from it when registering the gpio banks.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:58:20 +0000 (13:58 +0200)]
pinctrl: rockchip: use regmaps instead of raw mappings
This allows us to use syscons in the future.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Mon, 5 May 2014 11:58:00 +0000 (13:58 +0200)]
pinctrl: rockchip: do not require 2nd register area
Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.
The now deprecated register is still supported though.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Fri, 9 May 2014 06:47:16 +0000 (08:47 +0200)]
Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into devel
Pinctrl cleanup and reworks for 3.16
This serie of patch:
- Moves the Allwinner pinctrl driver to a folder of its own
- removes the sunxi-pinctrl-pins header, and split the driver into a core
one, with all the logic, and smaller drivers, one for each SoC, that
declare the pins, and will provide to the core the set of pins.
- And does a few cleanups here and there.
Maxime Ripard [Sat, 26 Apr 2014 20:28:54 +0000 (22:28 +0200)]
pinctrl: sunxi: Move the reset handling functions out of the core
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.
Move the reset functions out of the core and in the driver, where they can be
made mandatory.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sat, 26 Apr 2014 15:06:57 +0000 (17:06 +0200)]
pinctrl: sunxi: Introduce per-driver Kconfig options
Add one Kconfig option for each driver. This will allow to better control which
driver is enabled, instead of having either all or nothing.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be.
This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.
We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:12:50 +0000 (20:12 +0200)]
pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 18:10:41 +0000 (20:10 +0200)]
pinctrl: sunxi: Libraryse the driver
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sat, 26 Apr 2014 19:59:50 +0000 (21:59 +0200)]
pinctrl: sunxi: Switch to devm_ioremap_resource
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Thu, 24 Apr 2014 14:06:52 +0000 (16:06 +0200)]
pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 16:53:02 +0000 (18:53 +0200)]
pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory
This will allow to create numerous files without crippling the main pinctrl
directory.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Sat, 26 Apr 2014 18:11:47 +0000 (20:11 +0200)]
pinctrl: sunxi: Drop unused structure members
The ranges and nranges were never used. Remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime Ripard [Fri, 18 Apr 2014 17:34:07 +0000 (19:34 +0200)]
pinctrl: sunxi: Add const qualifier to the pin descriptor
The pins description structure were declared as const, but the of_device_id
data magic was losing it silently.
Make sure we have it on both sides.
And now that we're using const, we can also remove the useless cast in probe.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Andy Gross [Fri, 25 Apr 2014 20:41:55 +0000 (15:41 -0500)]
pinctrl: qcom: Correct name for pin 0
Fix copy/paste error in pinctrl_pin_desc for pin 0.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Thomas Petazzoni [Tue, 22 Apr 2014 21:26:07 +0000 (23:26 +0200)]
pinctrl: mvebu: new driver for Orion platforms
This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Wed, 23 Apr 2014 12:28:59 +0000 (14:28 +0200)]
pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handling
In some cases it is nice to be able to simply control a gpio output
via the PIN_CONFIG_OUTPUT option without having a driver control it.
Thus add support for it to the rockchip pinctrl driver.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Heiko Stübner [Wed, 23 Apr 2014 12:27:51 +0000 (14:27 +0200)]
pinctrl: rockchip: return a complete config in pinconf_get
Till now pinconf_get only set the argument value into the config parameter
effectively removing the actual config param value. As other pinctrl drivers
do, it might be nicer to keep the config param intact.
Therefore construct a real pinconfig value from param and arg in pinconf_get
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 15 Apr 2014 06:43:47 +0000 (14:43 +0800)]
pinctrl: sirf: switch driver to use gpiolib irqchip helpers
This switches the SiRF pinctrl driver over to using the gpiolib
irqchip helpers simplifying some of the code.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Barry Song [Tue, 15 Apr 2014 06:43:46 +0000 (14:43 +0800)]
pinctrl: sirf: wrap all gpio banks into one gpio_chip
all gpio banks are in one chip, that makes software clean in mapping
irq and gpio.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 8 Apr 2014 08:59:29 +0000 (10:59 +0200)]
pinctrl: sirf: rename inlined accessor
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is
not converting an irqchip to a bank but converts a gpiochip
to a bank so rename it sirfsoc_gpiochip_to_bank().
Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Gross [Tue, 15 Apr 2014 03:10:36 +0000 (22:10 -0500)]
dt: Document Qualcomm IPQ8064 pinctrl binding
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Gross [Tue, 15 Apr 2014 03:10:35 +0000 (22:10 -0500)]
pinctrl: qcom: Add definitions for IPQ8064
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.
Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Tue, 22 Apr 2014 13:38:06 +0000 (15:38 +0200)]
pinctrl: sunxi: list all pinctrl compatible strings
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tomasz Figa [Mon, 14 Apr 2014 01:45:47 +0000 (10:45 +0900)]
pinctrl: exynos: Add driver data for Exynos3250
This patch adds driver data (bank list and EINT layout) for Exynos3250
to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output
ports. There are 23 general port groups.
Changes from v1:
- Add signed-off of sender
- Post only separated patch for pinctrl from following patchset(v1)
: https://lkml.org/lkml/2014/4/10/286
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexander Stein [Mon, 14 Apr 2014 18:53:08 +0000 (20:53 +0200)]
pinctrl/at91: Fix mask creation in at91_gpio_dbg_show
pin_to_mask expects a bank pin number. So do not add the chip base.
Without that patch cat /sys/kernel/debug/gpio looks like that:
GPIOs 0-31, platform/
fffff200.gpio,
fffff200.gpio:
[spi32766.0] GPIOfffff200.gpio5: [gpio] set
[ads7846_pendown] GPIOfffff200.gpio15: [gpio] set
[ohci_vbus] GPIOfffff200.gpio21: [gpio] set
[ohci_vbus] GPIOfffff200.gpio24: [gpio] set
[button1] GPIOfffff200.gpio28: [gpio] clear
[button2] GPIOfffff200.gpio29: [gpio] clear
GPIOs 32-63, platform/
fffff400.gpio,
fffff400.gpio:
[sda] GPIOfffff400.gpio4: [periph A]
[scl] GPIOfffff400.gpio5: [periph A]
[spi32766.3] GPIOfffff400.gpio11: [periph A]
[error] GPIOfffff400.gpio22: [periph A]
[run] GPIOfffff400.gpio23: [periph A]
GPIOs 64-95, platform/
fffff600.gpio,
fffff600.gpio:
[reset_pin] GPIOfffff600.gpio29: [periph A]
GPIOs 96-127, platform/
fffff800.gpio,
fffff800.gpio:
[led1] GPIOfffff800.gpio5: [periph A]
[led2] GPIOfffff800.gpio6: [periph A]
[led3] GPIOfffff800.gpio7: [periph A]
[led4] GPIOfffff800.gpio8: [periph A]
GPIOs 128-159, platform/
fffffa00.gpio,
fffffa00.gpio:
[button3] GPIOfffffa00.gpio10: [periph A]
[button4] GPIOfffffa00.gpio12: [periph A]
Note that every bank despite bank 0 only shows "periph A" which are
obviously used as GPIOs.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Alexander Stein [Tue, 15 Apr 2014 20:09:41 +0000 (22:09 +0200)]
pinctrl/at91: convert driver to use gpiolib irqchip
This converts the AT91 pin control driver to register its
chained irq handler and irqchip using the helpers in the
gpiolib core.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Tue, 15 Apr 2014 17:02:03 +0000 (11:02 -0600)]
pinctrl: tegra: add missing kerneldoc
The kerneldoc for struct tegra_pingroup didn't describe all of the fields
in the struct. Add some extra kerneldoc to fix that.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Mon, 14 Apr 2014 21:33:42 +0000 (15:33 -0600)]
pinctrl: tegra: print better error messages
When an attempt is made to configure an unsupported option on a pin,
print the DT property name of that option, so it's easier to debug
what the problem is.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Mon, 14 Apr 2014 21:33:41 +0000 (15:33 -0600)]
pinctrl: tegra: reduce size of data table fields
The range of npins and function ID values is small enough to fit into a
u8. Use this type rather than unsigned to shrink the pinmux data tables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Mon, 14 Apr 2014 21:33:40 +0000 (15:33 -0600)]
pinctrl: tegra: remove fsafe from data tables
The fsafe value in the pingroup data tables is only used to implement
tegra_pinctrl_disable(). The only reason this function is called is when
dynamically switching between pinmux states, i.e. when disabling the old
state before programming the new state. It's simpler to have the new
target state define the expected value of each pin (and all current DTs
do that). This also gives more flexibility, since it allows individual
boards explicit control over the "inactive" mux function for each pin,
rather than requiring it to be an SoC-specific value. Assuming this, we
can get rid of the fsafe value from the driver completely, thus saving
some more space in the driver tables.
While re-writing the content of tegra124_pingroups[], fix the indentation
to use a TAB instead of spaces.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephen Warren [Tue, 15 Apr 2014 17:00:50 +0000 (11:00 -0600)]
pinctrl: tegra: remove redundant data table fields
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel
options has the relevant HW register fields in the same register as the
mux function selection. Similarly, the drvtype option is always in the
drive register, if it is supported at all. Hence, we don't need to have
struct *_reg fields in the pin group table to define which register and
bank to use for those options. Delete this to save space in the driver's
data tables.
However, many of those options are not supported on all SoCs, or not
supported on some pingroups. We need a way to detect when they are
supported. Previously, this was indicated by setting the struct *_reg
field to -1. With the struct *_reg fields removed, we use the struct
*_bit fields for this purpose instead. The struct *_bit fields need to
be expanded from 5 to 6 bits in order to store a value outside the valid
HW bit range of 0..31.
Even without removing the struct *_reg fields, we still need to add code
to validate the struct *_bit fields, since some struct *_bit fields were
already being set to -1, without an option-specific struct *_reg field to
"guard" them. In other words, before this change, the pinmux driver might
allow some unsupported options to be written to HW.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Wolfram Sang [Tue, 25 Mar 2014 18:56:26 +0000 (19:56 +0100)]
pinctrl: pfc: r8a7790: add mux data for IIC(B) cores
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Wolfram Sang [Tue, 25 Mar 2014 18:56:25 +0000 (19:56 +0100)]
pinctrl: pfc: r8a7790: add i2c0 muxing
Add the muxing for the last missing i2c rcar core. Fix the sorting for
SH_PFC_PIN_NAMED while we are here.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fabio Estevam [Sun, 13 Apr 2014 15:09:05 +0000 (12:09 -0300)]
pinctrl: pinctrl-imx: Print the mux_mode field in hex format
With debug enabled we get better readability dumps of the mux_mode register if
we use hexadecimal format instead:
imx6sl-pinctrl
20e0000.iomuxc: MX6SL_PAD_FEC_REF_CLK: 0x10 0x0001b0a8
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kuninori Morimoto [Mon, 14 Apr 2014 00:24:04 +0000 (17:24 -0700)]
sh-pfc: r8a7791: Add Audio pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kuninori Morimoto [Mon, 14 Apr 2014 00:23:35 +0000 (17:23 -0700)]
sh-pfc: r8a7791: Add SSI pin support
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Ténart [Wed, 16 Apr 2014 12:57:48 +0000 (14:57 +0200)]
pinctrl: sunxi: fix typo in module author address
According to the MODULE_AUTHOR() comments, the author name should be
"Name <email>" or just "Name". Add the missing '>'.
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Antoine Ténart [Thu, 10 Apr 2014 13:07:50 +0000 (15:07 +0200)]
pinctrl: allows not to define the get_group_pins operation
When using a group only pinctrl driver, which does not have any
information on the pins it is useless to define a get_group_pins
always returning an empty list of pins.
When not using get_group_pin[1], a driver must implement it so
pins = NULL and num_pins = 0. This patch makes it the default
behaviour if not defined in the pinctrl driver when used in
pinmux enable and disable funtions and in pinctrl_groups_show.
It also adds a check in pinctrl_get_group_pins and return -EINVAL if
not defined. This function is called in the gpiolib when adding when
pingroup range. It cannot be used if no group is defined, so this seams
reasonable.
[1] get_group_pin(struct pinctrl_dev *pctldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins);
Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:46 +0000 (15:52 +0200)]
ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
The A31 SoC has PL and PM banks and thus increase the default ARCH_NR_GPIO.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:45 +0000 (15:52 +0200)]
pinctrl: sunxi: add reset control support
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted.
Try to retrieve a reset control and deassert if one was found.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:44 +0000 (15:52 +0200)]
pinctrl: sunxi: define A31 R_PIO pin functions
The A31 SoC provides both PL and PM pio bank through the R_PIO block.
These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:43 +0000 (15:52 +0200)]
pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.
First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:42 +0000 (15:52 +0200)]
pinctrl: sunxi: add PL and PM pin definitions
Define PL and PM pin macros.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:41 +0000 (15:52 +0200)]
pinctrl: sunxi: disable clk when failing to probe pin controller
Disable the clk when failing to probe the pin controller device.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Boris BREZILLON [Thu, 10 Apr 2014 13:52:40 +0000 (15:52 +0200)]
pinctrl: sunxi: check clk_prepare_enable return value
Check the clk_prepare_enable return value to avoid false positive probe.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime COQUELIN [Tue, 8 Apr 2014 15:21:49 +0000 (17:21 +0200)]
pinctrl: st: Use ARRAY_SIZE for STiH415 data
This patch completes the one that used ARRAY_SIZE for STiH407 and STiH416
for setting ninput_delays and noutput_delays fields.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Maxime COQUELIN [Tue, 8 Apr 2014 15:21:48 +0000 (17:21 +0200)]
pinctrl: st: Use const qualifier when required
This patch adds const qualifier where applicable.
Reported-by: Joe Perches <joe@perches.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Axel Lin [Thu, 3 Apr 2014 13:47:53 +0000 (21:47 +0800)]
pinctrl: lantiq: Fix header file include guard
Define __PINCTRL_LANTIQ_H to prevent multiple inclusion.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Axel Lin [Thu, 3 Apr 2014 13:44:47 +0000 (21:44 +0800)]
pinctrl: adi2: Statize adi_gpio_irq_domain_ops
It's only referenced in this file, make it static.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Laurent Pinchart [Tue, 1 Apr 2014 10:59:09 +0000 (12:59 +0200)]
pinctrl: sh-pfc: r8a7791: Split the DU sync and cde/disp groups
The DU parallel interface ODDF signal is optional, move it out of the
HSYNC/VSYNC group into a group of its down. The CDE and DISP signals are
independent, split them to two different groups.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Uwe Kleine-König [Tue, 1 Apr 2014 20:25:59 +0000 (22:25 +0200)]
pinctrl: msm8x74: make Kconfig dependency more strict
This driver is only useful on MSM8x74, so let the driver depend on
ARCH_QCOM but allow compile coverage testing.
The main benefit is that the driver isn't available to be selected for
machines that don't have the matching hardware.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bjorn Andersson [Mon, 31 Mar 2014 21:49:57 +0000 (14:49 -0700)]
pinctrl: msm: Add definitions for the APQ8064 platform
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm APQ8064 platform.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bjorn Andersson [Mon, 31 Mar 2014 21:49:56 +0000 (14:49 -0700)]
pinctrl: msm: Add documentation for pinctrl-apq8064 binding
DT bindingdocumentation for qcom,apq8064-pinctrl driver.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Bjorn Andersson [Mon, 31 Mar 2014 21:49:55 +0000 (14:49 -0700)]
pinctrl: msm: Make number of functions variable
The various pins may have different number of functions defined, so make this
number definable per pin instead of just increasing it to the largest one for
all of the platforms.
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Tue, 8 Apr 2014 12:45:47 +0000 (14:45 +0200)]
pinctrl: st: use gpiolib irqchip helpers
This lets the gpiolib core handle the irqchip set-up and
chained IRQ on the primary (behind the mux) IRQ chip in
the st pinctrl driver.
Default irq type is set to level low at irqchip add time.
The v1 was sent by Linus
(https://lkml.org/lkml/2014/4/4/287).
Two changes were necessary to make it to work properly
on STiH416:
1 - dev reference was not passed to the gpio_chip
struct, causing a panic.
2 - gpiochip_irqchip_add passed IRQ_TYPE_NONE as
default type, which caused lot of warnings at
init time. I choose IRQ_TYPE_LEVEL_LOW as default.
Cc: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime COQUELIN <maxime.coquelin@st.com>
Linus Walleij [Fri, 4 Apr 2014 14:02:21 +0000 (16:02 +0200)]
pinctrl: st: switch IRQ locking to resource callbacks
In the mass-conversion to the new irqchip callbacks, this
in-transit IRQ support was missed. Fix it.
Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Cc: Maxime COQUELIN <maxime.coquelin@st.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Torvalds [Sun, 20 Apr 2014 18:08:50 +0000 (11:08 -0700)]
Linux 3.15-rc2
Linus Torvalds [Sun, 20 Apr 2014 17:35:31 +0000 (10:35 -0700)]
Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine fixes from Vinod Koul:
"Back from long weekend here in India and now the time to send fixes
for slave dmaengine.
- Dan's fix of sirf xlate code
- Jean's fix for timberland
- edma fixes by Sekhar for SG handling and Yuan for changing init
call"
* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
dma: fix eDMA driver as a subsys_initcall
dmaengine: sirf: off by one in of_dma_sirfsoc_xlate()
platform: Fix timberdale dependencies
dma: edma: fix incorrect SG list handling
Linus Torvalds [Sun, 20 Apr 2014 17:33:49 +0000 (10:33 -0700)]
Merge tag 'iommu-fixes-v3.15-rc1' of git://git./linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"Fixes for regressions:
- fix wrong IOMMU enumeration causing some SCSI device drivers
initialization failures
- ARM-SMMU fixes for a panic condition and a wrong return value"
* tag 'iommu-fixes-v3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/arm-smmu: fix panic in arm_smmu_alloc_init_pte
iommu/arm-smmu: Return 0 on unmap failure
iommu/vt-d: fix bug in matching PCI devices with DRHD/RMRR descriptors
iommu/vt-d: Fix get_domain_for_dev() handling of upstream PCIe bridges
iommu/vt-d: fix memory leakage caused by commit
ea8ea46
Linus Torvalds [Sun, 20 Apr 2014 17:32:33 +0000 (10:32 -0700)]
Merge branch 'perf-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull perf tooling fixes from Ingo Molnar:
"Three small tooling fixes"
* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf tools: Improve error reporting
perf tools: Adjust symbols in VDSO
perf kvm: Fix 'Min time' counting in report command
Ingo Molnar [Sun, 20 Apr 2014 07:53:55 +0000 (09:53 +0200)]
Merge tag 'perf-urgent-for-mingo' of git://git./linux/kernel/git/jolsa/perf into perf/urgent
Pull perf/urgent fixes from Jiri Olsa:
User visible changes:
* Adjust symbols in VDSO to properly resolve its function names (Vladimir Nikulichev)
* Improve error reporting for record session failure (Adrien BAK)
* Fix 'Min time' counting in report command (Alexander Yarygin)
Signed-off-by: Jiri Olsa <jolsa@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Adrien BAK [Fri, 18 Apr 2014 02:00:43 +0000 (11:00 +0900)]
perf tools: Improve error reporting
In the current version, when using perf record, if something goes
wrong in tools/perf/builtin-record.c:375
session = perf_session__new(file, false, NULL);
The error message:
"Not enough memory for reading per file header"
is issued. This error message seems to be outdated and is not very
helpful. This patch proposes to replace this error message by
"Perf session creation failed"
I believe this issue has been brought to lkml:
https://lkml.org/lkml/2014/2/24/458
although this patch only tackles a (small) part of the issue.
Additionnaly, this patch improves error reporting in
tools/perf/util/data.c open_file_write.
Currently, if the call to open fails, the user is unaware of it.
This patch logs the error, before returning the error code to
the caller.
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Adrien BAK <adrien.bak@metascale.org>
Link: http://lkml.kernel.org/r/1397786443.3093.4.camel@beast
[ Reorganize the changelog into paragraphs ]
[ Added empty line after fd declaration in open_file_write ]
Signed-off-by: Jiri Olsa <jolsa@redhat.com>
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