Michael Turquette [Wed, 2 Mar 2016 00:23:40 +0000 (16:23 -0800)]
Merge branch 'clk-ti' into clk-next
Conflicts:
drivers/clk/Kconfig
Stephen Boyd [Tue, 1 Mar 2016 18:51:42 +0000 (10:51 -0800)]
clk: ti: Fix some errors found by static checkers
drivers/clk/ti/clk-814x.c:34:12: warning: symbol 'dm814x_adpll_early_init' was not declared. Should it be static?
drivers/clk/ti/clk-814x.c:58:12: warning: symbol 'dm814x_adpll_enable_init_clocks' was not declared. Should it be static?
drivers/clk/ti/adpll.c:465 ti_adpll_recalc_rate() warn: should '__readw(d->regs + 20) << 18' be a 64 bit type?
drivers/clk/ti/adpll.c:945 ti_adpll_probe() error: we previously assumed 'd->clocks' could be null (see line 921)
The last one looks like a real bug because we don't return an
error on allocation failure.
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tony Lindgren [Fri, 26 Feb 2016 17:45:03 +0000 (09:45 -0800)]
clk: ti: Allow COMPILE_TEST to build selected drivers
The arch independent drivers can be build testeed with
COMPILE_TEST. Let's allow that for drivers/clk/ti.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Tony Lindgren [Fri, 26 Feb 2016 17:35:05 +0000 (09:35 -0800)]
clk: ti: Add support for dm814x ADPLL
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.
Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.
Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Archit Taneja [Sun, 28 Feb 2016 10:07:17 +0000 (15:37 +0530)]
clk: qcom: Fix pre-divider usage for pixel RCG
The clk_rcg_pixel_set_rate clk_op sets up the pre-divider by reading
its current value from the NS register.
Using the pre-divider wasn't really intended when creating these ops.
The pixel RCG was only intended to achieve fractional multiplication
provided in the pixel_table array. Leaving the pre-divider to the
existing register value results in a wrong pixel clock when the
bootloader sets up the display. This was left unidentified because
the IFC6410 Plus board on which this was verified didn't have a
bootloader that configured the display.
Don't set the RCG pre-divider in freq_tbl to the existing NS register
value. Force it to 1 and only use the M/N counter to achieve the desired
fractional multiplication.
Cc: Vinay Simha <vinaysimha@inforcecomputing.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 20:36:15 +0000 (12:36 -0800)]
clk: h8300: Properly cast to __iomem pointer
Sparse complains here because we dropped the __iomem annotation
when casting the aligned address. Add __iomem back so that sparse
stops complaining.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 19:14:25 +0000 (11:14 -0800)]
simplefb: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: <linux-fbdev@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 19:12:47 +0000 (11:12 -0800)]
usb: dwc3: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Acked-by: Felipe Balbi <balbi@kernel.org>
Cc: <linux-usb@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:49:23 +0000 (17:49 -0800)]
clk: ti: Update for of_clk_get_parent_count() returning unsigned int
Change the types here to unsigned int instead of int and update
the checks for == 0 instead < 1 to be more explicit about what's
going on now that of_clk_get_parent_count() has changed return
types.
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:44:27 +0000 (17:44 -0800)]
clk: sunxi: Use proper type for of_clk_get_parent_count() return value
The return type of of_clk_get_parent_count() is an unsigned int
now, so let's update the code here to be more explicit about the
range of values we can test for.
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:43:30 +0000 (17:43 -0800)]
clk: st: Remove impossible check for of_clk_get_parent_count() < 0
The checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the types.
Cc: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:36:51 +0000 (17:36 -0800)]
clk: h8300: Remove impossible check for of_clk_get_parent_count()
The checks for < 1 can be simplified now that
of_clk_get_parent_count() returns an unsigned int. Update the
code to reflect the int to unsigned int change.
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: <uclinux-h8-devel@lists.sourceforge.jp>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:31:52 +0000 (17:31 -0800)]
clk: gpio: Remove impossible check for of_clk_get_parent_count() < 0
The check for < 0 is impossible now that
of_clk_get_parent_count() returns an unsigned int. Simplify the
code and update the type here.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Sat, 20 Feb 2016 01:29:17 +0000 (17:29 -0800)]
clk: at91: Remove impossible checks for of_clk_get_parent_count()
These checks for < 0 are impossible now that
of_clk_get_parent_count() returns an unsigned int. Change the
checks for == 0 and update the type.
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Fri, 19 Feb 2016 23:52:32 +0000 (15:52 -0800)]
clk: Make of_clk_get_parent_count() return unsigned ints
Russell King recently pointed out a bug in the clk-gpio code
where it fails to register the clk if of_clk_get_parent_count()
returns an error because the "clocks" property isn't present in
the DT node. If we're trying to count parents from DT we'd like
to know the count, not if there is a "clocks" property or not.
Furthermore, some drivers are assigning the return value to their
clk_init_data::num_parents member which is unsigned, leading to
potentially large numbers of parents when the property isn't
present.
Let's change the API to return an unsigned int instead of an int.
All the callers just want to know the count anyway, and this
avoids the bug that was in the clk-gpio driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Geert Uytterhoeven [Fri, 26 Feb 2016 15:54:31 +0000 (16:54 +0100)]
clk: Ignore disabled DT clock providers
of_clk_init() uses for_each_matching_node_and_match() to find clock
providers, which returns all matching device nodes, whether they are
enabled or not. Hence clock providers that are disabled explicitly in DT
using e.g.
"status = "disabled";
are still activated.
Add a check to ignore device nodes that are not enabled, like
of_irq_init() does.
Reported-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Shawn Lin [Fri, 26 Feb 2016 01:25:52 +0000 (09:25 +0800)]
clk: skip unnecessary set_phase if nothing to do
Let's compare the degrees from clk_set_rate with
clk->core->phase. If the requested degrees is already
there, skip the following steps.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
[sboyd@codeaurora.org: s/drgrees/degrees/ in commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Martin Sperl [Tue, 22 Dec 2015 20:13:08 +0000 (20:13 +0000)]
clk: bcm2835: added missing clock register definitions
Added missing CTRL and DIV clock register definitions for:
PCM, SLIM, TCNT, TEC, TD0, TD1
Register information taken from:
https://rawgit.com/msperl/rpi-registers/master/rpi-registers.html#CM
which extracted the information from the header files shared by
Broadcom/rpi foundation in this file:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Simon Horman [Tue, 23 Feb 2016 00:57:31 +0000 (09:57 +0900)]
clk: shmobile: Remove ARCH_SHMOBILE_MULTI
As of
9b5ba0df4ea4 ("ARM: shmobile: Introduce ARCH_RENESAS") all platforms
that use Renesas clock drivers now select ARCH_RENESAS. As it is present in
drivers/clk/Makefile ARCH_SHMOBILE_MULTI may now be removed.
This is part of an ongoing process to migrate from ARCH_SHMOBILE to
ARCH_RENESAS the motivation for which being that RENESAS seems to be a more
appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Thu, 25 Feb 2016 23:18:12 +0000 (15:18 -0800)]
Merge tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung into clk-next
Pull Samsung clk driver changes from Sylwester Nawrocki:
Mostly correction of errors in the exynos5433 SoC
clocks definition, dropping read-only registers
from the suspend/resume register save/restore list
and exposition of two clocks required for the
exynos5433 HDMI subsystem operation.
* tag 'clk-samsung-4.6' of git://linuxtv.org/snawrocki/samsung:
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
clk/samsung: exynos5433: add pclk_decon clock
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
Kevin Smith [Thu, 11 Feb 2016 16:54:00 +0000 (16:54 +0000)]
clk: mvebu: Move corediv config to mvebu config
The core clock does not depend on corediv, so enabling corediv
based on the clock is not really correct. Move the corediv
config option from the clock driver Kconfig to the mvebu Kconfig
so that it can be enabled by the MACH option instead.
This also enables corediv on Armada 375 and 38X, which was
previously missing.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Kevin Smith [Thu, 11 Feb 2016 16:53:52 +0000 (16:53 +0000)]
clk: mvebu: Remove corediv clock from Armada XP
There is no corediv clock on Armada XP, so this is unnecessary.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Linus Walleij [Wed, 24 Feb 2016 08:39:11 +0000 (09:39 +0100)]
clk: versatile: sp810: support reentrance
Despite care take to allocate clocks state containers the
SP810 driver actually just supports creating one instance:
all clocks registered for every instance will end up with the
exact same name and __clk_init() will fail.
Rename the timclken<0> .. timclken<n> to sp810_<instance>_<n>
so every clock on every instance gets a unique name.
This is necessary for the RealView PBA8 which has two SP810
blocks: the second block will not register its clocks unless
every clock on every instance is unique and results in boot
logs like this:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at ../drivers/clk/versatile/clk-sp810.c:137
clk_sp810_of_setup+0x110/0x154()
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted
4.5.0-rc2-00030-g352718fc39f6-dirty #225
Hardware name: ARM RealView Machine (Device Tree Support)
[<
c00167f8>] (unwind_backtrace) from [<
c0013204>]
(show_stack+0x10/0x14)
[<
c0013204>] (show_stack) from [<
c01a049c>]
(dump_stack+0x84/0x9c)
[<
c01a049c>] (dump_stack) from [<
c0024990>]
(warn_slowpath_common+0x74/0xb0)
[<
c0024990>] (warn_slowpath_common) from [<
c0024a68>]
(warn_slowpath_null+0x1c/0x24)
[<
c0024a68>] (warn_slowpath_null) from [<
c051eb44>]
(clk_sp810_of_setup+0x110/0x154)
[<
c051eb44>] (clk_sp810_of_setup) from [<
c051e3a4>]
(of_clk_init+0x12c/0x1c8)
[<
c051e3a4>] (of_clk_init) from [<
c0504714>]
(time_init+0x20/0x2c)
[<
c0504714>] (time_init) from [<
c0501b18>]
(start_kernel+0x244/0x3c4)
[<
c0501b18>] (start_kernel) from [<
7000807c>] (0x7000807c)
---[ end trace
cb88537fdc8fa200 ]---
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Fixes: 6e973d2c4385 "clk: vexpress: Add separate SP810 driver"
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 27 Jan 2016 22:17:00 +0000 (14:17 -0800)]
clk: Get rid of HAVE_MACH_CLKDEV
This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Joshua Henderson <joshua.henderson@microchip.com>
Stephen Boyd [Thu, 25 Feb 2016 22:32:27 +0000 (14:32 -0800)]
Merge branch 'clk-ipq4019' into clk-next
* clk-ipq4019:
clk: qcom: Add IPQ4019 Global Clock Controller support
Varadarajan Narayanan [Thu, 19 Nov 2015 23:19:29 +0000 (17:19 -0600)]
clk: qcom: Add IPQ4019 Global Clock Controller support
This patch adds support for the global clock controller found on
the IPQ4019 based devices. This includes UART, I2C, SPI etc.
Signed-off-by: Pradeep Banavathi <pradeepb@codeaurora.org>
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
[sboyd@codeaurora.org: Drop 0x16024 enable_reg in crypto_ahb]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Thu, 25 Feb 2016 20:18:25 +0000 (12:18 -0800)]
clk: shmobile: Free 'clock' on error path
We forgot to free this clock when we return early in this code.
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Jonghwa Lee [Wed, 6 May 2015 12:24:20 +0000 (21:24 +0900)]
clk: samsung: exynos5433: Fix wrong registers of PCLK_GSCL_SMMU clocks
This fixes register assignment in the CLK_PCLK_SMMU_GSCL{1,2}
clocks definition.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Fri, 6 Nov 2015 11:55:30 +0000 (12:55 +0100)]
clk: samsung: exynos5433: Fix mout_aclk_cam1*_user clocks definition
Control bits for the ACLK_CAM1_552_USER and ACLK_CAM1_400_USER
mux clocks are in MUX_SEL_CAM10, not MUX_SEL_CAM01 register.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Tue, 26 May 2015 10:55:50 +0000 (12:55 +0200)]
clk: samsung: exynos5433: Drop RO registers from the save/restore lists
Restoring read-only registers is of not much effect, drop them
from the respective lists.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Marek Szyprowski [Tue, 21 Jul 2015 12:37:57 +0000 (14:37 +0200)]
clk: samsung: exynos5433: Fix definitions of SCLK ISP SENSOR0 clocks
This fixes bit field offsets in the CMU_TOP CLK_DIV_SCLK_ISP_SENSOR_{A,B}
clock definitions.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sylwester Nawrocki [Wed, 27 May 2015 13:04:43 +0000 (15:04 +0200)]
clk: samsung: exynos5433: Fix definitions of MUX_SEL_CAM04 clocks
This corrects assignment of bit offsets of the MUX_SEL_CAM04 register
to the respective mux clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Sudip Mukherjee [Tue, 23 Feb 2016 09:30:03 +0000 (15:00 +0530)]
clk: shmobile: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper devm_add_action_or_reset() and return directly
as we know that the cleanup has been done by this helper.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sylwester Nawrocki [Wed, 18 Feb 2015 16:31:35 +0000 (17:31 +0100)]
clk: samsung: exynos5433: Fix typos in *_ISP_MPWM clock names
This fixes "MPWM" -> "WPWM" typo in 3 *ISP_MWPM clock definitions.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Stephen Boyd [Mon, 22 Feb 2016 23:43:41 +0000 (15:43 -0800)]
clk: Update some outdated comments
__clk_init() was renamed to __clk_core_init() but these comments
weren't updated.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 23:01:39 +0000 (15:01 -0800)]
Revert "clk: avoid circular clock topology"
This reverts commit
858d5881564026cbc4e6f5e25ae878a27df5d4c9.
Joachim reports that this commit breaks lpc18xx boot. This is
because the hardware has circular clk topology where PLLs can
feed into dividers and the same dividers can feed into the PLLs.
The hardware is designed this way so that you can choose to put
the divider before the PLL or after the PLL depending on what you
configure to be the parent of the divider and what you configure
to be the parent of the PLL.
So let's drop this patch for now because we have hardware that
actually has loops. A future patch could check for circular
parents when we change parents and fail the switch, but that's
probably best left to some debugging Kconfig option so that we
don't suffer the sanity checking cost all the time.
Reported-by: Joachim Eastwood <manabian@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Dinh Nguyen [Mon, 22 Feb 2016 21:52:46 +0000 (15:52 -0600)]
clk: socfpga: allow for multiple parents on Arria10 periph clocks
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can
have multiple parents. Fix up the __socfpga_periph_init() to call
of_clk_parent_fill() that will return the appropriate number of parents.
Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper
function.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Sat, 20 Feb 2016 11:24:26 +0000 (13:24 +0200)]
clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs
Convert DPLL support code to use clk_hw pointers for reference and bypass
clocks. This allows us to use clk_hw_* APIs for accessing any required
parameters for these clocks, avoiding some locking problems at least with
DPLL enable code; this used clk_get_rate which uses mutex but isn't
good under clk_enable / clk_disable.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 22 Feb 2016 22:16:24 +0000 (14:16 -0800)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
Srinivas Kandagatla [Mon, 22 Feb 2016 11:43:39 +0000 (11:43 +0000)]
clk: qcom: msm8960: fix ce3_core clk enable register
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tero Kristo [Sat, 20 Feb 2016 11:12:57 +0000 (13:12 +0200)]
clk: ti: omap3+: dpll: use non-locking version of clk_get_rate
As the code in this file is being executed within irq context in some
cases, we must avoid the clk_get_rate which uses mutex internally.
Switch the code to use clk_hw_get_rate instead which is non-locking.
This fixes an issue where PM runtime will hang the system if enabled
with a serial console before a suspend-resume cycle.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Michael Turquette [Mon, 22 Feb 2016 18:24:40 +0000 (10:24 -0800)]
Merge branch 'clk-samsung' into clk-next
Krzysztof Kozlowski [Tue, 16 Feb 2016 06:20:31 +0000 (15:20 +0900)]
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS
so it is built also on ARMv7. This does not bring any kind of benefit.
There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like
multi_v7 for ARMv7).
Instead build clock drivers only for respective SoC's architecture.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Fri, 19 Feb 2016 17:46:31 +0000 (09:46 -0800)]
Merge branch 'clk-shmobile-for-v4.6' of git://git./linux/kernel/git/geert/renesas-drivers into clk-next
Stephen Boyd [Fri, 19 Feb 2016 03:17:29 +0000 (19:17 -0800)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: gpio: Really allow an optional clock= DT property
Revert "clk: qcom: Specify LE device endianness"
Stephen Boyd [Fri, 19 Feb 2016 03:07:44 +0000 (19:07 -0800)]
clk: gpio: Really allow an optional clock= DT property
We mis-merged the original patch from Russell here and so the
patch went almost all the way, except that we still failed to
probe when there wasn't a clocks property in the DT node. Allow
that case by making a negative value from
of_clk_get_parent_count() into "no parents", like the original
patch did.
Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property")
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Magnus Damm [Thu, 18 Feb 2016 07:14:03 +0000 (16:14 +0900)]
clk: shmobile: r8a7795: Add INTC-EX clock
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver.
According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Andrew F. Davis [Fri, 12 Feb 2016 18:50:16 +0000 (12:50 -0600)]
clk: Make of_clk_get_from_provider() available to modules
Export symbol of_clk_get_from_provider so it can be used in
loadable kernel modules
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Krzysztof Kozlowski [Tue, 16 Feb 2016 06:20:30 +0000 (15:20 +0900)]
clk: samsung: Enable COMPILE_TEST for Samsung clocks
Enable the COMPILE_TEST to get build coverage of some of Samsung clock
controller drivers. Still some of them will be built only if
appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX).
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Tue, 16 Feb 2016 20:31:51 +0000 (12:31 -0800)]
Merge branch 'clk-bcm2835' into clk-next
Eric Anholt [Tue, 16 Feb 2016 03:03:58 +0000 (19:03 -0800)]
clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()
We were rolling this ourselves, but clk-divider can do it now.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Eric Anholt [Tue, 16 Feb 2016 03:03:57 +0000 (19:03 -0800)]
clk: bcm2835: Fix setting of PLL divider clock rates
Our dividers weren't being set successfully because CM_PASSWORD wasn't
included in the register write. It looks easier to just compute the
divider to write ourselves than to update clk-divider for the ability
to OR in some arbitrary bits on write.
Fixes about half of the video modes on my HDMI monitor (everything
except 720x400).
Cc: stable@vger.kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Geert Uytterhoeven [Tue, 20 Oct 2015 08:21:49 +0000 (10:21 +0200)]
clk: shmobile: cpg-mssr: Update serial port clock in example
Cfr. commit
a9ec81f4ed5c05db ("serial: sh-sci: Drop the interface
clock").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Michael Turquette [Mon, 15 Feb 2016 19:59:45 +0000 (11:59 -0800)]
Merge tag 'v4.6-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-next
Introduction of a factor type and a variant containing a gate
to be able to also declare factor clocks in their correct
place in the clock tree instead of having to register factor
clocks in the init callback separately. And as always some more
clock-ids and non-regression fixes for mistakes introduced in
past kernel releases.
Stephen Boyd [Fri, 12 Feb 2016 17:21:13 +0000 (09:21 -0800)]
Revert "clk: qcom: Specify LE device endianness"
This reverts commit
329cabcecf94d8d7821e729dda284ba9dec44c87.
The commit that caused us to specify LE device endianness here,
29bb45f25ff3 (regmap-mmio: Use native endianness for read/write,
2015-10-29), has been reverted in mainline so now when we specify
LE it actively breaks big endian kernels because the byte
swapping in regmap-mmio is incorrect. Let's revert this change
because it will 1) fix the big endian kernels and 2) be redundant
to specify LE because that will become the default soon.
Cc: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:16 +0000 (21:42 +0530)]
clk: qcom: mmcc8974: Use gdscs .parent and remove genpd calls
With gdsc driver capable of handling hierarchical power domains,
specify oxili_gdsc as parent of oxilicx_gdsc.
Remove all direct calls to genpd from the mmcc clock driver. The
adding and removing of subdomains is now handled from within
the gdsc driver.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:15 +0000 (21:42 +0530)]
clk: qcom: gdsc: Add mmcc gdscs for msm8996 family
Add all gdsc data which are part of mmcc on msm8996 family
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:14 +0000 (21:42 +0530)]
clk: qcom: gdsc: Add GDSCs in msm8996 GCC
Add all data for the GDSCs which are part of msm8996 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:13 +0000 (21:42 +0530)]
clk: qcom: gdsc: Add support for votable gdscs
Some gdscs might be controlled via voting registers and might not
really disable when the kernel intends to disable them (due to other
votes keeping them enabled)
Mark these gdscs with a flag for we do not check/wait on a disable
status for these gdscs within the kernel disable callback.
Also at boot, if these GDSCs are found to be ON, we make sure we
vote for them before we inform the genpd framework about their
status. If genpd gets no users, it then disables (removes the vote)
them as part of genpd_poweroff_unused()
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:12 +0000 (21:42 +0530)]
clk: qcom: gdsc: Add support for gdscs with gds hw controller
Some gdsc power domains can have a gds_hw_controller block inside
to help ensure all slave devices within the power domain are idle
before the gdsc is actually switched off.
This is mainly useful in power domains which host a MMU, in which
case its necessary to make sure there are no outstanding MMU operations
or pending bus transactions before the power domain is turned off.
In gdscs with gds_hw_controller block, its necessary to check the
gds_hw_ctrl status bits instead of the ones in gdscr, to determine
the state of the powerdomain.
While at it, also move away from using jiffies and use ktime APIs
instead for busy looping on status bits.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Rajendra Nayak [Tue, 1 Dec 2015 16:12:11 +0000 (21:42 +0530)]
clk: qcom: gdsc: Add support for hierarchical power domains
Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs
specify the parents (if any) and the driver add genpd subdomains for them.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sylvain Lemieux [Wed, 10 Feb 2016 18:52:32 +0000 (13:52 -0500)]
clk: lpc32xx: add HCLK PLL output configuration
This patch add the support to setup the HCLK PLL output
using the "assigned-clock-rates" parameter in the device tree.
If the option is not use, the clock setup by the kickstart
and/or bootloader remain unchanged.
The previous kernel version did not change the clock frequency
output setup by the kickstart and/or bootloader;
this version always setup the clock frequency output to 208MHz.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 10 Feb 2016 20:44:33 +0000 (12:44 -0800)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: versatile: mask VCO bits before writing
Linus Walleij [Wed, 3 Feb 2016 13:47:08 +0000 (14:47 +0100)]
clk: versatile: mask VCO bits before writing
The Versatile syscon ICST driver OR:s the bits into place but
forgets to mask the previous value, making the code only work
if the register is zero or giving haphazard results. Mask the
19 bits used by the Versatile syscon interface register.
Regression caused and now fixed by yours truly.
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sylvain Lemieux [Tue, 9 Feb 2016 18:29:10 +0000 (13:29 -0500)]
clk: lpc32xx: do not register clock "0"
The following errors are display in the console during the power-on:
[ 0.000000] lpc32xx_usb_clk_init: failed to register (null) clock: -12
[ 0.000000] lpc32xx_clk_init: failed to register (null) clock: -12
There is no need to register clock "0"; the first clock used is 1;
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: s/prepare/register/]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Tue, 9 Feb 2016 11:19:14 +0000 (20:19 +0900)]
clk: fix __clk_init_parent() for single parent clocks
Before commit
b3d192d5121f ("clk: simplify __clk_init_parent()"),
__clk_init_parent() called .get_parent() only for multi-parent
clocks. That commit changed the behavior to call .get_parent()
if available even for single-parent clocks and root clocks.
It turned out a problem because there are some single-parent clocks
that implement .get_parent() callback and return non-zero index.
The SOCFPGA clock is the case; the commit broke the SOCFPGA boards.
To keep the original behavior, invoke .get_parent() only when
num_parents is greater than 1.
Fixes: b3d192d5121f ("clk: simplify __clk_init_parent()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sudip Mukherjee [Wed, 23 Dec 2015 12:27:20 +0000 (17:57 +0530)]
clk: qcom: common: check for failure
We were not checking the return from devm_add_action() which can fail.
Start using the helper and devm_add_action_or_reset() and return
directly as we know that the cleanup has been done by this helper.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sudip Mukherjee [Wed, 23 Dec 2015 12:27:19 +0000 (17:57 +0530)]
devm: add helper devm_add_action_or_reset()
Add a helper function devm_add_action_or_reset() which will internally
call devm_add_action(). But if devm_add_action() fails then it will
execute the action mentioned and return the error code.
Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Andreas Färber [Sun, 7 Feb 2016 21:13:03 +0000 (22:13 +0100)]
clk: meson: Fix meson_clk_register_clks() signature type mismatch
As preparation for arm64 based mesongxbb, which pulls in this code once
enabling ARCH_MESON, fix a size_t vs. unsigned int type mismatch.
The loop uses a local unsigned int variable, so adopt that type,
matching the header.
Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Arnd Bergmann [Mon, 8 Feb 2016 14:39:09 +0000 (15:39 +0100)]
clk: socfpga: fix __init annotation
clang found a bug with the __socfpga_pll_init definition:
drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and
global variables
This moves the __init annotation to the right place so the function
actually gets discarded.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Mike Looijmans [Tue, 3 Nov 2015 11:55:54 +0000 (12:55 +0100)]
drivers/clk/Kconfig: Move the TI CDCE chips close together
There are two TI CDCE clock chips in this file. Move them close
together so they're easier to find.
No functional change, just cosmetic.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Alphabetize]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Mike Looijmans [Tue, 3 Nov 2015 11:55:53 +0000 (12:55 +0100)]
drivers/clk/Kconfig: Fix typo "Sypport" instead of "Support"
Simple cosmetic fix.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Mon, 8 Feb 2016 22:01:10 +0000 (14:01 -0800)]
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: tegra: super: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warning for pll_m
clk: tegra: Use definition for pll_u override bit
clk: tegra: Fix warning caused by pll_u failing to lock
clk: tegra: Fix clock sources for Tegra210 EMC
clk: tegra: Add the APB2APE audio clock on Tegra210
clk: tegra: Add missing of_node_put()
clk: tegra: Fix PLLE SS coefficients
clk: tegra: Fix typos around clearing PLLE bits during enable
clk: tegra: Do not disable PLLE when under hardware control
clk: tegra: Fix pllx dyn step calculation
clk: tegra: pll: Fix potential sleeping-while-atomic
clk: tegra: Fix the misnaming of nvenc from msenc
clk: tegra: Fix naming of MISC registers
clk: tegra: Remove improper flags for lock_enable
clk: tegra: Fix divider on VI_I2C
Stephen Boyd [Mon, 8 Feb 2016 21:50:32 +0000 (13:50 -0800)]
Merge tag 'tegra-for-4.5-clk-fixes' of git://git./linux/kernel/git/tegra/linux into clk-fixes
Pull tegra fixes from Thierry Reding:
clk: tegra: Fixes for v4.5-rc3
This set contains a bunch of miscellaneous fixes that have accumulated
over the past couple of weeks, primarily for the Tegra210 support added
in v4.5-rc1.
* tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: super: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warnings for functions not declared as static
clk: tegra: Fix sparse warning for pll_m
clk: tegra: Use definition for pll_u override bit
clk: tegra: Fix warning caused by pll_u failing to lock
clk: tegra: Fix clock sources for Tegra210 EMC
clk: tegra: Add the APB2APE audio clock on Tegra210
clk: tegra: Add missing of_node_put()
clk: tegra: Fix PLLE SS coefficients
clk: tegra: Fix typos around clearing PLLE bits during enable
clk: tegra: Do not disable PLLE when under hardware control
clk: tegra: Fix pllx dyn step calculation
clk: tegra: pll: Fix potential sleeping-while-atomic
clk: tegra: Fix the misnaming of nvenc from msenc
clk: tegra: Fix naming of MISC registers
clk: tegra: Remove improper flags for lock_enable
clk: tegra: Fix divider on VI_I2C
Yoshihiro Shimoda [Mon, 1 Feb 2016 11:29:05 +0000 (20:29 +0900)]
clk: shmobile: r8a7795: Add USB-DMAC clocks
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Dirk Behme [Sat, 30 Jan 2016 06:33:59 +0000 (07:33 +0100)]
clk: shmobile: r8a7795: Add SD divider support
This patch adds SD[0..3] clock divider support for R-Car Gen3 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Stephen Boyd [Sun, 7 Feb 2016 07:34:55 +0000 (23:34 -0800)]
clk: provider: Remove of_gpio_{gate,mux}_clk_setup() prototypes
These functions either never existed or were only used in
OF_CLK_DECLARE() macros. Remove the dead prototypes.
Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 3 Feb 2016 01:24:56 +0000 (17:24 -0800)]
clk: Deprecate CLK_IS_ROOT
We don't use CLK_IS_ROOT but in a few places in the common clk
framework core. Let's replace those checks with a check for the
number of parents a clk has instead of the flag, freeing up one
flag for something else. We don't remove the flag yet so that
things keep building, but we'll remove it once all drivers have
removed their flag usage.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Stephen Boyd [Wed, 3 Feb 2016 01:09:26 +0000 (17:09 -0800)]
clk: gpio: Make into a platform driver
clk_get() for DT based clks already returns EPROBE_DEFER when the
OF clk provider is not present. So having all this code in the
clk provider to return EPROBE_DEFER when the gpio isn't ready yet
can be replaced with a platform driver that doesn't add the clk
provider until the gpio can be requested. Get rid of the
OF_CLK_DECLARE and convert this to a platform driver instead.
Tested-by: Jyri Sarha <jsarha@ti.com>
Cc: Sergej Sawazki <ce3a@gmx.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Jon Nettleton <jon@solid-run.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Heiko Stuebner [Sat, 20 Jun 2015 14:06:02 +0000 (16:06 +0200)]
clk: rockchip: convert manually created factor clocks to the new type
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.
This also unifies the artificial separation of the hclk_vcodec etc clocks
again.
We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Sat, 20 Jun 2015 11:08:57 +0000 (13:08 +0200)]
clk: rockchip: add a factor clock type
Add a clock type for fixed factor clocks. This allows us to define fixed
factor clocks where they appear in the clock hierarchy instead of in the
init function.
The additional factor_gate type, finally allows us to model some last
parts of the clock tree correctly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Heiko Stuebner [Wed, 27 Jan 2016 20:38:37 +0000 (21:38 +0100)]
clk: rockchip: fix parent of hclk_vcodec on rk3036
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock
hclk_vcodec_pre in between and not a child of hclk_disp_pre.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Andrzej Hajda [Tue, 20 Oct 2015 09:22:33 +0000 (11:22 +0200)]
clk/samsung: exynos5433: add pclk_decon clock
This undocumented gate clock is used by DECON IP.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Andrzej Hajda [Tue, 20 Oct 2015 09:22:32 +0000 (11:22 +0200)]
clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Shawn Lin [Tue, 2 Feb 2016 03:37:50 +0000 (11:37 +0800)]
clk: rockchip: free memory in error cases when registering clock branches
Add free memeory if rockchip_clk_register_branch fails.
Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Insu Yun [Sat, 30 Jan 2016 15:12:04 +0000 (10:12 -0500)]
clk: unlock for handling unregistered clock
If clock is already unregistered, it returns with holding lock.
It needs to be unlocked.
Signed-off-by: Insu Yun <wuninsu@gmail.com>
[sboyd@codeaurora.org: Use goto instead]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Arnd Bergmann [Mon, 1 Feb 2016 10:19:10 +0000 (11:19 +0100)]
clk: vt8500: don't return possibly uninitialized data
The clk-vt8500.c driver would previously enter an endless loop
when invalid settings got requested, this was now fixed. However,
the driver will now return uninitialized data for a subset of those
cases instead, as the gcc correctly warns:
clk/clk-vt8500.c: In function 'wm8650_find_pll_bits':
clk/clk-vt8500.c:423:12: error: 'best_div2' may be used uninitialized in this function [-Werror=maybe-uninitialized]
*divisor2 = best_div2;
^
clk/clk-vt8500.c:422:12: error: 'best_div1' may be used uninitialized in this function [-Werror=maybe-uninitialized]
*divisor1 = best_div1;
^
clk/clk-vt8500.c:421:14: error: 'best_mul' may be used uninitialized in this function [-Werror=maybe-uninitialized]
*multiplier = best_mul;
This reworks the error handling in the driver so we now return
-EINVAL from clk_round_rate() and clk_set_rate() when we get
impossible inputs.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fixes: 090341b0a95d ("clk: vt8500: fix sign of possible PLL values")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:10 +0000 (19:23 +0900)]
clk: slightly optimize clk_core_set_parent()
If clk_fetch_parent_index() fails, p_rate is unused. Move the
assignment after the error checking.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:09 +0000 (19:23 +0900)]
clk: simplify clk_fetch_parent_index() function
The clk_core_get_parent_by_index can be used as a helper function
to simplify the implementation of clk_fetch_parent_index().
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:08 +0000 (19:23 +0900)]
clk: make sure parent is not NULL in clk_fetch_parent_index()
If parent is given with NULL, clk_fetch_parent_index() could return
a positive index value.
Currently, parent is checked by the callers of this function, but
it would be safer to do it in this function.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:07 +0000 (19:23 +0900)]
clk: walk the orphan clock list more simply
This loop can be much simpler. If a new parent is available for
orphan clocks, __clk_init_parent(orphan) can detect it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:06 +0000 (19:23 +0900)]
clk: avoid circular clock topology
Currently, clk_register() never checks a circular parent looping,
but clock providers could register such an insane clock topology.
For example, "clk_a" could have "clk_b" as a parent, and vice versa.
In this case, clk_core_reparent() creates a circular parent list
and __clk_recalc_accuracies() calls itself recursively forever.
The core infrastructure should be kind enough to bail out, showing
an appropriate error message in such a case. This helps to easily
find a bug in clock providers. (uh, I made such a silly mistake
when I was implementing my clock providers first. I was upset
because the kernel did not respond, without any error message.)
This commit adds a new helper function, __clk_is_ancestor(). It
returns true if the second argument is a possible ancestor of the
first one. If a clock core is a possible ancestor of itself, it
would make a loop when it were registered. That should be detected
as an error.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:04 +0000 (19:23 +0900)]
clk: simplify __clk_init_parent()
The translation from the index into clk_core is done by
clk_core_get_parent_by_index(). The if-block for num_parents == 1
case is duplicating the code in the clk_core_get_parent_by_index().
Drop the "if (num_parents == 1)" from the special case. Instead,
set the index to zero if .get_parent() is missing.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Masahiro Yamada [Mon, 28 Dec 2015 10:23:04 +0000 (19:23 +0900)]
clk: move checking .get_parent to __clk_core_init()
The .get_parent is mandatory for multi-parent clocks. Move the check
to __clk_core_init(), like other callback checkings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
[sboyd@codeaurora.org: Squashed in error path handling, fix typos
in commit message]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Jon Hunter [Fri, 4 Dec 2015 17:04:25 +0000 (17:04 +0000)]
clk: tegra: super: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for structures and functions that
should be declared static:
drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol
'tegra_super_gen_info_gen4' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol
'tegra_super_gen_info_gen5' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol
'tegra_super_clk_init' was not declared. Should it be static?
Fix this by making the above static.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Fri, 4 Dec 2015 17:04:24 +0000 (17:04 +0000)]
clk: tegra: Fix sparse warnings for functions not declared as static
Sparse reports the following warnings for functions in clk-tegra210.c
that should be declared as static:
drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol
'tegra210_pllcx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol
'_pllc_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol
'_pllc2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol
'_pllc3_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol
'_plla1_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol
'tegra210_plla_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol
'tegra210_plld_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol
'tegra210_plld2_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol
'tegra210_plldp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol
'tegra210_pllc4_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol
'tegra210_pllre_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol
'tegra210_pllx_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol
'tegra210_pllmb_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol
'tegra210_pllp_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol
'tegra210_pllu_set_defaults' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol
'tegra210_clk_adjust_vco_min' was not declared. Should it be static?
Fix this by declaring the above as static.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Fri, 4 Dec 2015 17:04:23 +0000 (17:04 +0000)]
clk: tegra: Fix sparse warning for pll_m
Sparse generates the following warning for the pll_m params structure:
drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry
defined twice
drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here
Fix this by correcting the index for the MISC1 register.
Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Mon, 21 Dec 2015 12:56:32 +0000 (12:56 +0000)]
clk: tegra: Use definition for pll_u override bit
The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined
but not used and when the OVERRIDE bit is cleared in tegra210_pll_init()
the code directly uses the bit number. Therefore, use the definition,
PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Mon, 21 Dec 2015 12:56:31 +0000 (12:56 +0000)]
clk: tegra: Fix warning caused by pll_u failing to lock
If the pll_u is not configured by the bootloader, then on kernel boot the
following warning is seen:
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out1
------------[ cut here ]------------
WARNING: at drivers/clk/tegra/clk.c:269
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-
20151214+ #1
Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT)
task:
ffffffc0bc0a0000 ti:
ffffffc0bc0a8000 task.ti:
ffffffc0bc0a8000
PC is at tegra_init_from_table+0x140/0x164
LR is at tegra_init_from_table+0x140/0x164
pc : [<
ffffffc0008fee78>] lr : [<
ffffffc0008fee78>] pstate:
80000045
sp :
ffffffc0bc0abd50
x29:
ffffffc0bc0abd50 x28:
ffffffc00090b8a8
x27:
ffffffc000a06000 x26:
ffffffc0bc019780
x25:
ffffffc00086a708 x24:
ffffffc00086a790
x23:
ffffffc0006d7188 x22:
ffffffc0bc010000
x21:
000000000000016e x20:
ffffffc0bc00d100
x19:
ffffffc000944178 x18:
0000000000000007
x17:
000000000000000e x16:
0000000000000001
x15:
0000000000000007 x14:
000000000000000e
x13:
0000000000000013 x12:
000000000000001a
x11:
000000000000004d x10:
0000000000000750
x9 :
ffffffc0bc0a8000 x8 :
ffffffc0bc0a07b0
x7 :
0000000000000001 x6 :
0000000002d5f0f8
x5 :
0000000000000000 x4 :
0000000000000000
x3 :
0000000000000002 x2 :
ffffffc000996724
x1 :
0000000000000000 x0 :
0000000000000032
---[ end trace
cbd20ae519e92ced ]---
Call trace:
[<
ffffffc0008fee78>] tegra_init_from_table+0x140/0x164
[<
ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28
[<
ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24
[<
ffffffc00008291c>] do_one_initcall+0x90/0x194
[<
ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8
[<
ffffffc000636bb0>] kernel_init+0x10/0xdc
[<
ffffffc000085cd0>] ret_from_fork+0x10/0x40
clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock
tegra_init_from_table: Failed to enable pll_u_out2
------------[ cut here ]------------
pll_u can be either controlled by software or hardware and this is
selected via the OVERRIDE bit in the pll_u base register. In the function
tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects
hardware control of the pll. However, at the same time the pll_u clocks
are populated in the init_table for tegra210 and so software will try to
configure the pll_u if it is not already configured and hence, the above
warning is seen when the pll fails to lock. Remove the pll_u clocks from
the init_table so that software does not try to configure this pll on
boot.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Jon Hunter [Fri, 18 Dec 2015 13:45:28 +0000 (13:45 +0000)]
clk: tegra: Fix clock sources for Tegra210 EMC
The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This page took 0.047951 seconds and 5 git commands to generate.