Stephen Boyd [Wed, 15 Jan 2014 18:47:22 +0000 (10:47 -0800)]
clk: Add set_rate_and_parent() op
Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Stephen Boyd [Wed, 15 Jan 2014 18:47:21 +0000 (10:47 -0800)]
reset: Silence warning in reset-controller.h
If a user of <linux/reset-controller.h> doesn't include
<linux/of.h> before including reset-controller.h they'll get a
warning as follows:
include/linux/reset-controller.h:44:17:
warning: 'struct of_phandle_args' declared inside parameter list
This is because of_phandle_args is not forward declared. Add the
declaration to silence this warning.
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Barry Song [Wed, 15 Jan 2014 06:11:34 +0000 (14:11 +0800)]
clk: sirf: re-arch to make the codes support both prima2 and atlas6
sirfprima2 and sirfatlas6 are two different SoCs in CSR SiRF series. for
prima2 and atlas6, there are many shared clocks but there are still
some different register layout and hardware clocks, then result in
different clock table.
here we re-arch the driver to
1. clk-common.c provides common clocks for prima2 and atlas6,
2. clk-prima2.h describles registers of prima2 and clk-prima2.c provides
prima2 specific clocks and clock table.
3. clk-atlas6.h describles registers of atlas6 and clk-atlas6.c provides
atlas6 specific clocks and clock table.
4. clk.h and clk.c expose external interfaces and provide uniform entry
for both prima2 and atlas6.
so both prima2 and atlas6 will get support by drivers/clk/sirf.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Tue, 14 Jan 2014 20:56:01 +0000 (12:56 -0800)]
clk: composite: pass mux_hw into determine_rate
The composite clock's .determine_rate implementation can call the
underyling .determine_rate callback corresponding to rate_hw or the
underlying .determine_rate callback corresponding to mux_hw. In both
cases we pass in rate_hw, which is wrong. Fixed by passing mux_hw into
the correct callback.
Reported-by: Lemon Dai <dailemon.gl@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Tue, 14 Jan 2014 19:41:26 +0000 (11:41 -0800)]
Merge branch 'clk-next-shmobile' into clk-next
Valentine Barshak [Sat, 28 Dec 2013 12:09:09 +0000 (16:09 +0400)]
clk: shmobile: Fix MSTP clock array initialization
The clks member of the clk_onecell_data structure should
point to a valid clk array (no NULL entries allowed),
and the clk_num should be equal to the number
of elements in the clks array.
The MSTP driver fails to satisfy the above conditions.
The clks array may contain NULL entries if not all
clock-indices are initialized in the device tree.
Thus, if the clock indices are interleaved we end up
with NULL pointers in-between.
The other problem is the driver uses maximum clock index
as the number of clocks, which is incorrect (less than
the actual number of clocks by 1).
Fix the first issue by pre-setting the whole clks array
with ERR_PTR(-ENOENT) pointers instead of zeros; and
use maximum clkidx + 1 as the number of clocks to fix
the other one.
This should make of_clk_src_onecell_get() return the following:
* valid clk pointers for all clocks registered;
* ERR_PTR(-EINVAL) if (idx >= clk_data->clk_num);
* ERR_PTR(-ENOENT) if the clock at the selected index was not
initialized in the device tree (and was not registered).
Changes in V2:
* removed brackets from the one-line for loop
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Valentine Barshak [Sat, 28 Dec 2013 12:09:08 +0000 (16:09 +0400)]
clk: shmobile: Fix MSTP clock index
Use clkidx when registering MSTP clocks instead of loop counter
since the value is then used to access the specific clock index bit
in the mstp register.
The issue was introduced by the following commit:
f94859c215b6d977 "clk: shmobile: Add MSTP clock support"
Changes in V2:
* none
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Thu, 9 Jan 2014 00:38:10 +0000 (16:38 -0800)]
Merge tag 'for_3.14/samsung-clk' of git://git./linux/kernel/git/tfiga/samsung-clk into clk-next-samsung
(A bit late) first round of Samsung clock patches for v3.14.
Tomasz Figa [Thu, 12 Dec 2013 16:07:21 +0000 (17:07 +0100)]
ARM: dts: Add clock provider specific properties to max77686 node
This patch adds a label and #clock-cells property to device node of
max77686 PMIC to allow using it as a clock provider.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:20 +0000 (17:07 +0100)]
clk: max77686: Register OF clock provider
If max77686 chip is instantiated from device tree, it is desirable to
have an OF clock provider to allow device tree based look-up of clocks.
This patch adds OF clock provider registration to the clk-max77686
driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:19 +0000 (17:07 +0100)]
clk: max77686: Refactor driver data handling
As a prerequisite for further patch adding OF clock provider support to
the driver, this patch changes the driver to store an array of struct
clk * as driver data.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:18 +0000 (17:07 +0100)]
clk: max77686: Fix clean-up in error and remove paths
This patch fixes invalid kfree() and adds missing call to clk_unregister()
in error and remove paths in max77686_clk_probe(). While at it, error
handling is also cleaned up.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:17 +0000 (17:07 +0100)]
clk: max77686: Make max77686_clk_register() return struct clk *
As a preparation for further patches, this patch modifies the clock
registration helper function to return a pointer to the newly registered
clock. No functional change is done to the driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:16 +0000 (17:07 +0100)]
clk: max77686: Refactor successful exit of probe function
The function can simply return 0, without jumping to a separate label,
which does exactly the same. This patch does not introduce any
functional change, just a clean-up.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:15 +0000 (17:07 +0100)]
clk: max77686: Provide .recalc_rate() operation
It is usually nice to know frequency of a clock, so this patch adds a
.recalc_rate() callback returning rates of provided clocks.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Thu, 12 Dec 2013 16:07:14 +0000 (17:07 +0100)]
clk: max77686: Correct callback used for checking clock status
Changing status of clock gates in max77686 requires i2c transfers, which
can sleep, so this is done in prepare and unprepare callbacks. Due to
this, checking whether whether the clock is ungated must be done
in is_prepared() callback as well, for consistency.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Tomasz Figa [Sat, 9 Nov 2013 02:17:34 +0000 (03:17 +0100)]
MAINTAINERS: Add entry for Samsung SoC clock drivers
This patch adds an entry for Samsung SoC clock drivers located under
drivers/clk/samsung/ directory, with me taking the maintainer role.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:52 +0000 (14:12 -0700)]
ARM: dts: exynos5420: add input clocks to audss clock controller
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:51 +0000 (14:12 -0700)]
clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:50 +0000 (14:12 -0700)]
ARM: dts: exynos5250: add input clocks to audss clock controller
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS
clock controller.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:49 +0000 (14:12 -0700)]
clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:48 +0000 (14:12 -0700)]
clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Wed, 25 Sep 2013 21:12:47 +0000 (14:12 -0700)]
clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:40 +0000 (15:47 +0100)]
clk: exynos5440: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:38 +0000 (15:47 +0100)]
ARM: exynos5440: create a DT header defining CLK IDs
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Kyungmin Park <kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:37 +0000 (15:47 +0100)]
clk: exynos5420: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:35 +0000 (15:47 +0100)]
ARM: exynos5420: create a DT header defining CLK IDs
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:34 +0000 (15:47 +0100)]
clk: exynos5250: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:32 +0000 (15:47 +0100)]
ARM: exynos5250: create a DT header defining CLK IDs
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:31 +0000 (15:47 +0100)]
clk: exynos4: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrzej Hajda [Tue, 7 Jan 2014 14:47:29 +0000 (15:47 +0100)]
ARM: exynos4: create a DT header defining CLK IDs
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Fri, 8 Nov 2013 10:14:08 +0000 (15:44 +0530)]
clk: exynos5250: register APLL rate table
Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Mike Turquette [Tue, 31 Dec 2013 19:35:12 +0000 (11:35 -0800)]
Merge branch 'clk-next-unregister' into clk-next
Conflicts:
drivers/clk/clk.c
Mike Turquette [Mon, 30 Dec 2013 18:58:22 +0000 (10:58 -0800)]
Merge branch 'for_3.14/keystone-clk' of git://git./linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone
Sachin Kamat [Thu, 19 Dec 2013 08:33:39 +0000 (14:03 +0530)]
clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:21 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain
This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:20 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Correct parent list of audio muxes
According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:19 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Add missing unpopulated mux parents
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:18 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:17 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:16 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Make names of mux and div clocks consistent
This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Tue, 15 Oct 2013 17:41:15 +0000 (19:41 +0200)]
clk: samsung: exynos5250: Sort definitions by registers and bitfield
This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.
Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tomasz Figa [Mon, 30 Dec 2013 17:15:23 +0000 (18:15 +0100)]
Merge branch 'samsung-fixes' into samsung-next-base
Krzysztof Kozlowski [Tue, 17 Dec 2013 09:56:39 +0000 (10:56 +0100)]
clk: exynos: File scope reg_save array should depend on PM_SLEEP
Move reg_save[] into CONFIG_PM_SLEEP dependency block as it is used only
by suspend and resume functions.
This fixes the warning on CONFIG_PM_SLEEP=n:
drivers/clk/samsung/clk-exynos-audss.c:29:22: warning: ‘reg_save’ defined but not used [-Wunused-variable]
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Abhilash Kesavan [Wed, 11 Dec 2013 11:57:05 +0000 (17:27 +0530)]
clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Abhilash Kesavan [Thu, 12 Dec 2013 03:02:02 +0000 (08:32 +0530)]
ARM: dts: exynos5250: Fix MDMA0 clock number
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller
could cause system failures, due to wrong clock being controlled. This
patch fixes this by specifying correct clock.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Corrected commit message and description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Abhilash Kesavan [Thu, 12 Dec 2013 03:02:01 +0000 (08:32 +0530)]
clk: samsung: exynos5250: Add MDMA0 clocks
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Abhilash Kesavan [Thu, 12 Dec 2013 03:02:00 +0000 (08:32 +0530)]
clk: samsung: exynos5250: Fix ACP gate register offset
The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Andrew Bresticker [Fri, 8 Nov 2013 10:14:07 +0000 (15:44 +0530)]
clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Seung-Woo Kim [Fri, 22 Nov 2013 05:21:08 +0000 (14:21 +0900)]
clk: samsung: exynos4: Correct SRC_MFC register
The SRC_MFC register offset was incorrect, which could cause have caused
wrong calculation of rate of sclk_mfc clock, that could in turn lead to
incorrect operation of MFC. This patch corrects it.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Mike Turquette [Sun, 29 Dec 2013 21:37:56 +0000 (13:37 -0800)]
Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi
Allwinner sunXi SoCs clock changes
This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.
Chen-Yu Tsai [Tue, 24 Dec 2013 13:26:17 +0000 (21:26 +0800)]
clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Emilio López [Mon, 23 Dec 2013 03:32:40 +0000 (00:32 -0300)]
clk: sunxi: support better factor DT nodes
The DT nodes should look like
abc_clk: clk@
deadbeef {
...
clock-output-names = "abc";
}
But our old DT nodes look like
abc: abc@
deadbeef {
...
}
So, let's support both formats, until we can transition everything
to the new, correct one.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:39 +0000 (00:32 -0300)]
clk: sunxi: mod0 support
This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:37 +0000 (00:32 -0300)]
clk: sunxi: add PLL5 and PLL6 support
This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:36 +0000 (00:32 -0300)]
clk: sunxi: make factors_clk_setup return the clock it registers
We will be needing this to register a factor clock as parent with leaf
divisors on a single call.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:34 +0000 (00:32 -0300)]
clk: sunxi: add gating support to PLL1
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:33 +0000 (00:32 -0300)]
clk: sunxi: clean the magic number of mux parents
This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:32 +0000 (00:32 -0300)]
clk: sunxi: register factors clocks behind composite
This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Thu, 19 Dec 2013 05:38:52 +0000 (21:38 -0800)]
clk: remove CONFIG_COMMON_CLK_DEBUG
Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This
eliminates the extra (annoying) step of enabling the config option
manually.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:48 +0000 (16:47 +0530)]
clk: max77686: Remove redundant break
'break' after 'goto' is redundant. Remove it.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Boris BREZILLON [Sat, 21 Dec 2013 09:34:48 +0000 (10:34 +0100)]
clk: add accuracy support for fixed clock
This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.
This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Boris BREZILLON [Sat, 21 Dec 2013 09:34:47 +0000 (10:34 +0100)]
clk: add clk accuracy retrieval support
The clock accuracy is expressed in ppb (parts per billion) and represents
the possible clock drift.
Say you have a clock (e.g. an oscillator) which provides a fixed clock of
20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is
20Hz/20MHz = 1000 ppb (or 1 ppm).
Clock users may need the clock accuracy information in order to choose
the best clock (the one with the best accuracy) across several available
clocks.
This patch adds clk accuracy retrieval support for common clk framework by
means of a new function called clk_get_accuracy.
This function returns the given clock accuracy expressed in ppb.
In order to get the clock accuracy, this implementation adds one callback
called recalc_accuracy to the clk_ops structure.
This callback is given the parent clock accuracy (if the clock is not a
root clock) and should recalculate the given clock accuracy.
This callback is optional and may be implemented if the clock is not
a perfect clock (accuracy != 0 ppb).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Sat, 21 Dec 2013 10:15:27 +0000 (15:45 +0530)]
clk: si570: Remove redundant of_match_ptr helper
'clk_si570_of_match' is always compiled in. Hence the
helper macro is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Mon, 23 Dec 2013 05:55:22 +0000 (21:55 -0800)]
Merge tag 'renesas-clock-for-v3.14' of git://git./linux/kernel/git/horms/renesas into clk-next-shmobile2
Renesas ARM based SoC Clock updates for v3.14
Add support for using emev2 SMU clocks with DT
Mike Turquette [Fri, 20 Dec 2013 20:58:38 +0000 (12:58 -0800)]
Merge tag 'mvebu-clk-3.14' of git://git.infradead.org/linux-mvebu into clk-next
mvebu clock changes for v3.14
- mvebu: add the core divider clock driver
- sparse cleanup
Mike Turquette [Fri, 20 Dec 2013 20:53:02 +0000 (12:53 -0800)]
Merge tag 'zynq-clk-for-3.14-v2' of git://git.xilinx.com/linux-xlnx into clk-next
arm: Xilinx Zynq clk patches for v3.14
- Add support for fclk-enable feature
Soren Brinkmann [Wed, 27 Nov 2013 20:16:23 +0000 (12:16 -0800)]
clk/zynq/clkc: Add 'fclk-enable' feature
In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.
FPGA clocks are handled following the rules below:
If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.
If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sachin Kamat [Tue, 8 Oct 2013 11:17:47 +0000 (16:47 +0530)]
clk: ux500: Remove extra semicolon
Extra semicolon is redundant. Remove it.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:46 +0000 (16:47 +0530)]
clk: vt8500: Staticize vtwm_pll_ops
'vtwm_pll_ops' is local to this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:45 +0000 (16:47 +0530)]
clk: mvebu: Staticize of_cpu_clk_setup
'of_cpu_clk_setup' is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:44 +0000 (16:47 +0530)]
clk: versatile: Staticize clk_sp810_timerclken_of_get
clk_sp810_timerclken_of_get is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:43 +0000 (16:47 +0530)]
clk: socfpga: Use NULL instead of 0
'div_reg' is a pointer. Assign NULL instead of 0.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:42 +0000 (16:47 +0530)]
clk: tegra: Staticize tegra_clk_periph_nodiv_ops
tegra_clk_periph_nodiv_ops is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:41 +0000 (16:47 +0530)]
clk: tegra: Staticize local variables in clk-pll.c
Local variables used only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:40 +0000 (16:47 +0530)]
clk: SPEAr: Staticize clk_frac_ops
clk_frac_ops is local to this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Soren Brinkmann [Sat, 21 Sep 2013 23:40:39 +0000 (16:40 -0700)]
clk: si570: Add a driver for SI570 oscillators
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Stephen Boyd [Wed, 16 Oct 2013 07:40:03 +0000 (00:40 -0700)]
clk: Fix debugfs reparenting NULL pointer dereference
Adding clocks from a kernel module can cause a NULL pointer
dereference if the parent of a clock is added after the clock is
added. This happens because __clk_init() iterates over the list
of orphans and reparents the orphans to the clock being
registered before creating the debugfs entry for the clock.
Create the debugfs entry first before reparenting the orphans.
Unable to handle kernel NULL pointer dereference at virtual address
00000028
pgd =
ef3e4000
[
00000028] *pgd=
bf810831
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in: mmcc_8960(+)
CPU: 0 PID: 52 Comm: modprobe Not tainted
3.12.0-rc2-00023-g1021a28-dirty #659
task:
ef319200 ti:
ef3a6000 task.ti:
ef3a6000
PC is at lock_rename+0x24/0xc4
LR is at debugfs_rename+0x34/0x208
pc : [<
c0317238>] lr : [<
c047dfe4>] psr:
00000013
sp :
ef3a7b88 ip :
ef3a7ba8 fp :
ef3a7ba4
r10:
ef3d51cc r9 :
ef3bc680 r8 :
ef3d5210
r7 :
ef3bc640 r6 :
eee287e0 r5 :
eee287e0 r4 :
00000000
r3 :
ef3bc640 r2 :
00000000 r1 :
eee287e0 r0 :
00000000
Flags: nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control:
10c5787d Table:
af3e406a DAC:
00000015
Process modprobe (pid: 52, stack limit = 0xef3a6240)
Stack: (0xef3a7b88 to 0xef3a8000)
7b80:
ef3bc640 ee4047e0 00000000 eee287e0 ef3a7bec ef3a7ba8
7ba0:
c047dfe4 c0317220 ef3bc680 ef3d51cc ef3a7bdc ef3a7bc0 c06e29d0 c0268784
7bc0:
c08946e8 ef3d5210 00000000 ef3bc700 ef3d5290 ef3d5210 ef3bc680 ef3d51cc
7be0:
ef3a7c0c ef3a7bf0 c05b9e9c c047dfbc 00000000 00000000 ef3d5210 ef3d5290
7c00:
ef3a7c24 ef3a7c10 c05baebc c05b9e30 00000001 00000001 ef3a7c64 ef3a7c28
7c20:
c05bb124 c05bae9c bf000cd8 ef3bc7c0 000000d0 c0ff129c bf001774 00000002
7c40:
ef3bc740 ef3d5290 ef0f9a10 bf001774 bf00042c 00000061 ef3a7c8c ef3a7c68
7c60:
c05bb480 c05baed8 bf001774 ef3d5290 ef0f9a10 bf001774 ef38bc10 ef0f9a00
7c80:
ef3a7cac ef3a7c90 c05bb5a8 c05bb3a0 bf001774 00000062 ef0f9a10 ef38bc18
7ca0:
ef3a7cec ef3a7cb0 bf00010c c05bb56c 00000000 ef38ba00 00000000 ef3d60d0
7cc0:
ef3a7cdc c0fefc24 ef0f9a10 c0a091c0 bf000d24 00000000 bf0029f0 bf006000
7ce0:
ef3a7cfc ef3a7cf0 c05156c0 bf000040 ef3a7d2c ef3a7d00 c0513f5c c05156a8
7d00:
ef3a7d2c ef0f9a10 ef0f9a10 bf000d24 ef0f9a44 c09ca588 00000000 bf006000
7d20:
ef3a7d4c ef3a7d30 c05142b8 c0513ecc ef0fd25c 00000000 bf000d24 c0514214
7d40:
ef3a7d74 ef3a7d50 c0512030 c0514220 ef0050a8 ef0fd250 ef0050f8 bf000d24
7d60:
ef37c100 c09ed150 ef3a7d84 ef3a7d78 c05139c8 c0511fd8 ef3a7
7d80:
c051344c c05139a8 bf000864 c09ca588 ef3a7db4 bf000d24 bf002
7da0:
c09ca588 00000000 ef3a7dcc ef3a7db8 c05149dc c0513360 ef3a7
7dc0:
ef3a7ddc ef3a7dd0 c0515914 c0514960 ef3a7dec ef3a7de0 bf006
7de0:
ef3a7e74 ef3a7df0 c0208800 bf00600c ef3a7e1c ef3a7e00 c04c5
7e00:
ffffffff c09d46c4 00000000 bf0029a8 ef3a7e34 ef3a7e20 c024c
7e20:
ffffffff c09d46c4 ef3a7e5c ef3a7e38 c024e2fc c024ce40 00000
7e40:
ef3a7f48 bf0029b4 bf0029a8 271aeb1c ef3a7f48 bf0029a8 00000001 ef383c00
7e60:
bf0029f0 00000001 ef3a7f3c ef3a7e78 c028fac4 c0208718 bf0029b4 00007fff
7e80:
c028cd58 000000d2 f0065000 00000000 ef3a7ebc 00000000 00000000 bf0029b4
7ea0:
00000000 bf0029ac bf0029b4 ef3a6000 ef3a7efc c08bf128 00000000 00000000
7ec0:
00000000 00000000 00000000 00000000 6e72656b 00006c65 00000000 00000000
7ee0:
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
7f00:
00000000 00000000 00000000 271aeb1c ef3a7f2c 00016376 b6f38008 001d3774
7f20:
00000080 c020f968 ef3a6000 00000000 ef3a7fa4 ef3a7f40 c02904dc c028e178
7f40:
c020f898 010ccfa8 f0065000 00016376 f0073f60 f0073d7d f007a1e8 00002b24
7f60:
000039e4 00000000 00000000 00000000 0000002f 00000030 00000019 00000016
7f80:
00000012 00000000 00000000 010de1b2 b6f38008 010ccfa8 00000000 ef3a7fa8
7fa0:
c020f6c0 c0290434 010de1b2 b6f38008 b6f38008 00016376 001d3774 00000000
7fc0:
010de1b2 b6f38008 010ccfa8 00000080 010de1b2 bedb6f90 010de1c9 0001d8dc
7fe0:
0000000c bedb674c 0001ce30 000094c4 60000010 b6f38008 00000008 0000001d
[<
c0317238>] (lock_rename+0x24/0xc4) from [<
c047dfe4>] (debugfs_rename+0x34/0x208)
[<
c047dfe4>] (debugfs_rename+0x34/0x208) from [<
c05b9e9c>] (clk_debug_reparent+0x78/0xc0)
[<
c05baebc>] (__clk_reparent+0x2c/0x3c) from [<
c05bb124>] (__clk_init+0x258/0x4c8)
[<
c05bb124>] (__clk_init+0x258/0x4c8) from [<
c05bb480>] (_clk_register+0xec/0x1cc)
[<
c05bb480>] (_clk_register+0xec/0x1cc) from [<
c05bb5a8>] (devm_clk_register+0x48/0x7c)
[<
c05bb5a8>] (devm_clk_register+0x48/0x7c) from [<
bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960])
[<
bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) from [<
c05156c0>] (platform_drv_probe+0x24/0x28)
[<
c05156c0>] (platform_drv_probe+0x24/0x28) from [<
c0513f5c>] (driver_probe_device+0x9c/0x354)
[<
c0513f5c>] (driver_probe_device+0x9c/0x354) from [<
c05142b8>] (__driver_attach+0xa4/0xa8)
[<
c05142b8>] (__driver_attach+0xa4/0xa8) from [<
c0512030>] (bus_for_each_dev+0x64/0x98)
[<
c0512030>] (bus_for_each_dev+0x64/0x98) from [<
c05139c8>] (driver_attach+0x2c/0x30)
[<
c05139c8>] (driver_attach+0x2c/0x30) from [<
c051344c>] (bus_add_driver+0xf8/0x2a8)
[<
c051344c>] (bus_add_driver+0xf8/0x2a8) from [<
c05149dc>] (driver_register+0x88/0x104)
[<
c05149dc>] (driver_register+0x88/0x104) from [<
c0515914>] (__platform_driver_register+0x58/0x6c)
[<
c0515914>] (__platform_driver_register+0x58/0x6c) from [<
bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960])
[<
bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) from [<
c0208800>] (do_one_initcall+0xf4/0x1b8)
[<
c0208800>] (do_one_initcall+0xf4/0x1b8) from [<
c028fac4>] (load_module+0x1958/0x22bc)
[<
c028fac4>] (load_module+0x1958/0x22bc) from [<
c02904dc>] (SyS_init_module+0xb4/0x120)
[<
c02904dc>] (SyS_init_module+0xb4/0x120) from [<
c020f6c0>] (ret_fast_syscall+0x0/0x48)
Code:
e1500001 e1a04000 e1a05001 0a000021 (
e5903028)
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Takashi Yoshii [Tue, 8 Oct 2013 05:32:17 +0000 (14:32 +0900)]
clk: emev2: Add support for emev2 SMU clocks with DT
Device tree clock binding document for EMMA Mobile EV2 SMU,
And Common clock framework based implementation of it.
Following nodes are defined to describe clock tree.
- renesas,emev2-smu
- renesas,emev2-smu-clkdiv
- renesas,emev2-smu-gclk
These bindings are designed manually based on
19UH0037EJ1000_SMU : System Management Unit User's Manual
So far, reparent is not implemented, and is fixed to index #0.
Clock tree description is not included, and should be provided
by device-tree.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ulf Hansson [Tue, 12 Nov 2013 10:41:12 +0000 (11:41 +0100)]
MAINTAINERS: Add maintainer for the ARM Ux500 clock driver
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Fri, 13 Dec 2013 03:32:07 +0000 (19:32 -0800)]
Merge tag 'clk-hisilicon' of git://git./linux/kernel/git/hzhuang1/linux into clk-next-hisilicon
Mike Turquette [Fri, 13 Dec 2013 03:29:03 +0000 (19:29 -0800)]
Merge branch 'clk-next-shmobile' into clk-next
Laurent Pinchart [Thu, 17 Oct 2013 21:54:07 +0000 (23:54 +0200)]
clk: shmobile: Add MSTP clock support
MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Laurent Pinchart [Thu, 17 Oct 2013 21:54:07 +0000 (23:54 +0200)]
clk: shmobile: Add DIV6 clock support
DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Laurent Pinchart [Wed, 6 Nov 2013 12:14:19 +0000 (13:14 +0100)]
clk: shmobile: Add R-Car Gen2 clocks support
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Haojian Zhuang [Wed, 11 Dec 2013 05:07:55 +0000 (13:07 +0800)]
clk: hi3620: add gate clock flag
Add missing CLK_SET_RATE_PARENT flag for gate clock.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Haojian Zhuang [Wed, 11 Dec 2013 02:30:29 +0000 (10:30 +0800)]
clk: hi3620: fix wrong flags on divider
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not
CLK_MUX_HIWORD_MASK.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Grygorii Strashko [Sat, 23 Nov 2013 21:31:12 +0000 (16:31 -0500)]
clk: keystone: gate: fix error handling on init
This patch fixes Keystone gate control clock driver initialization path:
1) clk_register_psc() returns error code and not a pure pointer, hence
its return value need to be checked using IS_ERR(clk) macro.
2) Mapped IO memory isn't unmapped in case of errors, hence fix it.
Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Murali Karicheri [Sat, 23 Nov 2013 21:26:52 +0000 (16:26 -0500)]
clk: keystone: use clkod register bits for postdiv
DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.
Also update the Documentation of bindings to reflect the same.
Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Mike Turquette [Wed, 4 Dec 2013 20:14:59 +0000 (12:14 -0800)]
Merge branch 'clk/clk-unregister' of git://linuxtv.org/snawrocki/samsung into clk-next-unregister
Chander Kashyap [Thu, 26 Sep 2013 09:06:35 +0000 (14:36 +0530)]
clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sylwester Nawrocki [Sat, 24 Aug 2013 13:00:10 +0000 (15:00 +0200)]
clk: Implement clk_unregister
clk_unregister() is currently not implemented and it is required when
a clock provider module needs to be unloaded.
Normally the clock supplier module is prevented to be unloaded by
taking reference on the module in clk_get().
For cases when the clock supplier module deinitializes despite the
consumers of its clocks holding a reference on the module, e.g. when
the driver is unbound through "unbind" sysfs attribute, there are
empty clock ops added. These ops are assigned temporarily to struct
clk and used until all consumers release the clock, to avoid invoking
callbacks from the module which just got removed.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Sylwester Nawrocki [Sat, 24 Aug 2013 18:10:41 +0000 (20:10 +0200)]
clk: Add common __clk_get(), __clk_put() implementations
This patch adds common __clk_get(), __clk_put() clkdev helpers that
replace their platform specific counterparts when the common clock
API is used.
The owner module pointer field is added to struct clk so a reference
to the clock supplier module can be taken by the clock consumers.
The owner module is assigned while the clock is being registered,
in functions _clk_register() and __clk_register().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:44 +0000 (17:03 +0200)]
clkdev: Fix race condition in clock lookup from device tree
There is currently a race condition in the device tree part of clk_get()
function, since the pointer returned from of_clk_get_by_name() may become
invalid before __clk_get() call. E.g. due to the clock provider driver
remove() callback being called in between of_clk_get_by_name() and
__clk_get().
Fix this by doing both the look up and __clk_get() operations with the
clock providers list mutex held. This ensures that the clock pointer
returned from __of_clk_get_from_provider() call and passed to __clk_get()
is valid, as long as the clock supplier module first removes its clock
provider instance and then does clk_unregister() on the corresponding
clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:43 +0000 (17:03 +0200)]
clk: Provide not locked variant of of_clk_get_from_provider()
Add helper functions for the of_clk_providers list locking and
an unlocked variant of of_clk_get_from_provider().
These functions are intended to be used in the clkdev to avoid
race condition in the device tree based clock look up in clk_get().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Tue, 29 Oct 2013 19:51:04 +0000 (20:51 +0100)]
omap3isp: Modify clocks registration to avoid circular references
The clock core code is going to be modified so clk_get() takes
reference on the clock provider module. Until the potential circular
reference issue is properly addressed, we pass NULL as the first
argument to clk_register(), in order to disallow sub-devices taking
a reference on the ISP module back trough clk_get(). This should
prevent locking the modules in memory.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Haojian Zhuang [Wed, 13 Nov 2013 00:51:23 +0000 (08:51 +0800)]
clk: hisilicon: add common clock support
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Mike Turquette [Tue, 3 Dec 2013 19:47:56 +0000 (11:47 -0800)]
Merge branch 'clk-tegra-next' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra
Mike Turquette [Sun, 1 Dec 2013 20:42:45 +0000 (12:42 -0800)]
Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next-sunxi-rebase
Allwinner sunXi SoCs clock changes
Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.
Conflicts:
drivers/clk/sunxi/clk-sunxi.c
Wei Yongjun [Tue, 29 Oct 2013 02:07:57 +0000 (03:07 +0100)]
clk: tegra: fix __clk_lookup() return value checks
In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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