Chris Metcalf [Fri, 6 Sep 2013 12:56:45 +0000 (08:56 -0400)]
tile: rework <asm/cmpxchg.h>
The macrology in cmpxchg.h was designed to allow arbitrary pointer
and integer values to be passed through the routines. To support
cmpxchg() on 64-bit values on the 32-bit tilepro architecture, we
used the idiom "(typeof(val))(typeof(val-val))". This way, in the
"size 8" branch of the switch, when the underlying cmpxchg routine
returns a 64-bit quantity, we cast it first to a typeof(val-val)
quantity (i.e. size_t if "val" is a pointer) with no warnings about
casting between pointers and integers of different sizes, then cast
onwards to typeof(val), again with no warnings. If val is not a
pointer type, the additional cast is a no-op. We can't replace the
typeof(val-val) cast with (for example) unsigned long, since then if
"val" is really a 64-bit type, we cast away the high bits.
HOWEVER, this fails with current gcc (through 4.7 at least) if "val"
is a pointer to an incomplete type. Unfortunately gcc isn't smart
enough to realize that "val - val" will always be a size_t type
even if it's an incomplete type pointer.
Accordingly, I've reworked the way we handle the casting. We have
given up the ability to use cmpxchg() on 64-bit values on tilepro,
which is OK in the kernel since we should use cmpxchg64() explicitly
on such values anyway. As a result, I can just use simple "unsigned
long" casts internally.
As I reworked it, I realized it would be cleaner to move the
architecture-specific conditionals for cmpxchg and xchg out of the
atomic.h headers and into cmpxchg, and then use the cmpxchg() and
xchg() primitives directly in atomic.h and elsewhere. This allowed
the cmpxchg.h header to stand on its own without relying on the
implicit include of it that is performed by <asm/atomic.h>.
It also allowed collapsing the atomic_xchg/atomic_cmpxchg routines
from atomic_{32,64}.h into atomic.h.
I improved the tests that guard the allowed size of the arguments
to the routines to use a __compiletime_error() test. (By avoiding
the use of BUILD_BUG, I could include cmpxchg.h into bitops.h as
well and use the macros there, which is otherwise impossible due
to include order dependency issues.)
The tilepro _atomic_xxx internal methods were previously set up to
take atomic_t and atomic64_t arguments, which isn't as convenient
with the new model, so I modified them to take int or u64 arguments,
which is consistent with how they used the arguments internally
anyway, so provided some nice simplification there too.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 30 Aug 2013 14:12:36 +0000 (10:12 -0400)]
tile PCI RC: make default consistent DMA mask 32-bit
This change sets the PCI devices' initial DMA capabilities
conservatively and promotes them at the request of the driver,
as opposed to assuming advanced DMA capabilities. The old design
runs the risk of breaking drivers that assume default capabilities.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Wang Sheng-Hui [Thu, 22 Aug 2013 01:49:42 +0000 (21:49 -0400)]
tile: add null check for kzalloc in tile/kernel/setup.c
Should check the return value of kzalloc first to avoid the null pointer.
Then can dereference the non-null pointer to access the fields of struct
resource.
Signed-off-by: Wang Sheng-Hui <shhuiw@gmail.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Thu, 15 Aug 2013 20:29:02 +0000 (16:29 -0400)]
tile: make __write_once a synonym for __read_mostly
This was really only useful for TILE64 when we mapped the
kernel data with small pages. Now we use a huge page and we
really don't want to map different parts of the kernel
data in different ways.
We retain the __write_once name in case we want to bring
it back to life at some point in the future.
Note that this change uncovered a latent bug where the
"smp_topology" variable happened to always be aligned mod 8
so we could store two "int" values at once, but when we
eliminated __write_once it ended up only aligned mod 4.
Fix with an explicit annotation.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Thu, 15 Aug 2013 20:23:24 +0000 (16:23 -0400)]
tile: remove support for TILE64
This chip is no longer being actively developed for (it was superceded
by the TILEPro64 in 2008), and in any case the existing compiler and
toolchain in the community do not support it. It's unlikely that the
kernel works with TILE64 at this point as the configuration has not been
tested in years. The support is also awkward as it requires maintaining
a significant number of ifdefs. So, just remove it altogether.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Akinobu Mita [Wed, 14 Aug 2013 13:07:30 +0000 (22:07 +0900)]
tile: use asm-generic/bitops/builtin-*.h
The definisions of __ffs(), __fls(), and ffs() for tile are almost same
as asm-generic/bitops-*.h. The only difference is that it is defined
as __always_inline or inline. So this switches to use those headers.
Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> [moved #includes to end]
Chris Metcalf [Tue, 13 Aug 2013 19:37:06 +0000 (15:37 -0400)]
tile: eliminate no-op "noatomichash" boot argument
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 19:33:53 +0000 (15:33 -0400)]
tile: use standard tile_bundle_bits type in traps.c
We were rolling our own bundle_bits, which is unnecessary.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 19:26:23 +0000 (15:26 -0400)]
tile: simplify code referencing hypervisor API addresses
There's no need to make up new ways of computing the addresses
of the Tilera hypervisor APIs; just use the standard method
of relying on the symbols to provide the addresses.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 19:24:14 +0000 (15:24 -0400)]
tile: change <asm/system.h> to <asm/switch_to.h> in comments
Also fix mentions of it in #error statements.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 19:17:38 +0000 (15:17 -0400)]
tile: mark pcibios_init() as __init
It was bombed away because it was previously marked as __devinit,
but it should be an __init function.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 18:42:36 +0000 (14:42 -0400)]
tile: check for correct compiler earlier in asm-offsets.c
If we wait until after including a bunch of other files, we
will have generated so much warning spew that it's hard to
notice the error about using the wrong compiler.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 18:01:58 +0000 (14:01 -0400)]
tile: use standard 'generic-y' model for <asm/hw_irq.h>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 13 Aug 2013 18:00:04 +0000 (14:00 -0400)]
tile: use asm-generic version of <asm/local64.h>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 19:25:22 +0000 (15:25 -0400)]
tile PCI RC: add comment about "PCI hole" problem
Explain the rationale of not overlapping the 64-bit DMA window
with the PA range.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 19:09:18 +0000 (15:09 -0400)]
tile: remove DEBUG_EXTRA_FLAGS kernel config option
It isn't used any more by us now that the generic kernel build
offers DEBUG_INFO_REDUCED, so just get rid of it.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 19:08:09 +0000 (15:08 -0400)]
tile: add virt_to_kpte() API and clean up and document behavior
We use virt_to_pte(NULL, va) a lot, which isn't very obvious.
I added virt_to_kpte(va) as a more obvious wrapper function,
that also validates the va as being a kernel adddress.
And, I fixed the semantics of virt_to_pte() so that we handle
the pud and pmd the same way, and we now document the fact that
we handle the final pte level differently.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 19:00:51 +0000 (15:00 -0400)]
tile: support FRAME_POINTER
Allow enabling frame pointer support; this makes it easier to hook
into the various kernel features that claim they require it without
having to add Kconfig conditionals everywhere (a la mips, ppc, s390,
and microblaze). When enabled, it basically eliminates leaf functions
as such, and stops optimizing tail and sibling calls. It adds around
3% to the size of the kernel when enabled.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 18:39:22 +0000 (14:39 -0400)]
tile: support reporting Tilera hypervisor statistics
Newer hypervisors have an API for reporting per-cpu statistics
information. This change allows seeing that information via
/sys/devices/system/cpu/cpuN/hv_stats file for each core.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 28 Aug 2013 23:53:17 +0000 (19:53 -0400)]
tilegx: support KGDB
Enter kernel debugger at boot with:
--hvd UART_1=1 --hvx kgdbwait --hvx kgdboc=ttyS1,115200
or at runtime with:
echo ttyS1,115200 > /sys/module/kgdboc/parameters/kgdboc
echo g > /proc/sysrq-trigger
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 12 Aug 2013 18:11:44 +0000 (14:11 -0400)]
tilegx: Add tty serial support for TILE-Gx on-chip UART
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Chris Metcalf [Mon, 12 Aug 2013 18:09:28 +0000 (14:09 -0400)]
tilegx: provide kernel support for the tilegx UART shim
The TILE-Gx chip includes an on-chip UART. This change adds support
for using the UART from within the kernel. The UART shim has more
functionality than is exposed here, but to keep the kernel code and
binary simpler, this is a subset of the full API designed to enable
a standard Linux tty serial driver only.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 3 Sep 2013 18:41:36 +0000 (14:41 -0400)]
tile: parameterize VA and PA space more cleanly
The existing code relied on the hardware definition (<arch/chip.h>)
to specify how much VA and PA space was available. It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified
if desired.
Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space. In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".
Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 3 Sep 2013 18:45:52 +0000 (14:45 -0400)]
tile: don't assume user privilege is zero
Technically, user privilege is anything less than kernel
privilege. We modify the existing user_mode() macro to have
this semantic (and use it in a couple of places it wasn't being
used before), and add an IS_KERNEL_EX1() macro to the assembly
code as well.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 3 Sep 2013 18:13:31 +0000 (14:13 -0400)]
tile: clean up relocate_kernel_64 debug code
We remove some debug code in relocate_kernel_64.S that made raw
calls to the hv_console_putc Tilera hypervisor API, since everything
should funnel through the early_hv_write() API.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Sat, 10 Aug 2013 17:15:46 +0000 (13:15 -0400)]
tile: handle super huge pages in virt_to_pte
This tile-specific API had a minor bug, in that if a super huge (>4GB)
page mapped a particular address range, we wouldn't handle it correctly.
As part of fixing that bug, I also cleaned up some of the pud and pmd
accessors to make them more consistent.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Sat, 10 Aug 2013 16:35:02 +0000 (12:35 -0400)]
tilegx: change how we find the kernel stack
Previously, we used a special-purpose register (SPR_SYSTEM_SAVE_K_0)
to hold the CPU number and the top of the current kernel stack
by using the low bits to hold the CPU number, and using the high
bits to hold the address of the page just above where we'd want
the kernel stack to be. That way we could initialize a new SP
when first entering the kernel by just masking the SPR value and
subtracting a couple of words.
However, it's actually more useful to be able to place an arbitrary
kernel-top value in the SPR. This allows us to create a new stack
context (e.g. for virtualization) with an arbitrary top-of-stack VA.
To make this work, we now store the CPU number in the high bits,
above the highest legal VA bit (42 bits in the current tilegx
microarchitecture). The full 42 bits are thus available to store the
top of stack value. Getting the current cpu (a relatively common
operation) is still fast; it's now a shift rather than a mask.
We make this change only for tilegx, since tilepro has too few SPR
bits to do this, and we don't need this support on tilepro anyway.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Sat, 10 Aug 2013 16:22:43 +0000 (12:22 -0400)]
tile: don't call show_regs_print_info() with corrupt current
We use the validate_current() API to make sure that "current" seems
plausible before using it. With the new show_regs_print_info()
API, we want to check that current is OK before calling it, since
otherwise we will end up in a recursive panic.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:53:50 +0000 (16:53 -0400)]
tile: fix some -Wsign-compare warnings
Normally the build doesn't include these warnings, but at one
point I built with -Wsign-compare, and noticed a few things that
are technically bugs. This change fixes those things.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:50:36 +0000 (16:50 -0400)]
tile: group .hottext* sections properly in vmlinux.lds
With this change such sections are grouped with regular text
in the vmlinux image; this change puts them at the front,
which is where the standard Linux includes .text.hot*.
This change should fix a recently-observed bug where a bunch of
symbols were being omitted from the /proc/kallsyms output
because they fell between _etext and _sinittext.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:21:43 +0000 (16:21 -0400)]
tile: fix strncpy_from_user bug
In strncpy_from_user_asm, when the destination buffer length was the
same as the actual string length, we were returning the size of the
destination buffer. But since it's a NUL terminated string, we should
return the length of the string instead.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:17:03 +0000 (16:17 -0400)]
tile: remove set/clear_fixmap APIs
Nothing in the codebase was using them, and as written they took
"unsigned long" as the physical address rather than "phys_addr_t",
which is wrong on tilepro anyway. Rather than fixing stale APIs,
just remove them; if there's ever demand for them on this platform,
we can put them back.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:09:41 +0000 (16:09 -0400)]
tile: do less L1 I-cache eviction
We had been doing an automatic full eviction of the L1 I$
everywhere whenever we did a kernel-space TLB flush. It turns
out this isn't necessary, since all the callers already handle
doing a flush if necessary.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 20:04:34 +0000 (16:04 -0400)]
tile: allow "initrd" boot argument for kexec
This enables support for "kexec --initrd" for tile.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Tony Lu [Fri, 9 Aug 2013 19:45:24 +0000 (15:45 -0400)]
tile: support ASLR fully
With this change, tile Linux now supports address-space layout
randomization for shared objects, stack, heap and vdso.
Acked-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Tony Lu <zlu@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 19:42:56 +0000 (15:42 -0400)]
tile: correct r1 value during syscall tracing
The r1 value is set based on the r0 value as we return to user space.
So tracing tools won't automatically see the right value. Fix this by
generating the correct r1 value in do_syscall_trace_exit() rather
than trying to tamper with the hot path in syscall return.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 19:41:09 +0000 (15:41 -0400)]
tile: fix panic with large IRQ number
The "available_irqs" value needs to actually reflect the IRQs
available, not just start as an all-ones mask, since we only
have 32 IRQs available even on a 64-bit platform.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 9 Aug 2013 19:38:43 +0000 (15:38 -0400)]
tile: use proper .align directives on __ex_table sections
This may fix a reported bug where an R_TILEGX_64 in a module was not
pointing to an aligned address.
Reported-by: Simon Marchi <simon.marchi@polymtl.ca>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Tony Lu [Fri, 9 Aug 2013 19:08:57 +0000 (15:08 -0400)]
tile: support kprobes on tilegx
This change includes support for Kprobes, Jprobes and Return Probes.
Reviewed-by: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Signed-off-by: Tony Lu <zlu@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Tony Lu [Fri, 9 Aug 2013 17:26:09 +0000 (13:26 -0400)]
tile: support ftrace on tilegx
This commit adds support for static ftrace, graph function support,
and dynamic tracer support.
Signed-off-by: Tony Lu <zlu@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 20:03:08 +0000 (16:03 -0400)]
tile: provide traceability for hypervisor calls
This change adds infrastructure (CONFIG_TILE_HVGLUE_TRACE) that
provides C code wrappers for the calls the kernel makes to the Tilera
hypervisor. This allows standard kernel infrastructure like FTRACE to
be able to instrument hypervisor calls.
To allow direct calls to the true API, we export their names with a
leading underscore as well. This is important for the few contexts
where we need to make hypervisor calls without touching the stack.
As part of this change, we also switch from creating the symbols
with linker magic to creating them with assembler magic. This lets
us provide a symbol type and generally make them appear more as symbols
and less as just random values in the Elf namespace.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 19:42:34 +0000 (15:42 -0400)]
tile: avoid struct vm_struct leak
If ioreamp_prot() fails in ioremap_page_range() due to kernel memory
exhaustion, we previously would leak a struct vm_struct.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 19:33:32 +0000 (15:33 -0400)]
tile: implement gettimeofday() via vDSO
This change creates the framework for vDSO calls, makes the existing
rt_sigreturn() mechanism use it, and adds a fast gettimeofday().
Now that we need to expose the vDSO address to userspace, we add
AT_SYSINFO_EHDR to the set of aux entries provided to userspace.
(You can disable any extra vDSO support by booting with vdso=0,
but the rt_sigreturn vDSO page will still be provided.)
Note that glibc has supported the tile vDSO since release 2.17.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 18:07:03 +0000 (14:07 -0400)]
tile: support simulator notification for ET_DYN objects
The tile code notifies the simulator of new ET_EXEC objects starting
to execute so that tracing code can properly annotate the objects.
However, we didn't support ET_DYN executables like ld.so, so we
didn't properly load symbols, etc. This change enables that support;
we use a variant of the SIM_CONTROL_DLOPEN simulator notification
that newer simulators will recognize and use to set the base address
for the next SIM_CONTROL_OS_EXEC notification.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 16:11:56 +0000 (12:11 -0400)]
tile: improve illegal translation interrupt handling
First, don't re-enable interrupts blindly in the Linux trap handler.
We already handle page faults this way; synchronous interrupts like
ILL_TRANS will fire even when interrupts are disabled, and we don't
want to re-enable interrupts in that case.
For ILL_TRANS, we now pass the ILL_VA_PC reason into the trap handler
so we can report it properly; this is the address that caused the
illegal translation trap. We print the address as part of the
pr_alert() message now if it's coming from the kernel.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 16:03:53 +0000 (12:03 -0400)]
tile: make register dumps more readable
It's much easier to read register dumps if you read vertically
rather than horizontally, since the register numbers line up
and lead the eye down more than to the right.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 15:55:35 +0000 (11:55 -0400)]
tile: improve big-endian support
First, fix a bug in asm/unaligned.h; we need to just use the asm-generic
unaligned.h so we properly choose endian-correct flavors.
Second, keep the hv/hypervisor.h ABI fully "native" in the sense that
we don't have __BIG_ENDIAN__ ifdefs there. Instead, we use macros in
the head_NN.S assembly code to properly extract two 32-bit structure
members from a 64-bit register holding the structure.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 15:36:54 +0000 (11:36 -0400)]
tile: support CONFIG_PREEMPT
This change adds support for CONFIG_PREEMPT (full kernel preemption).
In addition to the core support, this change includes a number
of places where we fix up uses of smp_processor_id() and per-cpu
variables. I also eliminate the PAGE_HOME_HERE and PAGE_HOME_UNKNOWN
values for page homing, as it turns out they weren't being used.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 15:07:52 +0000 (11:07 -0400)]
tile: remove calls to arch_flush_lazy_mmu_mode()
Since it's a no-op on tile anyway, there's no reason to be calling
it in tile-specific code.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 15:00:45 +0000 (11:00 -0400)]
tile: fix some issues in hugepage support
First, in huge_pte_offset(), we were erroneously checking
pgd_present(), which is always true, rather than pud_present(),
which is the thing that tells us if there is a top-level (L0) PTE.
Fixing this means we properly look up huge page entries only when
the Present bit is actually set in the PTE.
Second, use the standard pte_alloc_map() instead of the hand-rolled
pte_alloc_hugetlb() routine that basically was written to avoid
worrying about CONFIG_HIGHPTE. However, we no longer plan to support
HIGHPTE, so a separate routine was just unnecessary code duplication.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 14:45:01 +0000 (10:45 -0400)]
tile: add some tile drivers to MAINTAINERS
Also, alphabetize the existing entries for tile.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 20:10:23 +0000 (16:10 -0400)]
tile: avoid recursive backtrace faults
This change adds support for avoiding recursive backtracer crashes;
we haven't seen this in practice other than when things are seriously
corrupt, but it may help avoid losing the root cause of a crash.
Also, don't abort kernel backtracers for invalid userspace PC's.
If we do, we lose the ability to backtrace through a userspace
call to a bad address above PAGE_OFFSET, even though that it can
be perfectly reasonable to continue the backtrace in such a case.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 20:04:13 +0000 (16:04 -0400)]
tile: fast-path unaligned memory access for tilegx
This change enables unaligned userspace memory access via a kernel
fast path on tilegx. The kernel tracks user PC/instruction pairs
per-thread using a direct-mapped cache in userspace. The cache
maps those PC/instruction pairs to JIT'ed instruction sequences that
load or store using byte-wide load store intructions and then
synthesize 2-, 4- or 8-byte load or store results. Once an
instruction has been seen to generate an unaligned access once,
subsequent hits on that instruction typically require overhead
of only around 50 cycles if cache and TLB is hot.
We support the prctl() PR_GET_UNALIGN / PR_SET_UNALIGN sys call to
enable or disable unaligned fixups on a per-process basis.
To do this we pull some of the tilepro unaligned support out of the
single_step.c file; tilepro uses instruction disassembly for both
single-step and unaligned access support. Since tilegx actually has
hardware singlestep support, though, it's cleaner to keep the tilegx
unaligned access code in a separate file. While we're at it,
properly rename the tilepro-specific types, etc., to have tilepro
suffixes instead of generic tile suffixes.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Wed, 7 Aug 2013 14:34:10 +0000 (10:34 -0400)]
tile: remove unnecessary backslashes in asm-offsets.c
Pointed out by checkpatch. A few of the DEFINE() lines were
properly written without backslash continuation; fix the rest.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 18:34:08 +0000 (14:34 -0400)]
tile: fix tilegx vmalloc_sync_all BUG_ON
As specified, the test wasn't correct, and in any case it should
be a BUILD_BUG_ON.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 18:32:49 +0000 (14:32 -0400)]
tile: fix comment bug in sys_cmpxchg description
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 18:29:59 +0000 (14:29 -0400)]
tile: support "memmap" boot parameter
This change adds support for the "memmap" boot parameter similar
to what x86 provides. The tile version supports "memmap=1G$5G",
for example, as a way to reserve a 1 GB range starting at PA 5GB.
The memory is reserved via bootmem during startup, and we create a
suitable "struct resource" marked as "Reserved" so you can see the
range reported by /proc/iomem. Up to 64 such regions can currently
be reserved on the boot command line.
We do not support the x86 options "memmap=nn@ss" (force some memory
to be available at the given address) since it's pointless to try to
have Linux use memory the Tilera hypervisor hasn't given it. We do
not support "memmap=nn#ss" to add an ACPI range for later processing,
since we don't support ACPI. We do not support "memmap=exactmap"
since we don't support reading the e820 information from the BIOS
like x86 does. I did add support for "memmap=nn" (and the synonym
"mem=nn") which cap the highest PA value at "nn"; these are both
just a synonym for the existing tile boot option "maxmem".
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 6 Aug 2013 18:11:21 +0000 (14:11 -0400)]
tile: various console improvements
This change improves and cleans up the tile console.
- We enable HVC_IRQ support on tilegx, with the addition of a new
Tilera hypervisor API for tilegx to allow a console IPI. If IPI
support is not available we fall back to the previous polling mode.
- We simplify the earlyprintk code to use CON_BOOT and eliminate some
of the other supporting earlyprintk code.
- A new tile_console_write() primitive is used to send output to
the console and is factored out of the hvc_tile driver.
This lets us support a "sim_console" boot argument to allow using
simulator hooks to send output to the "console" as a slightly
faster alternative to emulating the hardware more directly.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Chris Metcalf [Mon, 5 Aug 2013 18:40:55 +0000 (14:40 -0400)]
tile PCI RC: remove stale include of linux/numa.h
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 18:33:17 +0000 (14:33 -0400)]
tile PCI RC: reduce driver's vmalloc space usage
We can take advantage of the fact that bit 29 is hard-wired
to zero in register TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR.
This is handy since at the moment we only allocate one 4GB
region for vmalloc, and with this change we can allocate
four or more TRIO MACs without using up all the vmalloc space.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 18:27:05 +0000 (14:27 -0400)]
tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system
On Tilera Gx72 systems, the logic for figuring out whether
a given port is root complex is slightly different.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:45:28 +0000 (13:45 -0400)]
tile PCI DMA: fix bug in non-page-aligned accessors
The code incorrectly masked with PAGE_OFFSET instead of
PAGE_SIZE-1. This only matters when trying to do a
non page-aligned DMA; it was noticed during code inspection.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:40:47 +0000 (13:40 -0400)]
tile PCI RC: add dma_get_required_mask()
The standard kernel function dma_get_required_mask() uses the
highest DRAM address to determine if 32-bit or 64-bit DMA addressing
is needed. This only works on architectures that have direct mapping
between the PA and the PCI address space, i.e. those that don't have
I/O TLBs or have I/O TLB but choose to use direct mapping. Neither
of these are true for tilegx. Whether to use 64-bit DMA should depend
on the PCI device's capability only, not on the amount of DRAM
installeds, so we now advertise a 64-bit DMA mask unconditionally.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:32:52 +0000 (13:32 -0400)]
tile PCI RC: use proper accessor function
Using the low-level hv_dev_pread() API makes assumptions about the
layout of datastructures in the Tilera hypervisor API; it's better to
use the gxio_XXX accessor and the pcie_trio_ports_property struct.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:29:34 +0000 (13:29 -0400)]
tile PCI RC: bomb comments and whitespace format
This change is purely stylistic but improves the readability
of the tile PCI RC driver.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:20:44 +0000 (13:20 -0400)]
tile PCI RC: include pci/pcie/Kconfig
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:18:34 +0000 (13:18 -0400)]
tile PCI RC: eliminate pci_controller.mem_resources field
The .mem_resources[] field in the pci_controller struct
is now obsoleted by the .mem_space and .io_space fields.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 17:18:02 +0000 (13:18 -0400)]
tile PCI RC: restructure TRIO initialization
The TRIO shim initialization is shared with other kernel drivers
such as the endpoint and StreamIO drivers, so reorganize the
initialization flow to ensure that the root complex driver properly
initializes TRIO state regardless of what kind of TRIO driver will
end up using the shim.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 16:37:24 +0000 (12:37 -0400)]
tile PCI DMA: handle a NULL dev argument properly
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 20:45:22 +0000 (16:45 -0400)]
tile PCI RC: support I/O space access
To enable this functionality, configure CONFIG_TILE_PCI_IO. Without
this flag, the kernel still assigns I/O address ranges to the
devices, but no TRIO resource and mapping support is provided.
We assign disjoint I/O address ranges to separate PCIe domains.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 20:12:49 +0000 (16:12 -0400)]
tile PCI RC: gentler warning for missing plug-in PCI
Besides using pr_info() to print the linkdown status for a plug-in
slot, add extra indication that this is expected if the slot is empty.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 16:55:15 +0000 (12:55 -0400)]
tile PCI RC: support more MSI-X interrupt vectors
To support PCIe devices with higher number of MSI-X interrupt vectors,
e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more
MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more
vectors in addition to ~10 from the Map Mem regions.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 16:24:42 +0000 (12:24 -0400)]
tile: support LSI MEGARAID SAS HBA hybrid dma_ops
The LSI MEGARAID SAS HBA suffers from the problem where it can do
64-bit DMA to streaming buffers but not to consistent buffers.
In other words, 64-bit DMA is used for disk data transfers and 32-bit
DMA must be used for control message transfers. According to LSI,
the firmware is not fully functional yet. This change implements a
kind of hybrid dma_ops to support this.
Note that on most other platforms, the 64-bit DMA addressing space is the
same as the 32-bit DMA space and they overlap the physical memory space.
No special arrangement is needed to support this kind of mixed DMA
capability. On TILE-Gx, the 64-bit DMA space is completely separate
from the 32-bit DMA space. Due to the use of the IOMMU, the 64-bit DMA
space doesn't overlap the physical memory space. On the other hand,
the 32-bit DMA space overlaps the physical memory space under 4GB.
The separate address spaces make it necessary to have separate dma_ops.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 15:56:44 +0000 (11:56 -0400)]
tile PCI RC: handle case that PCI link is already up
If we are rebooting (e.g. via kexec) then the PCI RC link may
already be up. In that case, we don't want to do the software
fixup to force the link up, since that can degrade it to Gen1.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 15:47:29 +0000 (11:47 -0400)]
tile PCI RC: tweak the the pcie_rc_delay support
Allow longer delays if requested, and print the info messages
as we are performing the delay, not when parsing the arguments.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Mon, 5 Aug 2013 19:02:03 +0000 (15:02 -0400)]
tile PCI RC: support pci=off boot arg for tilepro
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 20:18:58 +0000 (16:18 -0400)]
tile PCI RC: tilepro conflict with PCI and RAM addresses
Fix a bug in the tilepro PCI resource allocation code that could make
the bootmem allocator unhappy if 4GB is installed on mshim 0.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Fri, 2 Aug 2013 15:59:06 +0000 (11:59 -0400)]
tile PCI RC: cleanups for tilepro PCI RC
- remove unneeded <linux/bootmem.h> include in pci.c
- eliminate unused pci_controller.first_busno field
- prefer msleep to mdelay
- remove stale comment about pci_scan_bus_parented()
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Ken Steele [Thu, 1 Aug 2013 19:55:07 +0000 (15:55 -0400)]
tile: optimize strnlen using SIMD instructions
Using strlen as a model, add length checking to create strnlen.
Signed-off-by: Ken Steele <ken@tilera.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Thu, 1 Aug 2013 19:52:17 +0000 (15:52 -0400)]
tile: optimize and clean up string functions
This change cleans up the string code in a number of ways:
- For memcpy(), fix bug in prefetch and increase distance to 3 lines;
optimize for unaligned data; do all loads before wh64 to make memcpy
safe for forward-overlapping calls; etc. Performance is improved.
- Use new copy_byte() function on tilegx to spread a single byte value
out into a full word using the shufflebytes instruction.
- Clean up header include ordering to be more canonical, and remove
spurious #undefs of function names.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 23 Jul 2013 21:32:04 +0000 (17:32 -0400)]
tile: convert uses of "inv" to "finv"
The "inv" (invalidate) instruction is generally less safe than "finv"
(flush and invalidate), as it will drop dirty data from the cache.
It turns out we have almost no need for "inv" (other than for the
older 32-bit architecture in some limited cases), so convert to
"finv" where possible and delete the extra "inv" infrastructure.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf [Tue, 23 Jul 2013 21:18:05 +0000 (17:18 -0400)]
tile: various minor cleanups to hardwall subsystem
First, clean up active hardwalls in exit_thread(). This is a better
place than in arch_release_thread_info().
Second, mask out any non-online cpus from the cpumask after
validating any required semantics of the cpu set.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Sachin Kamat [Fri, 3 May 2013 09:23:42 +0000 (14:53 +0530)]
edac: Remove redundant platform_set_drvdata()
Commit
0998d06310 (device-core: Ensure drvdata = NULL when no
driver is bound) removes the need to set driver data field to
NULL.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chen Gang [Mon, 1 Jul 2013 02:21:51 +0000 (10:21 +0800)]
arch: tile: include: asm: add cmpxchg64() definition
Need add cmpxchg64(), or will cause compiling issue.
Need define it as cmpxchg() only for 64-bit operation, since cmpxchg()
can support 8 bytes.
The related error (with allmodconfig):
drivers/block/blockconsole.c: In function ‘bcon_advance_console_bytes’:
drivers/block/blockconsole.c:164:2: error: implicit declaration of function ‘cmpxchg64’ [-Werror=implicit-function-declaration]
Signed-off-by: Chen Gang <gang.chen@asianux.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Linus Torvalds [Sun, 14 Jul 2013 22:18:27 +0000 (15:18 -0700)]
Linux 3.11-rc1
Linus Torvalds [Sun, 14 Jul 2013 22:14:29 +0000 (15:14 -0700)]
Merge branch 'slab/for-linus' of git://git./linux/kernel/git/penberg/linux
Pull slab update from Pekka Enberg:
"Highlights:
- Fix for boot-time problems on some architectures due to
init_lock_keys() not respecting kmalloc_caches boundaries
(Christoph Lameter)
- CONFIG_SLUB_CPU_PARTIAL requested by RT folks (Joonsoo Kim)
- Fix for excessive slab freelist draining (Wanpeng Li)
- SLUB and SLOB cleanups and fixes (various people)"
I ended up editing the branch, and this avoids two commits at the end
that were immediately reverted, and I instead just applied the oneliner
fix in between myself.
* 'slab/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/linux
slub: Check for page NULL before doing the node_match check
mm/slab: Give s_next and s_stop slab-specific names
slob: Check for NULL pointer before calling ctor()
slub: Make cpu partial slab support configurable
slab: add kmalloc() to kernel API documentation
slab: fix init_lock_keys
slob: use DIV_ROUND_UP where possible
slub: do not put a slab to cpu partial list when cpu_partial is 0
mm/slub: Use node_nr_slabs and node_nr_objs in get_slabinfo
mm/slub: Drop unnecessary nr_partials
mm/slab: Fix /proc/slabinfo unwriteable for slab
mm/slab: Sharing s_next and s_stop between slab and slub
mm/slab: Fix drain freelist excessively
slob: Rework #ifdeffery in slab.h
mm, slab: moved kmem_cache_alloc_node comment to correct place
Steven Rostedt [Thu, 17 Jan 2013 18:10:58 +0000 (13:10 -0500)]
slub: Check for page NULL before doing the node_match check
In the -rt kernel (mrg), we hit the following dump:
BUG: unable to handle kernel NULL pointer dereference at (null)
IP: [<
ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180
PGD
a2d39067 PUD
b1641067 PMD 0
Oops: 0000 [#1] PREEMPT SMP
Modules linked in: sunrpc cpufreq_ondemand ipv6 tg3 joydev sg serio_raw pcspkr k8temp amd64_edac_mod edac_core i2c_piix4 e100 mii shpchp ext4 mbcache jbd2 sd_mod crc_t10dif sr_mod cdrom sata_svw ata_generic pata_acpi pata_serverworks radeon ttm drm_kms_helper drm hwmon i2c_algo_bit i2c_core dm_mirror dm_region_hash dm_log dm_mod
CPU 3
Pid: 20878, comm: hackbench Not tainted 3.6.11-rt25.14.el6rt.x86_64 #1 empty empty/Tyan Transport GT24-B3992
RIP: 0010:[<
ffffffff811573f1>] [<
ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180
RSP: 0018:
ffff8800a9b17d70 EFLAGS:
00010213
RAX:
0000000000000000 RBX:
0000000001200011 RCX:
ffff8800a06d8000
RDX:
0000000004d92a03 RSI:
00000000000000d0 RDI:
ffff88013b805500
RBP:
ffff8800a9b17dc0 R08:
ffff88023fd14d10 R09:
ffffffff81041cbd
R10:
00007f4e3f06e9d0 R11:
0000000000000246 R12:
ffff88013b805500
R13:
ffff8801ff46af40 R14:
0000000000000001 R15:
0000000000000000
FS:
00007f4e3f06e700(0000) GS:
ffff88023fd00000(0000) knlGS:
0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0:
000000008005003b
CR2:
0000000000000000 CR3:
00000000a2d3a000 CR4:
00000000000007e0
DR0:
0000000000000000 DR1:
0000000000000000 DR2:
0000000000000000
DR3:
0000000000000000 DR6:
00000000ffff0ff0 DR7:
0000000000000400
Process hackbench (pid: 20878, threadinfo
ffff8800a9b16000, task
ffff8800a06d8000)
Stack:
ffff8800a9b17da0 ffffffff81202e08 ffff8800a9b17de0 000000d001200011
0000000001200011 0000000001200011 0000000000000000 0000000000000000
00007f4e3f06e9d0 0000000000000000 ffff8800a9b17e60 ffffffff81041cbd
Call Trace:
[<
ffffffff81202e08>] ? current_has_perm+0x68/0x80
[<
ffffffff81041cbd>] copy_process+0xdd/0x15b0
[<
ffffffff810a2125>] ? rt_up_read+0x25/0x30
[<
ffffffff8104369a>] do_fork+0x5a/0x360
[<
ffffffff8107c66b>] ? migrate_enable+0xeb/0x220
[<
ffffffff8100b068>] sys_clone+0x28/0x30
[<
ffffffff81527423>] stub_clone+0x13/0x20
[<
ffffffff81527152>] ? system_call_fastpath+0x16/0x1b
Code: 89 fc 89 75 cc 41 89 d6 4d 8b 04 24 65 4c 03 04 25 48 ae 00 00 49 8b 50 08 4d 8b 28 49 8b 40 10 4d 85 ed 74 12 41 83 fe ff 74 27 <48> 8b 00 48 c1 e8 3a 41 39 c6 74 1b 8b 75 cc 4c 89 c9 44 89 f2
RIP [<
ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180
RSP <
ffff8800a9b17d70>
CR2:
0000000000000000
---[ end trace
0000000000000002 ]---
Now, this uses SLUB pretty much unmodified, but as it is the -rt kernel
with CONFIG_PREEMPT_RT set, spinlocks are mutexes, although they do
disable migration. But the SLUB code is relatively lockless, and the
spin_locks there are raw_spin_locks (not converted to mutexes), thus I
believe this bug can happen in mainline without -rt features. The -rt
patch is just good at triggering mainline bugs ;-)
Anyway, looking at where this crashed, it seems that the page variable
can be NULL when passed to the node_match() function (which does not
check if it is NULL). When this happens we get the above panic.
As page is only used in slab_alloc() to check if the node matches, if
it's NULL I'm assuming that we can say it doesn't and call the
__slab_alloc() code. Is this a correct assumption?
Acked-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Signed-off-by: Pekka Enberg <penberg@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 14 Jul 2013 18:42:26 +0000 (11:42 -0700)]
Merge branch 'for-linus' of git://git./linux/kernel/git/viro/vfs
Pull more vfs stuff from Al Viro:
"O_TMPFILE ABI changes, Oleg's fput() series, misc cleanups, including
making simple_lookup() usable for filesystems with non-NULL s_d_op,
which allows us to get rid of quite a bit of ugliness"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
sunrpc: now we can just set ->s_d_op
cgroup: we can use simple_lookup() now
efivarfs: we can use simple_lookup() now
make simple_lookup() usable for filesystems that set ->s_d_op
configfs: don't open-code d_alloc_name()
__rpc_lookup_create_exclusive: pass string instead of qstr
rpc_create_*_dir: don't bother with qstr
llist: llist_add() can use llist_add_batch()
llist: fix/simplify llist_add() and llist_add_batch()
fput: turn "list_head delayed_fput_list" into llist_head
fs/file_table.c:fput(): add comment
Safer ABI for O_TMPFILE
Al Viro [Sun, 14 Jul 2013 13:55:39 +0000 (17:55 +0400)]
sunrpc: now we can just set ->s_d_op
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 13:50:23 +0000 (17:50 +0400)]
cgroup: we can use simple_lookup() now
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 13:48:35 +0000 (17:48 +0400)]
efivarfs: we can use simple_lookup() now
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 13:43:25 +0000 (17:43 +0400)]
make simple_lookup() usable for filesystems that set ->s_d_op
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 13:16:52 +0000 (17:16 +0400)]
configfs: don't open-code d_alloc_name()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 13:09:57 +0000 (17:09 +0400)]
__rpc_lookup_create_exclusive: pass string instead of qstr
... and use d_hash_and_lookup() instead of open-coding it, for fsck sake...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Al Viro [Sun, 14 Jul 2013 12:43:54 +0000 (16:43 +0400)]
rpc_create_*_dir: don't bother with qstr
just pass the name
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Linus Torvalds [Sun, 14 Jul 2013 01:08:23 +0000 (18:08 -0700)]
Merge branch 'for_linus' of git://cavan.codon.org.uk/platform-drivers-x86
Pull x86 platform driver updates from Matthew Garrett:
"Nothing overly exciting here - a couple of new drivers that don't do a
great deal, along with some miscellaneous fixes and a couple of small
feature enablement patches"
* 'for_linus' of git://cavan.codon.org.uk/platform-drivers-x86:
x86 platform drivers: fix gpio leak
toshiba_acpi: Add dependency on SERIO_I8042
asus-nb-wmi: set wapf=4 for ASUSTeK COMPUTER INC. 1015E/U
Add trivial driver to disable Intel Smart Connect
Add support driver for Intel Rapid Start Technology
hp-wmi: add supports for POST code error
asus-wmi: control wlan-led only if wapf == 4
drivers/platform/x86/intel_ips: Convert to module_pci_driver
asus-nb-wmi: ignore ALS notification key code
asus-wmi: append newline to messages
x86: asus-laptop: fix invalid point access
x86: msi-laptop: fix memleak
amilo-rfkill: Add dependency on SERIO_I8042
dell-laptop: fix error return code in dell_init()
hp-wmi: Enable hotkeys on some systems
Linus Torvalds [Sun, 14 Jul 2013 01:05:13 +0000 (18:05 -0700)]
Merge branch 'for-linus' of git://git./linux/kernel/git/dtor/input
Pull second round of input updates from Dmitry Torokhov:
"An update to Elantech driver to support hardware v7, fix to the new
cyttsp4 driver to use proper addressing, ads7846 device tree support
and nspire-keypad got a small cleanup."
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input:
Input: nspire-keypad - replace magic offset with define
Input: elantech - fix for newer hardware versions (v7)
Input: cyttsp4 - use 16bit address for I2C/SPI communication
Input: ads7846 - add device tree bindings
Input: ads7846 - make sure we do not change platform data
Linus Torvalds [Sun, 14 Jul 2013 00:42:22 +0000 (17:42 -0700)]
Merge git://git./linux/kernel/git/davem/net
Pull networking fixes from David Miller:
"Just a bunch of small fixes and tidy ups:
1) Finish the "busy_poll" renames, from Eliezer Tamir.
2) Fix RCU stalls in IFB driver, from Ding Tianhong.
3) Linearize buffers properly in tun/macvtap zerocopy code.
4) Don't crash on rmmod in vxlan, from Pravin B Shelar.
5) Spinlock used before init in alx driver, from Maarten Lankhorst.
6) A sparse warning fix in bnx2x broke TSO checksums, fix from Dmitry
Kravkov.
7) Dummy and ifb driver load failure paths can oops, fixes from Tan
Xiaojun and Ding Tianhong.
8) Correct MTU calculations in IP tunnels, from Alexander Duyck.
9) Account all TCP retransmits in SNMP stats properly, from Yuchung
Cheng.
10) atl1e and via-rhine do not handle DMA mapping failures properly,
from Neil Horman.
11) Various equal-cost multipath route fixes in ipv6 from Hannes
Frederic Sowa"
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (36 commits)
ipv6: only static routes qualify for equal cost multipathing
via-rhine: fix dma mapping errors
atl1e: fix dma mapping warnings
tcp: account all retransmit failures
usb/net/r815x: fix cast to restricted __le32
usb/net/r8152: fix integer overflow in expression
net: access page->private by using page_private
net: strict_strtoul is obsolete, use kstrtoul instead
drivers/net/ieee802154: don't use devm_pinctrl_get_select_default() in probe
drivers/net/ethernet/cadence: don't use devm_pinctrl_get_select_default() in probe
drivers/net/can/c_can: don't use devm_pinctrl_get_select_default() in probe
net/usb: add relative mii functions for r815x
net/tipc: use %*phC to dump small buffers in hex form
qlcnic: Adding Maintainers.
gre: Fix MTU sizing check for gretap tunnels
pkt_sched: sch_qfq: remove forward declaration of qfq_update_agg_ts
pkt_sched: sch_qfq: improve efficiency of make_eligible
gso: Update tunnel segmentation to support Tx checksum offload
inet: fix spacing in assignment
ifb: fix oops when loading the ifb failed
...
Linus Torvalds [Sun, 14 Jul 2013 00:41:21 +0000 (17:41 -0700)]
Merge tag 'scsi-for-linus' of git://git./linux/kernel/git/jejb/scsi
Pull final round of SCSI updates from James Bottomley:
"This is the remaining set of SCSI patches for the merge window. It's
mostly driver updates (scsi_debug, qla2xxx, storvsc, mp3sas). There
are also several bug fixes in fcoe, libfc, and megaraid_sas. We also
have a couple of core changes to try to make device destruction more
deterministic"
* tag 'scsi-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (46 commits)
[SCSI] scsi constants: command, sense key + additional sense strings
fcoe: Reduce number of sparse warnings
fcoe: Stop fc_rport_priv structure leak
libfcoe: Fix meaningless log statement
libfc: Differentiate echange timer cancellation debug statements
libfc: Remove extra space in fc_exch_timer_cancel definition
fcoe: fix the link error status block sparse warnings
fcoe: Fix smatch warning in fcoe_fdmi_info function
libfc: Reject PLOGI from nodes with incompatible role
[SCSI] enable destruction of blocked devices which fail LUN scanning
[SCSI] Fix race between starved list and device removal
[SCSI] megaraid_sas: fix a bug for 64 bit arches
[SCSI] scsi_debug: reduce duplication between prot_verify_read and prot_verify_write
[SCSI] scsi_debug: simplify offset calculation for dif_storep
[SCSI] scsi_debug: invalidate protection info for unmapped region
[SCSI] scsi_debug: fix NULL pointer dereference with parameters dif=0 dix=1
[SCSI] scsi_debug: fix incorrectly nested kmap_atomic()
[SCSI] scsi_debug: fix invalid address passed to kunmap_atomic()
[SCSI] mpt3sas: Bump driver version to v02.100.00.00
[SCSI] mpt3sas: when async scanning is enabled then while scanning, devices are removed but their transport layer entries are not removed
...
Linus Torvalds [Sat, 13 Jul 2013 22:37:57 +0000 (15:37 -0700)]
Merge branch 'sched-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull scheduler fix from Thomas Gleixner:
"Fix a potential deadlock versus hrtimers"
* 'sched-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
sched: Fix HRTICK
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