Tom Tromey [Fri, 16 Nov 2018 22:30:35 +0000 (15:30 -0700)]
Handle TYPE_CODE_PTR when printing Rust types
This changes the Rust type printers to handle TYPE_CODE_PTR. The
current approach is not ideal, because currently the code can't
distinguish between mut and const, or between pointers and references.
(These are debuginfo deficiencies, for which there are rustc bugs on
file.)
Meanwhile, this at least clears up the case seen in PR rust/23625.
Tested on x86-64 Fedora 28. The nightly compiler gives the best
results, but I regression-tested with stable and beta as well.
gdb/ChangeLog
2018-11-16 Tom Tromey <tom@tromey.com>
PR rust/23625:
* rust-lang.c (rust_internal_print_type): Handle TYPE_CODE_PTR.
gdb/testsuite/ChangeLog
2018-11-19 Tom Tromey <tom@tromey.com>
PR rust/23625:
* gdb.rust/simple.exp: Add ptype test. Update expected output.
* gdb.rust/expr.exp: Update expected output. Change one test.
Tom Tromey [Mon, 19 Nov 2018 17:52:32 +0000 (10:52 -0700)]
Fix gdb.rust/simple.rs for more recent compilers
gdb.rust/simple.exp will fail when run with a recent version of rustc.
This patch fixes the test case so that it will continue to run.
Tested on x86-64 Fedora 28.
I also temporarily backed out the rust-lang.c from
commit
098b2108a2b61531c0bc8ea16854f773083a95d7, and verified that
this updated test still would have provoked the original bug.
gdb/testsuite/ChangeLog
2018-11-19 Tom Tromey <tom@tromey.com>
* gdb.rust/simple.rs: Don't initialize empty_enum_value.
Simon Marchi [Mon, 19 Nov 2018 16:05:13 +0000 (11:05 -0500)]
Use std::forward_list for displaced_step_inferior_states
Use std::forward_list instead of manually implemented list. This
simplifies a bit the code, especially around removal.
Regtested on the buildbot. There are some failures as always, but I
think they are unrelated.
gdb/ChangeLog:
* infrun.c (displaced_step_inferior_states): Change type to
std::forward_list.
(get_displaced_stepping_state): Adjust.
(displaced_step_in_progress_any_inferior): Adjust.
(add_displaced_stepping_state): Adjust.
(remove_displaced_stepping_state): Adjust.
John Darrington [Mon, 19 Nov 2018 16:36:42 +0000 (17:36 +0100)]
GDB: Add ChangeLog entry inadvertently omitted from commit.
Pedro Alves [Mon, 19 Nov 2018 15:08:46 +0000 (15:08 +0000)]
gdb.base/warning.exp tweaks
#1- Check that the warning is emitted.
#2- Avoid overriding INTERNAL_GDBFLAGS, as per documentated in
gdb/testsuite/README:
~~~
The testsuite does not override a value provided by the user.
~~~
We don't actually need to tweak INTERNAL_GDBFLAGS, we just need to
append out -data-directory to GDBFLAGS, because each passed
-data-directory option leads to a call to the warning:
$ ./gdb -data-directory=foo -data-directory=bar
Warning: foo: No such file or directory.
Warning: bar: No such file or directory.
[...]
gdb/ChangeLog
2018-11-19 Pedro Alves <palves@redhat.com>
* gdb.base/warning.exp: Don't override INTERNAL_FLAGS. Use
gdb_spawn_with_cmdline_opts instead of gdb_start. Check that we
see the expected warning.
GDB Administrator [Mon, 19 Nov 2018 00:00:29 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Wed, 14 Nov 2018 16:29:51 +0000 (09:29 -0700)]
Fix ia64-linux-nat.c
PR build/23814 points out that ia64-linux-nat.c will not compile any
more. This patch fixes the problem. Thanks to Andreas Schwab for
trying the patch.
gdb/ChangeLog
2018-11-18 Tom Tromey <tom@tromey.com>
PR build/23814:
* target-delegates.c: Rebuild.
* ia64-linux-nat.c (class ia64_linux_nat_target)
<have_steppable_watchpoint>: Use override. Return true, not 1.
(ia64_linux_nat_target::can_use_hw_breakpoint): Rename. Remove
"self" argument.
(ia64_linux_nat_target::low_new_thread): Rename.
(class ia64_linux_nat_target) <read_description>: Don't declare.
* target.h (struct target_ops) <have_steppable_watchpoint>: Return
bool.
GDB Administrator [Sun, 18 Nov 2018 00:01:35 +0000 (00:01 +0000)]
Automatic date update in version.in
GDB Administrator [Sat, 17 Nov 2018 00:00:40 +0000 (00:00 +0000)]
Automatic date update in version.in
Alan Hayward [Thu, 11 Oct 2018 13:47:30 +0000 (14:47 +0100)]
Aarch64: Fix segfault when casting dummy calls
The following will segfault on aarch64 if foo is in another object,
was compiled as c++ and has no debug symbols:
(gdb) p (int)foo()
This is because aarch64_push_dummy_call determines the return type
of the function and then does not check for null pointer.
A null pointer for the return type means the call has no debug
information. For the code to get here, then the call must have
been cast, otherwise we'd error out sooner. In the case of a
no-debug-info call cast, the return type is the type the user
had cast the call to, but we do not have that information
available here.
However, aarch64_push_dummy_call only requires the return type in
order to calculate lang_struct_return. This information is available
in the return_method enum. The fix is to simply use this instead.
Adds testcase to check calls across objects, with all combinations
of c, c++, debug and no debug.
gdb/ChangeLog:
PR gdb/22736:
* aarch64-tdep.c (aarch64_push_dummy_call): Remove
lang_struct_return code.
gdb/testsuite/ChangeLog:
PR gdb/22736:
* gdb.cp/infcall-nodebug-lib.c: New test.
* gdb.cp/infcall-nodebug-main.c: New test.
* gdb.cp/infcall-nodebug.exp: New file.
Alan Hayward [Fri, 16 Nov 2018 11:21:04 +0000 (11:21 +0000)]
Pass return_method to _push_dummy_call
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_push_dummy_call): Replace arg with
return_method.
* alpha-tdep.c (alpha_push_dummy_call): Likewise.
* amd64-tdep.c (amd64_push_arguments): Likewise.
(amd64_push_dummy_call): Likewise.
* amd64-windows-tdep.c (amd64_windows_push_arguments): Likewise.
* arc-tdep.c (arc_push_dummy_call): Likewise.
* arm-tdep.c (arm_push_dummy_call): Likewise.
* avr-tdep.c (avr_push_dummy_call): Likewise.
* bfin-tdep.c (bfin_push_dummy_call): Likewise.
* cris-tdep.c (cris_push_dummy_call): Likewise.
* csky-tdep.c (csky_push_dummy_call): Likewise.
* frv-tdep.c (frv_push_dummy_call): Likewise.
* gdbarch.c: Regenerate.
* gdbarch.h: Regenerate.
* gdbarch.sh (gdbarch_push_dummy_call): Replace arg with
return_method.
* h8300-tdep.c (h8300_push_dummy_call): Likewise.
* hppa-tdep.c (hppa32_push_dummy_call): Likewise.
(hppa64_push_dummy_call): Likewise.
* i386-darwin-tdep.c (i386_darwin_push_dummy_call): Likewise.
* i386-tdep.c (i386_push_dummy_call): Likewise.
* ia64-tdep.c (ia64_push_dummy_call): Likewise.
* infcall.c (call_function_by_hand_dummy): Likewise.
* iq2000-tdep.c (iq2000_push_dummy_call): Likewise.
* lm32-tdep.c (lm32_push_dummy_call): Likewise.
* m32c-tdep.c (m32c_push_dummy_call): Likewise.
* m32r-tdep.c (m32r_push_dummy_call): Likewise.
* m68hc11-tdep.c (m68hc11_push_dummy_call): Likewise.
* m68k-tdep.c (m68k_push_dummy_call): Likewise.
* mep-tdep.c (mep_push_dummy_call): Likewise.
* mips-tdep.c (mips_eabi_push_dummy_call): Likewise.
(mips_n32n64_push_dummy_call): Likewise.
(mips_o32_push_dummy_call): Likewise.
(mips_o64_push_dummy_call): Likewise.
* mn10300-tdep.c (mn10300_push_dummy_call): Likewise.
* msp430-tdep.c (msp430_push_dummy_call): Likewise.
* nds32-tdep.c (nds32_push_dummy_call): Likewise.
* nios2-tdep.c (nios2_push_dummy_call): Likewise.
* or1k-tdep.c (or1k_push_dummy_call): Likewise.
* ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Likewise.
(ppc64_sysv_abi_push_dummy_call): Likewise.
* ppc-tdep.h (ppc_sysv_abi_push_dummy_call): Likewise.
(ppc64_sysv_abi_push_dummy_call): Likewise.
* riscv-tdep.c (riscv_push_dummy_call): Likewise.
* rl78-tdep.c (rl78_push_dummy_call): Likewise.
* rs6000-aix-tdep.c (rs6000_push_dummy_call): Likewise.
* rs6000-lynx178-tdep.c (rs6000_lynx178_push_dummy_call): Likewise.
* rx-tdep.c (rx_push_dummy_call): Likewise.
* s390-tdep.c (s390_push_dummy_call): Likewise.
* score-tdep.c (score_push_dummy_call): Likewise.
* sh-tdep.c (sh_push_dummy_call_fpu): Likewise.
(sh_push_dummy_call_nofpu): Likewise.
* sparc-tdep.c (sparc32_store_arguments): Likewise.
(sparc32_push_dummy_call): Likewise.
* sparc64-tdep.c (sparc64_store_arguments): Likewise.
(sparc64_push_dummy_call): Likewise.
* spu-tdep.c (spu_push_dummy_call): Likewise.
* tic6x-tdep.c (tic6x_push_dummy_call): Likewise.
* tilegx-tdep.c (tilegx_push_dummy_call): Likewise.
* v850-tdep.c (v850_push_dummy_call): Likewise.
* vax-tdep.c (vax_push_dummy_call): Likewise.
* xstormy16-tdep.c (xstormy16_push_dummy_call): Likewise.
* xtensa-tdep.c (xtensa_push_dummy_call): Likewise.
Alan Hayward [Fri, 16 Nov 2018 11:21:00 +0000 (11:21 +0000)]
Use enum for return method for dummy calls
In call_function_by_hand_dummy, struct_return and hidden_first_param_p
are used to represent a single concept. Replace with an enum.
gdb/ChangeLog:
* gdbarch.sh (enum function_call_return_method): Add enum.
* gdbarch.h: Regenerate.
* infcall.c (call_function_by_hand_dummy): Replace vars with enum.
Nick Clifton [Fri, 16 Nov 2018 11:35:24 +0000 (11:35 +0000)]
(Another) Updated Spanish translation for the ld subdirectory.
* po/es.po: Updated Spanish translation.
GDB Administrator [Fri, 16 Nov 2018 00:01:06 +0000 (00:01 +0000)]
Automatic date update in version.in
Joel Brobecker [Thu, 15 Nov 2018 15:53:57 +0000 (10:53 -0500)]
Move copy_bitwise unittests to own unittest file
Now that copy_bitwise has been made public, and considering that
its implementation could move to a different file again in the future,
this patch moves its unittest to its own file in gdb/unittests.
gdb/ChangeLog:
* unittests/copy_bitwise-selftests.c: New file.
* utils.c (selftests::bits_to_str, selftests::check_copy_bitwise)
(selftests::copy_bitwise_tests): Delete, moving this code to
unittests/copy_bitwise-selftests.c instead.
(_initialize_utils): Do not register copy_bitwise tests.
* Makefile.in (SUBDIR_UNITTESTS_SRCS): Add
unittests/copy_bitwise-selftests.c.
Tested on x86_64-linux using the official testsuite, but also by
verifying that "maintenance selftests" still runs the copy_bitwise
tests.
Nick Clifton [Thu, 15 Nov 2018 11:55:24 +0000 (11:55 +0000)]
Updated Spanish translation for the ld subdirectory.
ld * po/es.po: Updated Spanish translation.
GDB Administrator [Thu, 15 Nov 2018 00:00:41 +0000 (00:00 +0000)]
Automatic date update in version.in
Joel Brobecker [Wed, 14 Nov 2018 23:18:49 +0000 (18:18 -0500)]
delete ada-lang.c::move_bits, sharing and re-using copy_bitwise instead
This patch deletes ada-lang.c's move_bits function entirely, and
replaces all calls to it by calls to copy_bitwise instead. Because
the latter function was declared locally inside dwarf2loc.c, this
patch also move the function to a common area, and makes it non-static.
gdb/ChangeLog:
* ada-lang.c (move_bits): Delete. Update all callers to use
copy_bitwise instead.
* dwarf2loc.c (copy_bitwise, bits_to_str::bits_to_str)
(selftests::check_copy_bitwise, selftests::copy_bitwise_tests):
Move from here to utils.c.
(_initialize_dwarf2loc): Remove call to register copy_bitwise
selftests.
* utils.h (copy_bitwise): Add declaration.
* utils.c (copy_bitwise, bits_to_str::bits_to_str)
(selftests::check_copy_bitwise, selftests::copy_bitwise_tests):
Moved here from dwarf2loc.c.
(_initialize_utils): Register copy_bitwise selftests.
Tested on x86_64-linux, no regression. Also tested using AdaCore's
testsuite on a collection of small endian and big endian platforms.
Jim Wilson [Wed, 14 Nov 2018 22:54:10 +0000 (14:54 -0800)]
RISC-V: Fix unnamed arg alignment in registers.
For riscv64-linux target, second half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
Unnamed arguments with 2*XLEN alignment are passed in aligned register pairs.
gdb/
* riscv-tdep.c (struct riscv_arg_info): New field is_unnamed.
(riscv_call_arg_scalar_int): If unnamed arg with twice xlen alignment,
then increment next_regnum if odd.
(riscv_arg_location): New arg is_unnamed. Set ainfo->is_unnamed.
(riscv_push_dummy_call): New local ftype. Call check_typedef to set
function type. Pass new arg to riscv_arg_location based on function
type.
(riscv_return_value): Pass new arg to riscv_arg_location.
Jim Wilson [Wed, 14 Nov 2018 22:52:34 +0000 (14:52 -0800)]
RISC-V: Handle vector type alignment.
For riscv64-linux target, first half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
GCC gives vectors natural aligment based on total size, not element size,
bounded by the maximum supported type alignment.
gdb/
* riscv-tdep.c (BIGGEST_ALIGNMENT): New.
(riscv_type_alignment) <TYPE_CODE_ARRAY>: If TYPE_VECTOR, return min
of TYPE_LENGTH and BIGGEST_ALIGNMENT.
Jim Wilson [Wed, 14 Nov 2018 22:51:40 +0000 (14:51 -0800)]
RISC-V: Give stack slots same align as XLEN.
For riscv64-linux target, fixes
FAIL: gdb.base/gnu_vector.exp: call add_many_charvecs
Ensure that stack slots are always the same alignment as XLEN by rounding
up arg align to xlen.
gdb/
* riscv-tdep.c (riscv_call_arg_scalar_int): Use std::min when
setting len. New local align, set to max of arg align and xlen,
and pass to first riscv_assign_stack_location call.
GDB Administrator [Wed, 14 Nov 2018 00:01:05 +0000 (00:01 +0000)]
Automatic date update in version.in
Jim Wilson [Tue, 13 Nov 2018 23:50:38 +0000 (15:50 -0800)]
RISC-V: Improve linker error for FP mismatch.
bfd/
* elfnn-riscv.c (riscv_float_abi_string): New.
(_bfd_riscv_elf_merge_private_bfd_data): Use it for error message.
Francois H. Theron [Tue, 13 Nov 2018 10:33:16 +0000 (12:33 +0200)]
opcodes/nfp: Fix disassembly of crc[] with swapped operands.
The decoding of the CRC operation in alu instructions was using bits
from the instruction word directly, instead of srcA which would be
different if the swap bit was set.
Signed-off-by: Francois H. Theron <francois.theron@netronome.com>
Thomas Preud'homme [Tue, 13 Nov 2018 12:19:28 +0000 (12:19 +0000)]
[ARM] Improve indentation of ARM architecture declarations
This commit cleans up indentation of ARM architecture declaration,
namely entries of arm_archs and definition of macros ARM_EXT_*,
ARM_AEXT_*, ARM_AEXT2_*, FPU_EXT_*, FPU_ARCH_* and ARM_ARCH_*. It also
gets rid of unused ARM_ARCH_V6M-ONLY and merge AEM_AEXT_V6M_ONLY in
ARM_AEXT_V6M now sole user.
gas/
2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (arm_archs): Reindent.
include/
2018-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
(ARM_ARCH_V6M_ONLY): Remove.
(ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
GDB Administrator [Tue, 13 Nov 2018 00:00:40 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Mon, 12 Nov 2018 17:29:49 +0000 (09:29 -0800)]
i386: Accept both .plt.got and .plt.sec sections
Glibc commit:
commit
a15529fda8d132621328c3fe32997a3d9c55aef4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Mon May 14 09:23:55 2018 -0700
i386: Replace PREINIT_FUNCTION@PLT with *%eax in call
Since we have loaded address of PREINIT_FUNCTION into %eax, we can
avoid extra branch to PLT slot.
changed __gmon_start__ relocations in crt1.o from
00000015 0000092b R_386_GOT32X
00000000 __gmon_start__
0000001e 00000904 R_386_PLT32
00000000 __gmon_start__
to
00000015 00000a2b R_386_GOT32X
00000000 __gmon_start__
As the result, .plt.sec section may be generated instead of .plt.got
section, depending on __gmon_start__ relocations.
* testsuite/ld-i386/plt-main-ibt.dd: Accept both .plt.got and
.plt.sec sections.
Simon Marchi [Mon, 12 Nov 2018 15:38:44 +0000 (10:38 -0500)]
Add completer for skip numbers
Add completer to various commands that accept skip numbers:
- skip enable
- skip disable
- skip delete
- info skip
These commands also accept ranges, the completer works for that but is
not very smart. It will suggest invalid ranges, for example when doing
"2-<TAB>" it will suggest "1", which would not result in a valid range.
Also, it will keep suggesting when doing "1-2-<TAB>", even though it's
an invalid syntax.
A future idea would be to make a re-usable and well-tested completer for
numbers and ranges. I think it could at least be re-used for breakpoint
and thread numbers (for example with the "enable breakpoints" command).
gdb/ChangeLog:
* skip.c (complete_skip_number): New function.
(_initialize_step_skip): Add completers to some skip commands.
gdb/testsuite/ChangeLog:
* gdb.base/skip.exp: Add standard_testfile. Add "skip delete"
completer tests.
Nick Clifton [Mon, 12 Nov 2018 15:12:15 +0000 (15:12 +0000)]
Update documentation describing how the linker chooses a start address.
PR 10865
* ld.texi (Entry Point): Make it clear that the text refers to
PE-based systems rather than just a PE system.
Sudakshina Das [Mon, 12 Nov 2018 13:29:38 +0000 (13:29 +0000)]
[BINUTILS, AARCH64, 8/8] Add data cache instructions for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the data cache instructions that are part of this
extension:
- DC IGVAC, Xt
- DC IGSW, Xt
- DC CGSW, Xt
- DC CIGSW, Xt
- DC CGVAC, Xt
- DC CGVAP, Xt
- DC CGVADP, Xt
- DC CIGVAC, Xt
- DC GVA, Xt
- DC IGDVAC, Xt
- DC IGDSW, Xt
- DC CGDSW, Xt
- DC CIGDSW, Xt
- DC CGDVAC, Xt
- DC CGDVAP, Xt
- DC CGDVADP, Xt
- DC CIGDVAC, Xt
- DC GZVA, Xt
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entries for
IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test IGVAC, IGSW,
CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
CIGDVAC and GZVA with DC.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 13:26:01 +0000 (13:26 +0000)]
[BINUTILS, AARCH64, 7/8] Add system registers for Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds all the system registers that are part of this
extension and are accessible via the MRS/MSR instructions:
- TCO
- TFSRE0_SL1
- TFSR_EL1
- TFSR_EL2
- TFSR_EL3
- TFSR_EL12
- RGSR_EL1
- GCR_EL1
TCO is also accessible with the MSR(immediate) instruction.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
RGSR_EL1 and GCR_EL1.
(aarch64_sys_reg_supported_p): New check for above.
(aarch64_pstatefields): New entry for TCO.
(aarch64_pstatefield_supported_p): New check for above.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test TCO, TFSRE0_SL1,
TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12, RGSR_EL1 and
GCR_EL1 MSR and MRS.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 13:19:12 +0000 (13:19 +0000)]
[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Bulk Allocation Tag instructions from
MTE. These are the following instructions added in this patch:
- LDGV <Xt>, [<Xn|SP>]!
- STGV <Xt>, [<Xn|SP>]!
This needed a new kind of operand for the new addressing [<Xn|SP>]!
since this has no offset and only takes a pre-indexed version.
Hence AARCH64_OPND_ADDR_SIMPLE_2 and ldtdgv_indexed are introduced.
(AARCH64_OPND_ADDR_SIMPLE fulfilled the no offset criteria but does
not allow writeback). We also needed new encoding and decoding
functions to be able to do the same.
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
(aarch64_insn_class): Add ldstgv_indexed.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_addr_simple_2): New.
* aarch64-asm.h (ins_addr_simple_2): Declare the above.
* aarch64-dis.c (aarch64_ext_addr_simple_2): New.
* aarch64-dis.h (ext_addr_simple_2): Declare the above.
* aarch64-opc.c (operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
(aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
* aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
(AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMPLE_2 and allow [base]! for it.
(warn_unpredictable_ldst): Exempt ldstgv_indexed for ldgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldgv and stgv.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 13:14:00 +0000 (13:14 +0000)]
[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag Getting instruction from Memory Tagging
Extension.
- LDG <Xt>, [<Xn|SP>, #<simm>]
where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range of -4096 and 4080, defaulting to 0.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (QL_LDG): New.
(aarch64_opcode_table): Add ldg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 13:09:55 +0000 (13:09 +0000)]
[BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
and AARCH64_OPND_ADDR_SIMM13.
(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
for AARCH64_OPND_QLF_imm_tag.
(operand_general_constraint_met_p): Add case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
(aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
for both offset and pre/post indexed versions.
(AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
(fix_insn): Likewise.
(warn_unpredictable_ldst): Exempt STGP.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg, st2g,
stzg, stz2g and stgp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 12:58:26 +0000 (12:58 +0000)]
[BINUTILS, AARCH64, 3/8] Add Pointer Arithmetic instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Pointer Arithmetic instructions from
MTE. These are the following instructions added in this patch:
- SUBP <Xd>, <Xn|SP>, <Xm|SP>
- SUBPS <Xd>, <Xn|SP>, <Xm|SP>
- CMPP <Xn|SP>, <Xm|SP>
where CMPP is an alias to SUBPS XZR, <Xn|SP>, <Xm|SP>
where
<Xd> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<Xm|SP> : Is the 64-bit second source GPR or Stack pointer.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for subp,
subps and cmpp.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 12:52:55 +0000 (12:52 +0000)]
[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch add support to the Tag generation instructions from
MTE. These are the following instructions added in this patch:
- IRG <Xd|SP>, <Xn|SP>{, Xm}
- ADDG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- SUBG <Xd|SP>, <Xn|SP>, #<uimm1>. #<uimm2>
- GMI <Xd>, <Xn|SP>, <Xm>
where
<Xd|SP> : Is the 64-bit destination GPR or Stack pointer.
<Xn|SP> : Is the 64-bit source GPR or Stack pointer.
<uimm6> : Is the unsigned immediate, a multiple of 16
in the range 0 to 1008.
<uimm4> : Is the unsigned immediate, in the range 0 to 15.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (aarch64_opnd): Add
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
(OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
* aarch64-opc.c (fields): Add entry for imm4_3.
(operand_general_constraint_met_p): Add cases for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
(aarch64_print_operand): Likewise.
* aarch64-tbl.h (QL_ADDG): New.
(aarch64_opcode_table): Add addg, subg, irg and gmi.
(AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
* aarch64-asm.c (aarch64_ins_imm): Add case for
operand_need_shift_by_four.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add switch case for
AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: New.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.d: Likewise.
Sudakshina Das [Mon, 12 Nov 2018 12:45:30 +0000 (12:45 +0000)]
[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A
This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.
*** include/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
*** opcodes/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
*** gas/ChangeLog ***
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
Nick Clifton [Mon, 12 Nov 2018 11:24:18 +0000 (11:24 +0000)]
Updated Spanish translation for the ld subdirectory.
ld * po/es.po: Updated Spanish translation.
GDB Administrator [Mon, 12 Nov 2018 00:00:26 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Sun, 11 Nov 2018 00:01:25 +0000 (00:01 +0000)]
Automatic date update in version.in
GDB Administrator [Sat, 10 Nov 2018 00:00:36 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Tue, 24 Jul 2018 01:47:39 +0000 (19:47 -0600)]
Remove a VEC from remote.c
This removes the VEC from remote_g_packet_data, replacing it with a
std::vector. This is a bit odd in that this object is never
destroyed, and is obstack-allocated. I believe a gdbarch is never
destroyed, so this seemed ok.
Tested by the buildbot.
gdb/ChangeLog
2018-11-09 Tom Tromey <tom@tromey.com>
* remote.c (remote_g_packet_guess_s): Remove typedef and DEF_VEC.
(struct remote_g_packet_data): Derive from allocate_on_obstack.
<guesses>: Now a std::vector.
(remote_g_packet_data_init, register_remote_g_packet_guess):
Update.
(remote_read_description_p): Update. Return bool.
(remote_target::read_description): Update.
(struct remote_g_packet_guess): Add constructor.
Tom Tromey [Sat, 27 Oct 2018 18:23:44 +0000 (12:23 -0600)]
Return scoped_fd from open_source_file and find_and_open_source
This changes open_source_file and find_and_open_source to return
scoped_fd, then updates the callers as appropriate, including using
scoped_fd::to_file.
Tested by the buildbot.
gdb/ChangeLog
2018-11-09 Tom Tromey <tom@tromey.com>
* common/scoped_fd.h (class scoped_fd): Add move constructor and
move assignment operator.
* psymtab.c (psymtab_to_fullname): Update.
* source.h (open_source_file): Return scoped_fd.
(find_and_open_source): Likewise.
* source.c (open_source_file): Return scoped_fd.
(get_filename_and_charpos): Update.
(print_source_lines_base): Update. Use scoped_fd::to_file.
(forward_search_command): Likewise.
(reverse_search_command): Likewise.
(find_and_open_source): Return scoped_fd.
* tui/tui-source.c (tui_set_source_content): Update. Use
gdb_file_up.
John Baldwin [Fri, 9 Nov 2018 19:44:20 +0000 (11:44 -0800)]
Fix unsigned overflow in minsyms reader.
Use a ssize_t helper variable for the number of bytes to shrink the
msymbols obstack rather than relying on unsigned overflow to shrink
the size of the obstack.
gdb/ChangeLog:
* minsyms.c (minimal_symbol_reader::install): Fix unsigned
overflow.
Pedro Franco de Carvalho [Fri, 9 Nov 2018 18:09:03 +0000 (16:09 -0200)]
[PowerPC] Document requirements for VSX feature
As suggested in
https://sourceware.org/ml/gdb-patches/2018-10/msg00510.html, this
patch changes the documentation for the VSX tdesc feature to make it
clear that the altivec and FPU features are requirements.
gdb/doc/ChangeLog:
2018-11-09 Pedro Franco de Carvalho <pedromfc@linux.ibm.com>
* gdb.texinfo (PowerPC Features): Document the altivec and fpu
requirements for the org.gnu.gdb.power.vsx feature.
Hafiz Abid Qadeer [Fri, 9 Nov 2018 16:03:11 +0000 (16:03 +0000)]
Fix a typo in iconv.m4.
config/
2018-11-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
* iconv.m4 (AM_ICONV_LINK): Don't overwrite CPPFLAGS.
Append $INCICONV to it.
gdb/
2018-11-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
* configure: Regenerate.
binutils/
2018-11-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
* configure: Regenerate.
intl/
2018-11-09 Hafiz Abid Qadeer <abidh@codesourcery.com>
* configure: Regenerate.
Bernhard M. Wiedemann [Fri, 9 Nov 2018 16:06:48 +0000 (16:06 +0000)]
Correct comment concerning PE timestamp insertion.
* peXXigen.c (_bfd_XXi_only_swap_filehdr_out): Correct comment
concerning timestamp insertion.
Cupertino Miranda [Fri, 9 Nov 2018 15:49:29 +0000 (15:49 +0000)]
Fixed warning from previous patch. Added Changelog.
Cupertino Miranda [Thu, 4 Oct 2018 09:17:03 +0000 (10:17 +0100)]
[ARC] More fixes for TLS.
Added warning for static TLS reloc.
Fixed issue related to TLS and partial static linking of libraries:
This issue was detected when throwing exceptions in C++ while linking with
-static-libstdc++.
TLS relocation from the libstdc++ wasn't being patched as local now that it was
static linked with the executable.
Fix for TLS with static and pie. Problem introduced by earlier patch:
Fixes the following glibc tests:
- elf/tst-tls1-static
bfd/
xxxx-xx-xx Cupertino Miranda <cmiranda@synopsys.com>
* arc-got.h (arc_got_entry_type_for_reloc): Changed to
correct static TLS relocs.
* elf32-arc.c (elf_arc_check_relocs): Introduced warning to
TLS relocs which require -fPIC.
(arc_create_forced_local_got_entries_for_tls): Created.
Traverses list of GOT entries to be resolved statically
when needed.
(elf_arc_finish_dynamic_sections): Changed. Calls
arc_create_forced_local_got_entries_for_tls for each known
possibly GOT symbol.
Nick Clifton [Fri, 9 Nov 2018 14:18:02 +0000 (14:18 +0000)]
Updated French translation for the ld subdirectory.
* po/fr.po: Updated French translation.
rhn [Fri, 9 Nov 2018 14:09:44 +0000 (14:09 +0000)]
Stop corruption of ihex output shen addresses are sign extended.
PR 23699
* ihex.c (ihex_write_object_contents): Check for sign extended
addresses that cannot be supported in the ihex format.
Nick Clifton [Fri, 9 Nov 2018 12:51:46 +0000 (12:51 +0000)]
oops - add missing piece of previous delta
Nick Clifton [Fri, 9 Nov 2018 12:48:23 +0000 (12:48 +0000)]
Enhance the strings program so that it can display multibyte strings.
* strings.c (print_strings): Check for multibyte encodings.
* binutils-all/strings-1.bin: New file. Test binary for string decoding.
* testsuite/binutils-all/strings.exp: New file. Test the strings program.
* testsuite/config/default.exp (STRINGS): Define if not provided
by the environment.
(STRINGSFLAGS): Likewise.
Claudiu Zissulescu [Fri, 9 Nov 2018 11:24:29 +0000 (13:24 +0200)]
[ARC] Update ld tests.
ld/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/ld-arc/tls_gd-01.d: Update test.
* testsuite/ld-arc/arclinux-nps.d: Add cpu option.
Claudiu Zissulescu [Fri, 9 Nov 2018 11:14:00 +0000 (13:14 +0200)]
[ARC] Fix local got entry list.
Fix a memory leak appearing when the local got entry list was constructed.
bfd/
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com>
* arc-got.h (arc_get_local_got_ents): Revamp it; use
elf_local_got_ents to store the local got list.
(get_got_entry_list_for_symbo): Restructure it.
* elf32-arc.c (elf_arc_relocate_section): Correct the call to
get_got_entry_list_for_symbol.
Marc [Fri, 9 Nov 2018 11:13:50 +0000 (11:13 +0000)]
Allow for compilers that do not produce aligned .rdat sections in PE format files.
PR 23872
* scripttempl/pep.sc (pe.sc): Ensure rdata_runtime_pseudo_relocs
are aligned.
* scripttempl/pep.sc (pep.sc): Likewise.
Tom de Vries [Fri, 9 Nov 2018 10:54:04 +0000 (11:54 +0100)]
[gdb/symtab] Fix language of duplicate static minimal symbol
Consider a test-case with source files msym.c:
...
static int foo (void) { return 1; }
...
and msym_main.c:
...
static int foo (void) { return 2; }
int main (void) { return 0; }
..
compiled as c++ with minimal symbols:
...
$ g++ msym_main.c msym.c
...
With objdump -x we find the two foo symbols prefixed with their corresponding
files in the symbol table:
...
0000000000000000 l df *ABS*
0000000000000000 msym_main.c
00000000004004c7 l F .text
000000000000000b _ZL3foov
0000000000000000 l df *ABS*
0000000000000000 msym.c
00000000004004dd l F .text
000000000000000b _ZL3foov
...
However, when we use gdb to print info on foo, both foos are listed, but we
get one symbol mangled and one symbol demangled:
...
$ gdb ./a.out -batch -ex "info func foo"
All functions matching regular expression "foo":
Non-debugging symbols:
0x00000000004004c7 foo()
0x00000000004004dd _ZL3foov
...
During minimal symbol reading symbol_set_names is called for each symbol.
First, it's called with foo from msym.c, an entry is created in
per_bfd->demangled_names_hash and symbol_find_demangled_name is called, which
has the side effect of setting the language of the symbol to language_cplus.
Then, it's called with foo from msym_main.c. Since
per_bfd->demangled_names_hash already has an entry for that name,
symbol_find_demangled_name is not called, and the language of the symbol
remains language_auto.
Fix this by doing the symbol_find_demangled_name call unconditionally.
Build and reg-tested on x86_64-linux.
gdb/ChangeLog:
2018-11-09 Tom de Vries <tdevries@suse.de>
* symtab.c (symbol_set_names): Call symbol_find_demangled_name
unconditionally, to set the language of the symbol. Manage freeing
returned pointer using gdb::unique_xmalloc_ptr.
gdb/testsuite/ChangeLog:
2018-11-09 Tom de Vries <tdevries@suse.de>
* gdb.base/msym-lang.c: New test.
* gdb.base/msym-lang.exp: New file.
* gdb.base/msym-lang-main.c: New test.
Andreas Krebbel [Fri, 9 Nov 2018 10:00:47 +0000 (11:00 +0100)]
S/390: Fix optional operand handling after memory addresses
Instructions having an optional argument following a memory address
operand were not handled correctly if the optional argument was not
specified.
gas/ChangeLog:
2018-11-09 Andreas Krebbel <krebbel@linux.ibm.com>
* config/tc-s390.c (skip_optargs_p): New function.
(md_gather_operands): Use skip_optargs_p.
* testsuite/gas/s390/s390.exp: Run the new test.
* testsuite/gas/s390/zarch-optargs.d: New test.
* testsuite/gas/s390/zarch-optargs.s: New test.
Alan Modra [Wed, 7 Nov 2018 05:42:36 +0000 (16:12 +1030)]
PowerPC, don't use bfd reloc howto in md_assemble
We support source like the following
.data
.quad x-.
.space 8
x:
where at the time the .quad line is assembled, x is unknown so a fixup
is emitted for later evaluation. This is supported for data even when
the target may not have relocations for the expression, for example,
32-bit powerpc targets lack a 64-bit reloc. As long as the fixup
resolves at assembly time, gas is happy.
The idea of this patch is to support fixups that resolve at assembly
time for instructions too, even when the target might lack the
necessary relocations (and thus no howto).
* config/tc-ppc.c (fixup_size): New function.
(md_assemble): Use it to derive size and pcrel directly
from fixup reloc type.
GDB Administrator [Fri, 9 Nov 2018 00:00:25 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Wed, 7 Nov 2018 03:12:36 +0000 (20:12 -0700)]
Capitalize "<TAB>" in require_record_target error
This changes require_record_target to say "<TAB>" rather than "<tab>".
I think capitalizing here is a bit more GNU-ish, based on Emacs usage
and one other case in gdb.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
* record.c (require_record_target): Upper-case "<TAB>".
Tom Tromey [Wed, 7 Nov 2018 03:09:20 +0000 (20:09 -0700)]
Fix output indentation for "info pretty-printers"
I noticed that "info pretty-printers" will indent the "objfile" line
like:
(top-gdb) info pretty-printer
global pretty-printers:
builtin
mpx_bound128
objfile /home/tromey/gdb/build/gdb/gdb pretty-printers:
type_lookup_function
I think the "objfile" line should be "out-dented", following the same
style as the "global" and "progspace" (not shown) lines.
This patch implements this.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
* python/lib/gdb/command/pretty_printers.py
(InfoPrettyPrinter.invoke): Don't indent "objfile" heading.
Tom Tromey [Fri, 5 Oct 2018 20:54:35 +0000 (14:54 -0600)]
Avoid crash when calling warning too early
I noticed that if you pass the name of an existing file (not a
directory) as the argument to --data-directory, gdb will crash:
$ ./gdb -nx --data-directory ./gdb
../../binutils-gdb/gdb/target.c:590:56: runtime error: member call on null pointer of type 'struct target_ops'
This was later reported as PR gdb/23838.
This happens because warning ends up calling
target_supports_terminal_ours, which calls current_top_target, which
returns nullptr this early.
This fixes the problem by handling this case specially in
target_supports_terminal_ours. I also changed
target_supports_terminal_ours to return bool.
gdb/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
PR gdb/23555:
PR gdb/23838:
* target.h (target_supports_terminal_ours): Return bool.
* target.c (target_supports_terminal_ours): Handle case where
current_top_target returns nullptr. Return bool.
gdb/testsuite/ChangeLog
2018-11-08 Tom Tromey <tom@tromey.com>
PR gdb/23555:
PR gdb/23838:
* gdb.base/warning.exp: New file.
Joel Brobecker [Thu, 8 Nov 2018 15:27:31 +0000 (10:27 -0500)]
(AArch64) wrong value returned by "finish" for HFA
Consider the gdb.ada/array_return.exp testcase, and in particular,
consider the following code...
type Small_Float_Vector is array (1 .. 2) of Float;
function Create_Small_Float_Vector return Small_Float_Vector is
begin
return (others => 4.25);
end Create_Small_Float_Vector;
... which declares a type which is an array with 2 floats in it
(floats are 4 bytes on AArch64), trying to get GDB to print
the return value from that function does not work:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 0.0)
^^^
|||
We expected the value shown to be:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 4.25)
Because the return type is an HFA, it is returned via the first two
SIMD registers. However, what happens is that the current implementation
fails to realize that this is an HFA, and therefore fetches the return
value from the wrong location. And the reason why it fails to realize
this is because it thinks that our array has 8 elements (HFAs have
a maximum of 4). Looking at aapcs_is_vfp_call_or_return_candidate_1,
where this is determined, we can easily see why (looks like a thinko):
| case TYPE_CODE_ARRAY:
| [...]
| struct type *target_type = TYPE_TARGET_TYPE (type);
| int count = aapcs_is_vfp_call_or_return_candidate_1
| (target_type, fundamental_type);
|
| if (count == -1)
| return count;
|
!! -> | count *= TYPE_LENGTH (type);
| return count;
Here, we first determine the count for one element of our array,
and so we should then be multiplying that count by the number
of elements in our array (2 in our case). But instead, we multiply it
by the total size (8). As a result, we do not classify the return
type as an HFA, and thus pick the wrong location for fetching
the return value.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1):
return the correct count for potential HFAs.
Tested on aarch64-linux, fixes:
array_return.exp: value printed by finish of Create_Small_Float_Vector
Jan Beulich [Thu, 8 Nov 2018 11:12:05 +0000 (12:12 +0100)]
x86-64: fix ZMM register state tracking
The three AVX512 state components are entirely independent - one being
in its "init state" has no implication whatsoever on either of the other
two. Fully separate X86_XSTATE_ZMM_H and X86_XSTATE_ZMM handling, to
prevent upper halves of the upper 16 ZMM registers to display as if they
were zero (when they aren't) after e.g. VZEROALL/VZEROUPPER.
Andrew Burgess [Mon, 5 Nov 2018 22:00:31 +0000 (22:00 +0000)]
gdb/riscv: Update test to support targets without FP hardware
Update gdb.arch/riscv-reg-aliases.exp test to support targets without
floating point registers.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-reg-aliases.exp: Handle targets without floating
point hardware.
Andrew Burgess [Mon, 29 Oct 2018 15:14:03 +0000 (15:14 +0000)]
gdb/riscv: Handle errors while setting the frame id
When we connect to a remote target one of the first things GDB does is
establish a frame id. If an error is thrown while building this frame
id then GDB will disconnect from the target.
This can mean that, if the user is attempting to connect to a target
that doesn't yet have a program loaded, or the program the user is
going to load onto the target doesn't match what is already loaded, or
the target is just in some undefined state, then the very first
request for a frame id can fail (for example, by trying to load from
an invalid memory address), and GDB will disconnect. It is then
impossible for the user to connect to the target and load a new
program at all.
An example of such a session might look like this:
Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases...
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
Cannot access memory at address 0x0
(gdb) load
You can't do that when your target is `exec'
(gdb) info frame
/path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n)
The solution is to handle errors in riscv_frame_this_id, and leave the
this_id variable with its default value, which is the predefined
'outermost' frame.
With this fix in place, connecting to the same target now looks like
this:
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
(gdb) info frame
Stack level 0, frame at 0x0:
pc = 0x100; saved pc = <not saved>
Outermost frame: outermost
Arglist at unknown address.
Locals at unknown address, Previous frame's sp in sp
gdb/ChangeLog:
* riscv-tdep.c (riscv_insn::decode): Update header comment.
(riscv_frame_this_id): Catch errors thrown while building the
frame cache, leave the frame id as the default, which is the outer
frame id.
Alan Modra [Fri, 2 Nov 2018 10:57:02 +0000 (21:27 +1030)]
Make gold testsuite work with CC and CXX specifying -B
The patch allows the gold testsuite to pass when using something like
the following configure line, which works for the rest of the binutils
testsuite. At least, it does if you don't configure your gcc with any
of the options that force a particular path to as or ld.
gccdir="/home/alan/build/gcc/prev-"
gccsrc="/home/alan/src/gcc.git"
gcctarg="x86_64-linux"
CC="${gccdir}gcc/xgcc -B${gccdir}gcc/" \
CXX="${gccdir}gcc/xg++ -B${gccdir}gcc/ -I${gccdir}$gcctarg/libstdc++-v3/include -I${gccdir}$gcctarg/libstdc++-v3/include/$gcctarg -I${gccsrc}/libstdc++-v3/libsupc++ -L${gccdir}$gcctarg/libstdc++-v3/src/.libs/" \
~/src/binutils-gdb/configure ...
gold's -Bgcctestdir/ option must come before the -B supplied by $CC
or $CXX, in order to pick up the linker we want to test. Also when
using a not-yet-installed gcc, it is necessary to provide a collect-ld
in gcctestdir/ as otherwise a collect-ld script in -B${gccdir}gcc/
will be used and the wrong linker tested.
Besides this, the patch fixes some bugs: The $COMPILE -D_FORTIFY_SOURCE
edit was wrong (but worked for usual values), and the $CXXLINK_S edit
unnecessarily but harmlessly used extra backslash quoting. See
posix shell documentation regarding quoting, or
www.gnu.org/software/bash/manual/bashref.html#Command-Substitution
Also, -Bgcctestdir/ in one place makes it less likely a new test will
be added that accidentally lacks the option.
* Makefile.am (gcctestdir1/ld): Use $@ and absolute paths.
(gcctestdir1/collect-ld): New.
(ld1_DEPENDENCIES): Add gcctestdir1/collect-ld.
(ld1_LDFLAGS): Remove -Bgcctestdir1/.
(editcc1, ld1_LINK): Define.
(gcctestdir2/ld, gcctestdir2/collect-ld, ld2_DEPENDENCIES),
(ld2_LDFLAGS, editcc2, ld2_LINK),
(ld1_r_DEPENDENCIES, ld1_r_LDFLAGS, ld1_r_LINK),
(gcctestdir2-r/ld, gcctestdir2-r/collect-ld, ld2_r_DEPENDENCIES),
(ld2_r_LDFLAGS, editcc2r, ld2_r_LINK),
(gcctestdir3/ld, gcctestdir3/collect-ld, ld3_DEPENDENCIES),
(ld3_LDFLAGS, editcc3, ld3_LINK),
(gcctestdir4/ld, gcctestdir4/collect-ld, ld4_DEPENDENCIES),
(ld4_LDFLAGS, editcc4, ld4_LINK): Similarly.
* Makefile.in: Regenerate.
* testsuite/Makefile.am (editcc): Define sed command to put
our -B option first. Remove other occurrences of -Bgcctestdir/
throughout file.
(editcc1): Define for -D_FORTIFY_SOURCE stripping.
(editcc2): Define for -static-libgcc/libstdc++ stripping.
(LINK1, CXXLINK1): Don't use CCLD or CXXLD.
(CCLD, CXXLD, COMPILE, LINK, CXXCOMPILE, CXXLINK, CXXLINK_S): Define
using editcc macros.
(gcctestdir/collect-ld): New rule, add as a dependency of..
(gcctestdir/ld): ..this. Use $@ and abs_top_buildir.
(gcctestdir/as): Use $@.
* testsuite/Makefile.in: Regenerate.
* testsuite/incremental_test.sh (actual): Match collect-ld too.
GDB Administrator [Thu, 8 Nov 2018 00:00:32 +0000 (00:00 +0000)]
Automatic date update in version.in
Joel Brobecker [Wed, 7 Nov 2018 21:04:13 +0000 (16:04 -0500)]
(Ada/tasking) fix array or string index out of range warning
A recent change in the compiler highlighted a small weakness in
the function reading the contents of the Ada Task Control Block
(ATCB -- the data that allows us to inspect Ada tasks). As a result,
anytime we read it, we started getting some warnings. For instance,
using the gdb.ada/tasks.exp testcase...
$ gnatmake -g foo.adb
$ gdb foo
(gdb) b foo.adb:60
Breakpoint 1 at 0x403e07: file foo.adb, line 60.
(gdb) run
[...]
Thread 1 "foo" hit Breakpoint 1, foo () at foo.adb:60
60 for J in Task_List'Range loop -- STOP_HERE
... we can see that the "info tasks" command produces some warnings,
followed by the correct output.
(gdb) info tasks
!! -> warning: array or string index out of range
!! -> warning: array or string index out of range
!! -> warning: array or string index out of range
!! -> warning: array or string index out of range
ID TID P-ID Pri State Name
* 1 654050 48 Runnable main_task
2 654ef0 1 48 Accept or Select Term task_list(1)
3 658680 1 48 Accept or Select Term task_list(2)
4 65be10 1 48 Accept or Select Term task_list(3)
The problem comes from the fact that read_atcb, the function responsible
for loading the contents of the ATCB, blindly tries to read some data
which is only relevant when a task is waiting for another task on
an entry call. A comment in that code's section gives a hint as to
how the information is meant to be decoded:
/* Let My_ATCB be the Ada task control block of a task calling the
entry of another task; then the Task_Id of the called task is
in My_ATCB.Entry_Calls (My_ATCB.ATC_Nesting_Level).Called_Task. */
What the comment shows is that, to get the Id of the task being called,
one has to go through the entry calls field, which is an array pointer.
Up to now, we were lucky that, for tasks that are _not_ waiting on an
entry call, its ATCB atc_nesting_level used to be set to 1, and so
we were able to silently read some irrelevant data. But a recent change
now causes this field to be zero instead, and this triggers the warning,
since we are now trying to read outside of the array's range (arrays
in Ada often start at index 1, as is the case here).
We avoid this issue by simply only reading that data when the data
is actually known to be relevant (state == Entry_Caller_Sleep).
This, in turn, allows us to simplify a bit the use of the task_info->state
field, where we no longer need to check task the task has a state equal
to Entry_Caller_Sleep before using this field. Indeed, with this new
approach, we now know that, unless task_info->state == Entry_Caller_Sleep,
the state is now guaranteed to be zero. In other words, we no longer set
task_info->called_task to some random value, forcing to check the task's
state first as a way to verify that the data is not random.
gdb/ChangeLog:
* ada-lang.c (read_atcb): Only set task_info->called_task if
task_info->state == Entry_Caller_Sleep.
(print_ada_task_info): Do not check task_info->state before
checking task_info->called_task.
(info_task): Likewise.
Joel Brobecker [Wed, 7 Nov 2018 21:03:38 +0000 (16:03 -0500)]
ada-tasks.c::read_atcb: start from a cleared ada_task_info result
The purpose of this patch is not to fix a bug per se, but rather
to robustify this function to make sure it never returns a struct
ada_task_info where some of the fields are left uninitialized.
Reading the current implementation, it attempts to methodically
set them all one by one: but it's not excluded that a future
change might miss something. A memset is cheap and make sure that
this function returns repeatable results.
This in turns allows us to remove some assignments which have become
redundant.
gdb/ChangeLog:
* ada-tasks.c (read_atcb): Clear task_info before computing
the value of each of its fields.
Masatake Yamato [Wed, 7 Nov 2018 18:07:36 +0000 (18:07 +0000)]
Enhance objdump's --disassemble switch so that it can now take an optional parameter, specifying the starting symbol for disassembly. Disassembly will continue from this symbol up to the next symbol.
* objdump.c (long_options): Have the --disassemble option take an
optional argument.
(usage): Add description for the `symbol' argument to the
--disassemble option.
(disasm_sym): New file private variable.
(struct objdump_disasm_info): New field `symbol'.
(disassemble_section): Introduce `do_print' local variable
to control whether objdump displays the result of disassembling
for a symbol or not.
(main): Set `symbol' file private variable if the option argument
for the --disassemble option is given.
* doc/binutils.texi (objdump): Add description for the option
argument.
* NEWS: Mention the new feature.
* testsuite/binutils-all/objdump.exp: Add tests of the -d and
--disassemble=<symbol> options.
* testsuite/binutils-all/bintest.s: Add more symbols and code.
* testsuite/binutils-all/readelf.s: Update expected output.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-mips: Likewise.
* testsuite/binutils-all/readelf.ss-tmips: Likewise.
Nick Clifton [Wed, 7 Nov 2018 16:09:27 +0000 (16:09 +0000)]
Add updated French and Portuguese translations.
gas * po/fr.po: Updated French translation.
bfd * po/fr.po: Updated French translation.
* po/pt.po: Updated Portuguese translation.
binutils* po/pt.po: Updated Portuguese translation.
Roman Bolshakov [Wed, 7 Nov 2018 15:20:22 +0000 (15:20 +0000)]
Add support for new load commands added by Apple to the MACH-O file format.
bfd * mach-o.h: Add new enums for BFD_MACH_O_PLATFORM_MACOS,
BFD_MACH_O_PLATFORM_IOS, BFD_MACH_O_PLATFORM_TVOS,
BFD_MACH_O_PLATFORM_WATCHOS, BFD_MACH_O_PLATFORM_BRIDGEOS,
BFD_MACH_O_TOOL_CLANG, BFD_MACH_O_TOOL_SWIFT, BFD_MACH_O_TOOL_LD.
(struct bfd_mach_o_note_command): New.
(struct bfd_mach_o_build_version_tool): New.
(struct bfd_mach_o_build_version_command): New.
(bfd_mach_o_read_version_min): Don't split version into
a few fields. Rename reserved to sdk.
* mach-o.c (bfd_mach_o_read_version_min): Don't split version into a
few fields. Rename reserved to sdk.
(bfd_mach_o_read_command): Handle LC_VERSION_MIN_TVOS, LC_NOTE,
LC_BUILD_VERSION.
(bfd_mach_o_read_note): New.
(bfd_mach_o_read_build_version): New.
PR 23728
binutils* od-macho.c (printf_version): New.
(dump_load_command): Use it to print version. Print sdk version. Print
version info for watchOS and tvOS. Print LC_NOTE, LC_BUILD_VERSION.
(dump_buld_version): New.
(bfd_mach_o_platform_name): New
(bfd_mach_o_tool_name): New
* mach-o/external.h (mach_o_nversion_min_command_external): Rename
reserved to sdk.
(mach_o_note_command_external): New.
(mach_o_build_version_command_external): New.
* mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
(BFD_MACH_O_LC_NOTE): Define.
Andrew Burgess [Tue, 6 Nov 2018 19:55:21 +0000 (19:55 +0000)]
gdb: Guard against NULL dereference in dwarf2_init_integer_type
In this commit:
commit
eb77c9df9f6d2f7aa644a170280fe31ce080f887
Date: Thu Oct 18 14:04:27 2018 +0100
gdb: Handle ICC's unexpected void return type
A potential dereference of a NULL pointer was introduced if a
DW_TAG_base_type is missing a DW_AT_name attribute.
I have taken this opportunity to fix a slight confusion that existed
in the test also added in the above commit, the test had two C
variables, declared like this:
int var_a = 5;
void *var_ptr = &var_a;
However, the fake DWARF in the test script declared them like this:
void var_a = 5;
void *var_ptr = &var_a;
This wasn't a problem as the test never uses 'var_a' directly, this
only exists so 'var_ptr' can be initialised. However, it seemed worth
fixing.
I've also added a test for a DW_TAG_base_type with a missing
DW_AT_name, as clearly there's not test currently that covers this
(the original patch tested cleanly). I can confirm that the new test
causes GDB to crash before this patch, and passes with this patch.
gdb/ChangeLog:
* dwarf2read.c (dwarf2_init_integer_type): Check for name being
NULL before dereferencing it.
gdb/testsuite/ChangeLog:
* gdb.dwarf2/void-type.exp: Rename types, and make var_a an 'int'.
* gdb.dwarf2/missing-type-name.exp: New file.
Alan Modra [Wed, 7 Nov 2018 11:23:21 +0000 (21:53 +1030)]
Regen bfd/configure
* configure: Regenerate.
Yoshinori Sato [Wed, 7 Nov 2018 08:16:56 +0000 (17:16 +0900)]
rx: Add target rx-*-linux.
GDB Administrator [Wed, 7 Nov 2018 00:00:16 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom de Vries [Thu, 1 Nov 2018 08:21:18 +0000 (09:21 +0100)]
[gdb] Fix gdb crash when reading core file
Consider the test-case from this patch, compiled with O0.
The executable segfaults, and generates a core dump:
...
$ ./a.out
Segmentation fault (core dumped)
...
When loading the core file, limiting stack size to 4MB, gdb crashes:
...
$ ulimit -s 4096
$ gdb -batch ./a.out core.saved
[New LWP 19379]
Segmentation fault (core dumped)
...
The crash originates here in linux_vsyscall_range_raw, where we call alloca
with phdrs_size ==
4194112 (roughly 4MB):
...
phdrs = (Elf_Internal_Phdr *) alloca (phdrs_size);
...
While for this test-case gdb runs fine with the system default stack limit of
8MB, there are cases reported of 12MB phdrs_size where gdb also crashes with
the system default stack limit.
Fix this by using xmalloc instead of alloca, which prevents the crash provided
the stack limit is at least 112kb.
Build and reg-tested on x86_64-linux.
2018-11-06 Tom de Vries <tdevries@suse.de>
* linux-tdep.c (linux_vsyscall_range_raw): Use xmalloc to allocate
program headers.
* gdb.base/many-headers.c: New test.
* gdb.base/many-headers.exp: New file.
Jim Wilson [Tue, 6 Nov 2018 19:06:23 +0000 (11:06 -0800)]
RISC-V: Force variables to .data for code_elim.
RISC-V puts a global variable in .sdata by default, which causes the
add-symbol-file commands with -s .data to fail as there is no .data section.
This fixes 3 testsuite failures.
gdb/testsuite/
* gdb.base/code_elim.exp: For riscv, set additional_flags
to include -msmall-data-limit=0.
Max Filippov [Thu, 1 Nov 2018 00:10:33 +0000 (17:10 -0700)]
gdb: xtensa: use linux ABI code for uclinux
gdb/
2018-11-06 Max Filippov <jcmvbkbc@gmail.com>
* configure.tgt (xtensa*-*-linux*): Change to xtensa*-*-*linux*
so that it applies to uclinux as well.
Marius Muench [Tue, 6 Nov 2018 17:51:39 +0000 (10:51 -0700)]
ARM: Do not use FP reg when on AAPCS
GDB tries to dereference the frame pointer in arm_scan_prologue as a
last resort to create frame information.
However, the more recent AAPCS ABI does not make use of a frame pointer.
This patch checks whether the specified arm_abi is AAPCS before
dereferencing the "frame pointer". If so, just return as efforts to use
it for restoring frame information won't work.
gdb/ChangeLog
2018-11-06 Marius Muench <marius.muench@eurecom.fr>
* arm-tdep.c (arm_scan_prologue): Don't dereference FP reg
when on AAPCS.
John Baldwin [Tue, 6 Nov 2018 17:47:21 +0000 (09:47 -0800)]
Note that PT_GETREGS supplies SSTATUS for FreeBSD/riscv.
This permits reading the value of the SSTATUS CSR returned by ptrace()
for live FreeBSD/riscv processes.
* riscv-fbsd-nat.c (getregs_supplies): Return true for
RISCV_CSR_SSTATUS_REGNUM.
H.J. Lu [Tue, 6 Nov 2018 17:38:33 +0000 (09:38 -0800)]
elfedit: Add --enable-x86-feature/--disable-x86-feature
Add --enable-x86-feature and --disable-x86-feature options to elfedit
to set and clear the IBT and SHSTK bits in program property in ELF
executables and shared objects.
binutils/
* doc/binutils.texi: Document --enable-x86-feature and
--disable-x86-feature options for elfedit.
* elfedit.c: Include "config.h" and <sys/mman.h>.
(enable_x86_features): New.
(disable_x86_features): Likewise.
(update_gnu_property): Likewise.
(elf_x86_feature): Likewise.
(process_file): Call update_gnu_property on ET_EXEC or ET_DYN
file.
(command_line_switch): Add OPTION_ENABLE_X86_FEATURE and
OPTION_DISABLE_X86_FEATURE.
(options): Add--enable-x86-feature and --disable-x86-feature.
(usage): Likewise.
(main): Handle OPTION_ENABLE_X86_FEATURE and
OPTION_DISABLE_X86_FEATURE.
ld/
* testsuite/config/default.exp (ELFEDIT): New.
* testsuite/ld-elf/linux-x86.exp (elfedit_test): New proc.
Run elfedit tests.
* testsuite/ld-elf/x86-feature-1a.rd: New file.
* testsuite/ld-elf/x86-feature-1b.rd: Likewise.
* testsuite/ld-elf/x86-feature-1c.rd: Likewise.
* testsuite/ld-elf/x86-feature-1d.rd: Likewise.
* testsuite/ld-elf/x86-feature-1e.rd: Likewise.
Nick Clifton [Tue, 6 Nov 2018 17:09:40 +0000 (17:09 +0000)]
Add support for a couple of new Mach-O commands.
PR 23742
* mach-o.c (bfd_mach_o_read_command): Accept and ignore
BFD_MACH_O_LC_LINKER_OPTIONS and BFD_MACH_O_LC_BUILD_VERSION
commands.
* mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
Matthew Malcomson [Tue, 6 Nov 2018 17:09:34 +0000 (17:09 +0000)]
[arm] fix testsuite breakage on pe-coff
The PE target can insert NOP's for padding to 4 byte alignment.
This was causing a testcase failure, this commit fixes the testcase.
This commit also escapes some full-stops in the testcase regexp.
2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/arm/neon-cond-bad_t2.d: Fix testcase for PE
target.
Matthew Malcomson [Tue, 6 Nov 2018 14:52:11 +0000 (14:52 +0000)]
[arm] Check for neon and condition in vcvt.f16.f32
VCVT between f16 and f32 is an Advanced SIMD instruction.
Not all the VCVT alternatives need neon, hence the check for neon is in
the encode function.
The check on neon for VCVT.f16.f32 (and vice versa) is missing.
vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a -
testdir [15:59:10] $
Also, the handling of the condition code behaves differently to other
SIMD instructions -- no error message is produced when assembling an
instruction with a condition code suffix despite the arm encoding not
allowing a condition code. (n.b. the actual binary produced is
independent of the suffix).
The instruction should be treated similarly to VSUBL that has the same
caveat of "must be unconditional" describing the {<c>} symbol. vcvt
half-precision to single precision found in F6.1.58 in the ARM
Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in
the ARM Architecture Reference Manual issue C.a
2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition
codes to half-precision conversion.
* testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed.
* testsuite/gas/arm/neon-cond-bad.l: Likewise.
* testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT
block.
* testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon.
* testsuite/gas/arm/vfp-bad.s: Likewise.
Sudakshina Das [Tue, 6 Nov 2018 12:13:45 +0000 (12:13 +0000)]
[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.
This patch addresses the following
1) Adding ARMv8.5-A in select_arm_features.
2) Updating the feature macro so that the new ARM_EXT2_* features for
Armv8.5-A are moved to ARM_AEXT2_V8_5A.
*** opcodes/ChangeLog ***
2018-11-06 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (select_arm_features): Update bfd_mach_arm_8
with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
*** include/ChangeLog ***
2018-11-06 Sudakshina Das <sudi.das@arm.com>
* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
ARM_EXT2_SB to ...
(ARM_AEXT2_V8_5A): Here.
Alan Modra [Tue, 6 Nov 2018 05:34:40 +0000 (16:04 +1030)]
PowerPC instruction mask checks
The instruction mask bits should never overlap any of the operands,
nor should operand bits overlap, but some operands weren't checked.
This patch arranges to check the omitted operands, using a mask
returned by the operand->insert function. Some tweaking of various
insert functions is needed to support this: The error case must set
field bits.
Since I was looking at the insert functions, I tidied some dead code
and simplified some of the powerpc_operands entries.
gas/
* config/tc-ppc.c (insn_validate): Don't ignore mask in
PPC_OPSHIFT_INV case. Call the insert function to calculate
a mask.
opcodes/
* ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
(insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
(insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
(insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
Don't return zero on error, insert mask bits instead.
(insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
(insert_sh6, extract_sh6): Delete dead code.
(insert_sprbat, insert_sprg): Use unsigned comparisions.
(powerpc_operands <OIMM>): Set shift count rather than using
PPC_OPSHIFT_INV.
<SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
Alan Modra [Tue, 6 Nov 2018 02:53:20 +0000 (13:23 +1030)]
PowerPC instruction operand flag validation
This adds another check that might have saved me a little time
recently if it had been present.
* config/tc-ppc.c (insn_validate): Check that optional operands
are not followed by non-optional operands.
Jan Beulich [Tue, 6 Nov 2018 10:45:49 +0000 (11:45 +0100)]
x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode
For the flavor having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be VPBROADCASTQ.
Jan Beulich [Tue, 6 Nov 2018 10:45:11 +0000 (11:45 +0100)]
x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode
For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ, the GPR operand should
not name a non-existing 64-bit register, just like is already the case
for the AVX counterparts, and the Disp8 scaling factor should be 4
rather than 8.
Jan Beulich [Tue, 6 Nov 2018 10:44:31 +0000 (11:44 +0100)]
x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode
For the flavors having a GPR operand VEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ.
Jan Beulich [Tue, 6 Nov 2018 10:43:55 +0000 (11:43 +0100)]
x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter
that the SDM uses a nonstandard description of that fact.
PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode,
just like its AVX counterpart.
Jan Beulich [Tue, 6 Nov 2018 10:42:54 +0000 (11:42 +0100)]
x86: adjust {,E}VEX.W handling outside of 64-bit mode
Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of
64-bit mode. The respective templates should specify neither VexWIG nor
VexW0, but instead the setting of the bit should be determined from
- REX.W in 64-bit mode,
- the setting established through -mvexwig= / -mevexwig= otherwise.
This implies that the evex-wig2 testcase needs to go away, as being
wrong altogether.
A few test additions desirable here will only happen in later patches,
as the disassembler needs adjustments first.
Once again SSE2AVX templates are left alone, for it being unclear what
the behavior there should be.
Jan Beulich [Tue, 6 Nov 2018 10:42:08 +0000 (11:42 +0100)]
x86: fix various non-LIG templates
Quite a few templates were marked LIG while really the insns aren't.
Introduce descriptive shorthands once again, instead of continuing to
use the less legible original forms.
Jan Beulich [Tue, 6 Nov 2018 10:40:25 +0000 (11:40 +0100)]
x86: allow {store} to select alternative {,}PEXTRW encoding
The 0F C5 encoding is indeed a load type one (just that memory operands
are not permitted), while the 0F 3A 15 encoding is obviously a store.
Allow the pseudo prefixes to be used to select between them.
Also move (without any change) the secondary AVX512BW templates next to
the primary one.
Jan Beulich [Tue, 6 Nov 2018 10:39:42 +0000 (11:39 +0100)]
x86: add more VexWIG
Commits
6865c0435a ("x86: Support VEX/EVEX WIG encoding") and
6fa52824c3
("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly
enough in some cases despite testcases getting added (which then were
recorded with wrong expected output).
Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering
of that of neighboring templates.
For the moment SSE2AVX templates are left alone, as it isn't clear
whether they were intentionally left untouched by the original commits
(the descriptions don't say either way).
In this context I question the decision in commit
0375113302 ("x86: Add
-mvexwig=[0|1] option to assembler") to move the logic to determine the
value of the W bit ahead of the decision whether to use 2-byte VEX:
While I can see this as one possible interpretation of -mvexwig=, the
other alternative (setting the value of the bit only if it actually
exists in the encoding) looks as reasonable to me, and perhaps even more
in line with us generally trying to pick the shortest encoding.
Jan Beulich [Tue, 6 Nov 2018 10:38:47 +0000 (11:38 +0100)]
x86: XOP VPHADD* / VPHSUB* are VEX.W0
Also avoid introducing further uses of VexW=1, by introducing and using
VexW0 at this occasion. Move the marker past all #define-s.
GDB Administrator [Tue, 6 Nov 2018 00:00:35 +0000 (00:00 +0000)]
Automatic date update in version.in
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