Mike Frysinger [Thu, 24 Dec 2015 21:38:37 +0000 (16:38 -0500)]
sim: delete SIM_HAVE_MEM_SIZE
This define isn't used anywhere (doesn't seem to ever have been used by
versions committed), so delete the commented out code as it's dead.
Mike Frysinger [Thu, 24 Dec 2015 21:04:26 +0000 (16:04 -0500)]
sim: delete SIM_HAVE_SIMCACHE
This was used by the old run interface, but we punted that awhile ago,
so drop this define too.
GDB Administrator [Fri, 25 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Thomas Preud'homme [Thu, 24 Dec 2015 09:33:17 +0000 (17:33 +0800)]
Add support for linking ARMv8-M object files
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
* elf32-arm.c (using_thumb_only): Check that profile is 'M' and update
logic around Tag_CPU_arch values to return TRUE for ARMv8-M
architectures.
(tag_cpu_arch_combine): Define v8m_baseline and v8m_mainline and update
v4t_plus_v6_m and comb to deal with ARMv8-M Tag_CPU_arch merging logic.
(elf32_arm_merge_eabi_attributes): Add Tag_CPU_name values for
ARMv8-M.
bfd/testsuite/
* ld-arm/arm-elf.exp (armeabitests_common): Run new tests
"Thumb-Thumb farcall v8-M", "EABI attribute merging 8",
"EABI attribute merging 9" and "EABI attribute merging 10".
(Thumb-Thumb farcall v8-M): Renamed to ...
(Thumb-Thumb farcall v8-M Mainline): This.
(Thumb-Thumb farcall v8-M Baseline): New test.
* ld-arm/attr-merge-8a.s: New file.
* ld-arm/attr-merge-8b.s: Likewise.
* ld-arm/attr-merge-8.attr: Likewise.
* ld-arm/attr-merge-9a.s: Likewise.
* ld-arm/attr-merge-9b.s: Likewise.
* ld-arm/attr-merge-9.out: Likewise.
* ld-arm/attr-merge-10a.s: Likewise.
* ld-arm/attr-merge-10b.s: Likewise.
* ld-arm/attr-merge-10.attr: Likewise.
Thomas Preud'homme [Thu, 24 Dec 2015 09:26:08 +0000 (17:26 +0800)]
Add assembler support for ARMv8-M Baseline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards
to merging with ARMv8-M Baseline.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch
value.
gas/
* config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
shared between ARMv6T2 and ARMv8-M.
(move_or_literal_pool): Check mov.w/mvn and movw availability against
arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
arm_arch_t2.
(do_t_branch): Error out for wide conditional branch instructions if
targetting ARMv8-M Baseline.
(non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
in ARMv8-M Baseline.
(wide_insn_ok): New function.
(md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
adapt error message for unsupported wide instruction to ARMv8-M
Baseline.
(insns): Reorganize instructions shared by ARMv8-M Baseline and
ARMv6t2 architecture.
(arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
marvell-whitney cores.
(arm_archs): Define armv8-m.base architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
(aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well.
gas/testsuite/
* gas/arm/archv8m-base.d: New file.
* gas/arm/attr-march-armv8m.base.d: Likewise.
* gas/arm/armv8m.base-idiv.d: Likewise.
* gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_BASE): Declare.
include/opcode/
* arm.h (ARM_EXT2_V6T2_V8M): New extension bit.
(ARM_AEXT2_V8A): New architecture extension bitfield.
(ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_AEXT_V8M_BASE): New architecture extension bitfield.
(ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M.
(ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield.
(ARM_ARCH_V6KT2): Likewise.
(ARM_ARCH_V6ZT2): Likewise.
(ARM_ARCH_V6KZT2): Likewise.
(ARM_ARCH_V7): Likewise.
(ARM_ARCH_V7A): Likewise.
(ARM_ARCH_V7VE): Likewise.
(ARM_ARCH_V7R): Likewise.
(ARM_ARCH_V7M): Likewise.
(ARM_ARCH_V7EM): Likewise.
(ARM_ARCH_V8A): Likewise.
(ARM_ARCH_V8M_BASE): New architecture bitfield.
(ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M.
(ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension
bitfield and reindent.
(ARM_ARCH_V7A_MP_SEC): Likewise.
(ARM_ARCH_V7R_IDIV): Likewise.
(ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex,
ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by
ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2.
Thomas Preud'homme [Thu, 24 Dec 2015 09:16:19 +0000 (17:16 +0800)]
Add assembler support for ARMv8-M Mainline
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
bfd/
(tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in
comb array.
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
value.
(arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
value.
gas/
* config/tc-arm.c (arm_ext_m): Include ARMv8-M.
(arm_ext_v8m): New feature for ARMv8-M.
(arm_ext_atomics): New feature for ARMv8 atomics.
(do_tt): New encoding function for TT* instructions.
(insns): Add new entries for ARMv8-M specific instructions and
reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
(arm_archs): Define armv8-m.main architecture.
(cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
clarify the ordering rule.
(aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
to 'A' if extension bit for atomic instructions is set, unless it is
ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
for ARMv8-M Mainline.
gas/testsuite/
* gas/arm/archv8m.s: New file.
* gas/arm/archv8m-main.d: Likewise.
* gas/arm/attr-march-armv8m.main.d: Likewise.
* gas/arm/any-armv8m.s: Likewise.
* gas/arm/any-armv8m.d: Likewise.
include/elf/
* arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
(MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
(TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.
include/opcode/
* arm.h (ARM_EXT2_ATOMICS): New extension bit.
(ARM_EXT2_V8M): Likewise.
(ARM_EXT_V8): Adjust comment with regards to atomics and remove
mention of legacy use for that bit.
(ARM_AEXT2_V8_1A): New architecture extension bitfield.
(ARM_AEXT2_V8_2A): Likewise.
(ARM_AEXT_V8M_MAIN): Likewise.
(ARM_AEXT2_V8M): Likewise.
(ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
(ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
(ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
(ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
(ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
and reindent.
(ARM_ARCH_V8A_SIMD): Likewise.
(ARM_ARCH_V8A_CRYPTOV1): Likewise.
(ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
feature bits.
(ARM_ARCH_V8_1A_SIMD): Likewise.
(ARM_ARCH_V8_1A_CRYPTOV1): Likewise.
opcodes/
* arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
ARM_EXT_V8.
(thumb32_opcodes): Add entries for wide ARMv8-M instructions.
Thomas Preud'homme [Thu, 24 Dec 2015 09:01:42 +0000 (17:01 +0800)]
Consolidate Thumb-1/Thumb-2 ISA detection
2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
availability against arm_ext_v6t2 instead of checking arm_arch_t2,
fixing comments along the way.
(handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
generate IT instruction.
(t1_isa_t32_only_insn): New function.
(md_assemble): Use above new function to check for invalid wide
instruction for CPU Thumb ISA and to determine what Thumb extension
bit is necessary for that instruction.
(md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
branch is out of range.
include/opcode/
* arm.h (ARM_ARCH_THUMB2): Add comment explaining its meaning and
remove extension bit not including any Thumb-2 instruction.
Thomas Preud'homme [Thu, 24 Dec 2015 08:50:26 +0000 (16:50 +0800)]
Add tests for gas arch autodetection on ARM
2015-12-09 Andre Vieira <andre.simoesdiasvieira@arm.com>
gas/testsuite/
* gas/arm/automatic-bw.d: New.
* gas/arm/automatic-bw.s: New.
* gas/arm/automatic-cbz.d: New.
* gas/arm/automatic-cbz.s: New.
* gas/arm/automatic-clrex.d: New.
* gas/arm/automatic-clrex.s: New.
* gas/arm/automatic-lda.d: New.
* gas/arm/automatic-lda.s: New.
* gas/arm/automatic-ldaex.d: New.
* gas/arm/automatic-ldaex.s: New.
* gas/arm/automatic-ldaexb.d: New.
* gas/arm/automatic-ldaexb.s: New.
* gas/arm/automatic-ldrex.d: New.
* gas/arm/automatic-ldrex.s: New.
* gas/arm/automatic-ldrexd.d: New.
* gas/arm/automatic-ldrexd.s: New.
* gas/arm/automatic-movw.d: New.
* gas/arm/automatic-movw.s: New.
* gas/arm/automatic-sdiv.d: New.
* gas/arm/automatic-sdiv.s: New.
* gas/arm/automatic-strexb.d: New.
* gas/arm/automatic-strexb.s: New.
Joel Brobecker [Tue, 22 Dec 2015 09:28:41 +0000 (13:28 +0400)]
[testsuite/Ada] stop using project files when building test programs
The current approach when building Ada programs for testing is
based on the use of a project file (testsuite/gdb.ada/gnat_ada.gpr).
To do that, we pass a number of additional arguments to target_compile,
one of them being the project file (via "-P/path/to/gnat_ada.gpr").
This used to work well-enough, but AdaCore is currently working towards
removing project-file support from gnatmake (the prefered tool for
using project files is gprbuild). So, we need to either switch
the compilation to gprbuild, or stop using project files.
First, using gprbuild is not always what users will be using to
build their applications. So having the option of using gnatmake
provides more flexibility towards exactly reproducing past bugs.
If we ever need a testcase that requires the use of gprbuild, then
I believe support for a new target needs to be added to dejagnu's
target_compile.
Also, the only real reason behind using a project file in the first
place is that we wanted to make it easy to specify the directory
where all compilation artifacts get stored. This is a consequence
of the organization choice we made for gdb.ada to keep each testcase
well organized. It is very easy to achieve that goal without using
project files.
This is therefore what this patch does: It change gdb_compile_ada
to build any program using gnatmake without using a project file
(by temporarily changing the current working directory).
There is a small (beneficial) side-effect; in the situation where
GDB is built in-tree, gnatmake is called as...
% gnatmake [...] unit.adb
... which means that the debugging info in unit.o will say contain
a filename whose name is 'unit.adb', rather than '/path/to/unit.adb'.
This also better matches what users might typically do. But the side-
effect is that the unit name in the GDB output is not always a full
path. This patch tweaks a couple of testcases to make the path part
optional.
gdb/testsuite:
* lib/ada.exp (target_compile_ada_from_dir): New function.
(gdb_compile_ada): Reimplement avoiding the use of project files.
* gdb.ada/gnat_ada.gpr: Delete.
* gdb.ada/cond_lang.exp: Adjust test to make path before
filename optional.
* gdb.ada/small_reg_param.exp: Likewise.
Tested on x86_64-linux, with both in-tree and out-of-tree builds.
GDB Administrator [Thu, 24 Dec 2015 00:00:15 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Wed, 23 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Tue, 22 Dec 2015 15:52:31 +0000 (10:52 -0500)]
Remove HP-UX reference in foll-vfork.exp
One more I just found.
Tested with native, native-gdbserver and native-extended-gdbserver on
Linux.
gdb/testsuite/ChangeLog:
* gdb.base/foll-vork.exp: Remove HP-UX special case.
Yury Usishchev [Tue, 22 Dec 2015 15:50:13 +0000 (15:50 +0000)]
ARM: Fix exidx coverage for relocatable builds.
bfd * elf-bfd.h: Add callback to count additional relocations.
* elf32-arm.c (_arm_elf_section_data): Add new counter.
(insert_cantunwind_after): Increment relocations counter.
(elf32_arm_fix_exidx_coverage): Remove exidx entries and add
terminating CANTUNWIND entry only in final builds.
(elf32_arm_add_relocation): New function.
(elf32_arm_write_section): Add relocations in relocatable builds.
(elf32_arm_count_additional_relocs): New function.
(elf_backend_count_additional_relocs): New define.
* bfd/elflink.c (bfd_elf_final_link): Use callback and adjust size of
.rel section.
* bfd/elfxx-target.h (elf_backend_count_additional_relocs): New define.
ld * emultempl/armelf.em (gld${EMULATION_NAME}_after_allocation): Call
elf32_arm_fix_exidx_coverage for relocatable builds.
ld/testsuite
* ld-arm/arm-elf.exp: New test.
* ld-arm/unwind-rel.d: New file.
* ld-arm/unwind-rel1.s: New file.
* ld-arm/unwind-rel2.s: New file.
* ld-arm/unwind-rel3.s: New file.
Joel Brobecker [Sun, 20 Dec 2015 14:39:40 +0000 (09:39 -0500)]
[lynxos] gdbserver hangs when killing inferior from GDB
With any program under GDBserver control on LynxOS, killing
the program from the debugger (using the "kill" command) causes
GDBserver to properly kill the inferior but GDBserver then hangs.
This change of behavior occured after the following change was
applied:
commit
f0ea042932e6922c90df3fd0001497d287b97677
Date: Mon Nov 30 16:05:27 2015 +0000
Subject: gdbserver: don't exit until GDB disconnects
One of the changes introduced by the commit above is that
process_serial_event no longer calls exit after handling
the vKill packet. Instead, what happens is that we wait
until captured_main finds that we no longer have any inferior
to debug, at which point it throws_quit. This (normal) exception
is then expected to propagate all the way to the exception handle
in function "main", which calls exit.
However, before the exception gets propagated, the cleanups
are first executed, and one of the cleanups in question is
detach_or_kill_for_exit_cleanup, which was put in place by
captured_main. detach_or_kill_for_exit_cleanup is basically
a wrapper around detach_or_kill_for_exit, which iterates
over all inferiors, and kills them all.
In our case, we have only one inferior, which we have already
killed during the handling for the "vKill" packet. Unfortunately,
we did not properly clean our internal data for that inferior up,
and so detach_or_kill_for_exit thinks that we still have one inferior,
and therefore tries to kill it. This results in lynx_kill being
called, doing the following:
lynx_ptrace (PTRACE_KILL, ptid, 0, 0, 0);
lynx_wait (ptid, &status, 0);
the_target->mourn (process);
The hang is caused by the call to lynx_wait, which waits for
an event from a process which does not exist...
This patch fixes the issue by enhancing lynx_mourn to clean
the threads and process list up.
gdb/gdbserver/ChangeLog:
* lynx-low.c (lynx_delete_thread_callback): New function.
(lynx_mourn): Properly delete our process and all of its
threads. Remove call to clear_inferiors.
Joel Brobecker [Sun, 20 Dec 2015 05:49:59 +0000 (00:49 -0500)]
gdbserver crash in gdb/gdbserver/thread.c::thread_search_callback
Connecting GDB to a LynxOS-178 GDBserver causes GDBserver to crash:
% gdbserver :4444 simple_main
Process simple_main created; pid = 19
Listening on port 4444
Remote debugging from host 205.232.38.10
Segmentation fault (core dumped)
The crash happens in thread_search_callback where the function
calls the_target->thread_stopped (via the thread_stopped macro)
without verifying whether the callback is NULL or not.
For the record, the regression was introduced by:
commit
a67a9faef0e32886c83611cc7a0ba61e91123063
Date: Mon Nov 30 16:05:26 2015 +0000
Subject: gdbserver:prepare_access_memory: pick another thread
This patch avoids the crash by checking the value of the callback
first, before calling it.
gdb/gdbserver/ChangeLog:
* target.c (thread_search_callback): Add check that
the thread_stopped target callback is not NULL before
calling it.
Joel Brobecker [Sat, 19 Dec 2015 14:21:01 +0000 (09:21 -0500)]
[win32] cannot automatically find executable file [...] warning at GDB startup
The following change...
commit
43499ea30db2a866412c86952c7e1d7b158d806f
Date: Tue Nov 17 15:17:44 2015 +0000
Subject: [C++/mingw] windows-nat.c casts
... causes a small regression in GDB, where we get the following
warning at startup:
% gdb
C:\[...]\gdb.exe: warning: cannot automatically find executable file or library to read symbols.
Use "file" or "dll" command to load executable/libraries directly.
GNU gdb (GDB) 7.10.50.
20151218-cvs (with AdaCore local changes)
[...]
(gdb)
The warning comes from _initialize_loadable which tries to dynamically
load some symbols from kernel32.dll and psapi.dll, and in particular:
hm = LoadLibrary ("psapi.dll");
if (hm)
{
GPA (hm, EnumProcessModules);
GPA (hm, GetModuleInformation);
GPA (hm, GetModuleFileNameEx);
}
The problem is that the new GPA macro assumes that the name of
the variable we use to point to the function, and the name of
its associated symbol are the same. This is mostly the case,
except for GetModuleFileNameEx, where the name is provided by
the GetModuleFileNameEx_name macro (defined differently depending
on whether we are on cygwin or not). As a result, the dynamic
resolution for GetModuleFileNameEx returns NULL, and we trip
the following check which leads to the warning:
if (!EnumProcessModules || !GetModuleInformation || !GetModuleFileNameEx)
{
[...]
warning(_("[...]"));
}
This patch fixes the problem by calling GetProcAddress directly,
rather than through the GPA macro, but in a way which hopefully
avoids the C++ compilation warning that the previous patch was
trying to get rid of.
gdb/ChangeLog:
* windows-nat.c (_initialize_loadable): Fix computing of
GetModuleFileNameEx.
Yoshinori Sato [Wed, 16 Dec 2015 16:42:34 +0000 (01:42 +0900)]
RXv2 support update
2015-12-22 Yoshinori Sato <ysato@users.sourceforge.jp>
opcodes/
* rx-decode.opc (movco): Use uniqe id.
(movli): Likewise.
(stnz): Condition fix.
(mvtacgu): Destination fix.
* rx-decode.c: Regenerate.
bfd/
* archures.c: Add bfd_mach_rx_v2.
* bfd-in2.h: Regenerate.
* cpu-rx.c (arch_info_struct): Add v2 information.
* elf32-rx.c (elf32_rx_machine): Add v2 support.
Mickael Guene [Tue, 22 Dec 2015 14:12:35 +0000 (14:12 +0000)]
Add support for ARM's NOREAD section flag.
include/elf
* arm.h: Add arm SHF_ARM_NOREAD section flag.
bfd * bfd-in2.h: Regenerate.
* section.c: Add SEC_ELF_NOREAD.
* elf32-arm.c (elf32_arm_post_process_headers): Only set
PF_X attribute if a segment only contains section with
SHF_ARM_NOREAD flag.
(elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion.
(elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD
to bfd flag.
(elf32_arm_lookup_section_flags): New function to allow
INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag.
(elf32_arm_special_sections): Add special sections array
to catch section prefix by '.text.noread' pattern.
ld/testsuite
* ld-arm/arm-elf.exp: New tests.
* ld-arm/thumb1-input-section-flag-match.d: New
* ld-arm/thumb1-input-section-flag-match.s: New
* ld-arm/thumb1-noread-not-present-mixing-two-section.d: New
* ld-arm/thumb1-noread-not-present-mixing-two-section.s: New
* ld-arm/thumb1-noread-present-one-section.d: New
* ld-arm/thumb1-noread-present-one-section.s: New
* ld-arm/thumb1-noread-present-two-section.d: New
* ld-arm/thumb1-noread-present-two-section.s: New
binutils
* readelf.c (get_elf_section_flags): Add support for ARM specific
section flags.
Thomas Preud'homme [Tue, 22 Dec 2015 02:50:21 +0000 (10:50 +0800)]
Add an expect for running commands with CLI jump
2015-12-22 Thomas Preud'homme <thomas.preudhomme@arm.com>
gdb/testsuite/
* lib/mi-support.exp (mi_run_cmd_full): Add an expect for the CLI jump
case.
GDB Administrator [Tue, 22 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Mon, 21 Dec 2015 19:38:51 +0000 (14:38 -0500)]
Remove dead code in testsuite
This patch removes cases from the testsuite that are not posssibly used. The
messages "Catch of * not yet implemented" were removed here:
https://www.sourceware.org/ml/gdb-patches/2004-01/msg00679.html
I changed the regexp at the same time to match the string more closely.
gdb/testsuite/ChangeLog:
* gdb.base/break.exp: Remove dead code.
* gdb.base/sepdebug.exp: Likewise.
Simon Marchi [Mon, 21 Dec 2015 17:51:54 +0000 (12:51 -0500)]
Remove HP-UX references fom testsuite
This patch removes all special cases for HP-UX, for which support has
been removed earlier, that I found in the testsuite. Note that the hppa
architecture != HP-UX, since other OSes can run on hppa, so I tried to
leave everything that is not HP-UX specific.
Two complete tests were completely HP-UX specific, so I removed them.
I ran the testsuite on Linux x86-64, native and native-gdbserver, and
noticed no regressions.
gdb/testsuite/ChangeLog:
* gdb.asm/asm-source.exp: Remove HP-UX references.
* gdb.base/annota1.exp: Likewise.
* gdb.base/annota3.exp: Likewise.
* gdb.base/attach.exp: Likewise.
* gdb.base/bigcore.exp: Likewise.
* gdb.base/break.exp: Likewise.
* gdb.base/call-ar-st.exp: Likewise.
* gdb.base/callfuncs.exp: Likewise.
* gdb.base/catch-fork-static.exp: Likewise.
* gdb.base/display.exp: Likewise.
* gdb.base/foll-exec-mode.exp: Likewise.
* gdb.base/foll-exec.exp: Likewise.
* gdb.base/foll-fork.exp: Likewise.
* gdb.base/foll-vfork.exp: Likewise.
* gdb.base/funcargs.exp: Likewise.
* gdb.base/hbreak2.exp: Likewise.
* gdb.base/inferior-died.exp: Likewise.
* gdb.base/interrupt.exp: Likewise.
* gdb.base/multi-forks.exp: Likewise.
* gdb.base/nodebug.exp: Likewise.
* gdb.base/sepdebug.exp: Likewise.
* gdb.base/solib1.c: Likewise.
* gdb.base/step-test.exp: Likewise.
* gdb.mi/non-stop.c: Likewise.
* gdb.mi/pthreads.c: Likewise.
* gdb.multi/bkpt-multi-exec.ex: Likewise.
* gdb.threads/pthreads.c: Likewise.
* gdb.threads/staticthreads.exp: Likewise.
* lib/future.exp: Likewise.
* lib/gdb.exp: Likewise.
* gdb.base/so-indr-cl.c: Remove.
* gdb.base/so-indr-cl.exp: Likewise.
* gdb.base/solib.c: Likewise.
* gdb.base/solib.exp: Likewise.
* gdb.base/solib2.c: Likewise.
Simon Marchi [Mon, 21 Dec 2015 16:23:43 +0000 (11:23 -0500)]
Remove references to HP CC/aCC compiler from testsuite
The HP CC/aCC compiler is exclusive to HP-UX, for which support has been
explicitly removed. Therefore, It does not make sense to keep tests
for these compilers' quirks.
gdb/testsuite/ChangeLog:
* gdb.base/break.exp: Remove references to HP CC/aCC compilers.
* gdb.base/call-ar-st.exp: Likewise.
* gdb.base/callfuncs.exp: Likewise.
* gdb.base/condbreak.exp: Likewise.
* gdb.base/constvars.exp: Likewise.
* gdb.base/hbreak2.exp: Likewise.
* gdb.base/langs.exp: Likewise.
* gdb.base/list.exp: Likewise.
* gdb.base/long_long.exp: Likewise.
* gdb.base/ptype.exp: Likewise.
* gdb.base/scope.exp: Likewise.
* gdb.base/signals.exp: Likewise.
* gdb.base/so-impl-ld.exp: Likewise.
* gdb.base/varargs.exp: Likewise.
* gdb.base/volatile.exp: Likewise.
* gdb.base/whatis.exp: Likewise.
* gdb.cp/cplusfuncs.exp: Likewise.
* gdb.cp/inherit.exp: Likewise.
* gdb.cp/local.exp: Likewise.
* gdb.cp/member-ptr.exp: Likewise.
* gdb.cp/method.exp: Likewise.
* gdb.cp/overload.exp: Likewise.
* gdb.cp/templates.exp: Likewise.
* gdb.stabs/weird.exp: Likewise.
* lib/compiler.c: Likewise.
* lib/compiler.cc: Likewise.
* lib/cp-support.exp: Likewise.
* lib/gdb.exp: Likewise.
Yao Qi [Mon, 21 Dec 2015 13:55:45 +0000 (13:55 +0000)]
Use arm_eabi_breakpoint on aarch32
This patch is to get
b37a6290 back again, which was removed by
d9311bfa by mistake.
gdb/gdbserver:
2015-12-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.h [__aarch64__]: Use arm_abi_breakpoint
arm breakpoint.
Nick Clifton [Mon, 21 Dec 2015 12:00:04 +0000 (12:00 +0000)]
Fix building pdfs of assembler documentation.
PR gas/19386
* doc/as.texinfo (Strings): Prepend a space to index entries that
start with a backslash. This works around a problem in the pdf
generator.
Joel Brobecker [Mon, 21 Dec 2015 02:51:50 +0000 (06:51 +0400)]
Minor reformatting fix in gdbtypes.c::create_array_type_with_stride
gdb/ChangeLog:
* gdbtypes.c (create_array_type_with_stride): Fix indentation.
GDB Administrator [Mon, 21 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Sun, 20 Dec 2015 14:59:02 +0000 (09:59 -0500)]
Remove HP-UX reference in testsuite/configure.ac
gdb/testsuite/ChangeLog:
* configure.ac: Remove HP-UX case.
* configure: Regenerate.
GDB Administrator [Sun, 20 Dec 2015 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Joel Brobecker [Sat, 19 Dec 2015 03:28:41 +0000 (07:28 +0400)]
Fix ARI warning in gdb/arch/arm-get-next-pcs.c
gdb/ChangeLog:
* arch/arm-get-next-pcs.c (arm_get_next_pcs_raw): Remove trailing
newline at end of error message.
Sandra Loosemore [Sat, 19 Dec 2015 01:55:26 +0000 (17:55 -0800)]
Reset pagination counts even when stdin is not a tty.
2015-12-18 Sandra Loosemore <sandra@codesourcery.com>
gdb/
* event-top.c (command_handler): Don't require stdin to be a tty
for call to reinitialize_more_filter.
* top.c (command_loop): Likewise.
Sandra Loosemore [Sat, 19 Dec 2015 01:53:11 +0000 (17:53 -0800)]
Make prompt_for_continue call throw_quit directly.
2015-12-18 Sandra Loosemore <sandra@codesourcery.com>
gdb/
* utils.c (prompt_for_continue): Call throw_quit directly on 'q'.
GDB Administrator [Sat, 19 Dec 2015 00:00:09 +0000 (00:00 +0000)]
Automatic date update in version.in
H.J. Lu [Fri, 18 Dec 2015 22:03:43 +0000 (14:03 -0800)]
Process 64-bit imm/disp only for 64-bit BFD
We only need to store 32-bit immediate in 64-bit and optimize 64-bit
displacement to 32-bit only for 64-bit BFD.
* config/tc-i386.c (optimize_imm): Store 32-bit immediate in
64-bit only for 64-bit BFD
(optimize_disp): Optimize 64-bit displacement to 32-bit only
for 64-bit BFD.
Antoine Tremblay [Fri, 18 Dec 2015 20:23:58 +0000 (15:23 -0500)]
Cast to enum bfd_endian in arm_get_next_pcs_read_memory_unsigned_integer
This patch fixes the cxx build broken by commit :
d9311bfaf572cf14af577a66e79c51c491553552.
Pushed as obvious.
gdb/ChangeLog:
* arm-tdep.c (arm_get_next_pcs_read_memory_unsigned_integer): Cast
to enum bfd_endian)
Simon Marchi [Fri, 18 Dec 2015 18:39:26 +0000 (13:39 -0500)]
Add documentation to gdb_compile
This patch adds some documentation to gdb_compile. It describes the
various options that can influence compilation. Most of them are
handled by DejaGnu, but are not really documented anywhere, so I think
it's good to have a quick reference. Not all possible options are
described, that would add way to much noise. I chose those that I think
are relevant in the context of writing a test case.
gdb/testsuite/ChangeLog:
* lib/gdb.exp (gdb_compile): Add function doc.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Enable conditional breakpoints for targets that support software single step in GDBServer
This patch enables support for conditional breakpoints if the target supports
software single step.
This was disabled before as the implementations of software single step were too
simple as discussed in
https://sourceware.org/ml/gdb-patches/2015-04/msg01110.html.
Since these issues are now fixed support can be added back.
New tests passing :
PASS: gdb.base/cond-eval-mode.exp: set breakpoint condition-evaluation
target and related...
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/gdbserver/ChangeLog:
* server.c (handle_query): Call target_supports_software_single_step.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Enable software single stepping for while-stepping actions in GDBServer
This patch enables software single stepping if the targets support it,
to do while-stepping actions.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/gdbserver/ChangeLog:
* linux-low.c (single_step): New function.
(linux_resume_one_lwp_throw): Call single_step.
(start_step_over): Likewise.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Support software single step on ARM in GDBServer
This patch teaches GDBServer how to software single step on ARM
linux by sharing code with GDB.
The arm_get_next_pcs function in GDB is now shared with GDBServer. So
that GDBServer can use the function to return the possible addresses of
the next PC.
A proper shared context was also needed so that we could share the code,
this context is described in the arm_get_next_pcs structure.
Testing :
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Append arm-get-next-pcs.o,
arm-linux.o.
(ALLDEPFILES): Append arm-get-next-pcs.c, arm-linux.c
(arm-linux.o): New rule.
(arm-get-next-pcs.o): New rule.
* arch/arm-get-next-pcs.c: New file.
* arch/arm-get-next-pcs.h: New file.
* arch/arm-linux.h: New file.
* arch/arm-linux.c: New file.
* arm.c: Include common-regcache.c.
(thumb_advance_itstate): Moved from arm-tdep.c.
(arm_instruction_changes_pc): Likewise.
(thumb_instruction_changes_pc): Likewise.
(thumb2_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
* arm.h (submask): Move macro from arm-tdep.h
(bit): Likewise.
(bits): Likewise.
(sbits): Likewise.
(BranchDest): Likewise.
(thumb_advance_itstate): Moved declaration from arm-tdep.h
(arm_instruction_changes_pc): Likewise.
(thumb_instruction_changes_pc): Likewise.
(thumb2_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
* arm-linux-tdep.c: Include arch/arm.h, arch/arm-get-next-pcs.h
arch/arm-linux.h.
(arm_linux_get_next_pcs_ops): New struct.
(ARM_SIGCONTEXT_R0, ARM_UCONTEXT_SIGCONTEXT,
ARM_OLD_RT_SIGFRAME_SIGINFO, ARM_OLD_RT_SIGFRAME_UCONTEXT,
ARM_NEW_RT_SIGFRAME_UCONTEXT, ARM_NEW_SIGFRAME_MAGIC): Move stack
layout defines to arch/arm-linux.h.
(arm_linux_sigreturn_next_pc_offset): Move to arch/arm-linux.c.
(arm_linux_software_single_step): Adjust for arm_get_next_pcs
implementation.
* arm-tdep.c: Include arch/arm-get-next-pcs.h.
(arm_get_next_pcs_ops): New struct.
(submask): Move macro to arm.h.
(bit): Likewise.
(bits): Likewise.
(sbits): Likewise.
(BranchDest): Likewise.
(thumb_instruction_changes_pc): Move to arm.c
(thumb2_instruction_changes_pc): Likewise.
(arm_instruction_changes_pc): Likewise.
(shifted_reg_val): Likewise.
(thumb_advance_itstate): Likewise.
(thumb_get_next_pc_raw): Move to arm-get-next-pcs.c.
(arm_get_next_pc_raw): Likewise.
(arm_get_next_pc): Likewise.
(thumb_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence): Likewise.
(arm_get_next_pcs_read_memory_unsigned_integer): New function.
(arm_get_next_pcs_addr_bits_remove): Likewise.
(arm_get_next_pcs_syscall_next_pc): Likewise.
(arm_get_next_pcs_is_thumb): Likewise.
(arm_software_single_step): Adjust for arm_get_next_pcs
implementation.
* arm-tdep.h: (arm_get_next_pc): Remove declaration.
(arm_get_next_pcs_read_memory_unsigned_integer):
New declaration.
(arm_get_next_pcs_addr_bits_remove): Likewise.
(arm_get_next_pcs_syscall_next_pc): Likewise.
(arm_get_next_pcs_is_thumb): Likewise.
(arm_deal_with_atomic_sequence: Remove declaration.
* common/gdb_vecs.h: Add CORE_ADDR vector definition.
* configure.tgt (aarch64*-*-linux): Add arm-get-next-pcs.o,
arm-linux.o.
(arm*-wince-pe): Add arm-get-next-pcs.o.
(arm*-*-linux*): Add arm-get-next-pcs.o, arm-linux.o,
arm-get-next-pcs.o
(arm*-*-netbsd*,arm*-*-knetbsd*-gnu): Add arm-get-next-pcs.o.
(arm*-*-openbsd*): Likewise.
(arm*-*-symbianelf*): Likewise.
(arm*-*-*): Likewise.
* symtab.h: Move CORE_ADDR vector definition to gdb_vecs.h.
gdb/gdbserver/ChangeLog:
* Makefile.in (SFILES): Append arch/arm-linux.c,
arch/arm-get-next-pcs.c.
(arm-linux.o): New rule.
(arm-get-next-pcs.o): New rule.
* configure.srv (arm*-*-linux*): Add arm-get-next-pcs.o,
arm-linux.o.
* linux-aarch32-low.c (arm_abi_breakpoint): Remove macro. Moved
to linux-aarch32-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): Make non-static.
* linux-aarch32-low.h (arm_abi_breakpoint): New macro. Moved
from linux-aarch32-low.c.
(arm_eabi_breakpoint, arm_breakpoint): Likewise.
(arm_breakpoint_len, thumb_breakpoint): Likewise.
(thumb_breakpoint_len, thumb2_breakpoint): Likewise.
(thumb2_breakpoint_len): Likewise.
(arm_is_thumb_mode): New declaration.
* linux-arm-low.c: Include arch/arm-linux.h
aarch/arm-get-next-pcs.h, sys/syscall.h.
(get_next_pcs_ops): New struct.
(get_next_pcs_addr_bits_remove): New function.
(get_next_pcs_is_thumb): New function.
(get_next_pcs_read_memory_unsigned_integer): Likewise.
(arm_sigreturn_next_pc): Likewise.
(get_next_pcs_syscall_next_pc): Likewise.
(arm_gdbserver_get_next_pcs): Likewise.
(struct linux_target_ops) <arm_gdbserver_get_next_pcs>:
Initialize.
* linux-low.h: Move CORE_ADDR vector definition to gdb_vecs.h.
* server.h: Include gdb_vecs.h.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Share regcache function regcache_raw_read_unsigned
This patch is in preparation for software single step support on ARM in
GDBServer. It adds a new shared function regcache_raw_read_unsigned and
regcache_raw_get_unsigned so that GDB and GDBServer can use the same call
to fetch a raw register into an integer.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* Makefile.in (SFILES): Append common/common-regcache.c.
(COMMON_OBS): Append common/common-regcache.o.
(common-regcache.o): New rule.
* common/common-regcache.h (register_status) New enum.
(regcache_raw_read_unsigned): New declaration.
* common/common-regcache.c: New file.
* regcache.h (enum register_status): Move to common-regcache.h.
(regcache_raw_read_unsigned): Likewise.
(regcache_raw_get_unsigned): Likewise.
gdb/gdbserver/ChangeLog:
* Makefile.in (SFILES): Append common/common-regcache.c.
(OBS): Append common-regcache.o.
(common-regcache.o): New rule.
* regcache.c (init_register_cache): Initialize cache to
REG_UNAVAILABLE.
(regcache_raw_read_unsigned): New function.
* regcache.h (REG_UNAVAILABLE, REG_VALID): Replaced by shared
register_status enum.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:59 +0000 (11:33 -0500)]
Refactor arm_software_single_step to use regcache
This patch is in preparation for software single step support on ARM in
GDBServer. It refactors arm_*_software_single_step and sub-functions to
use regcache instead of frame to access registers so that the code can be
shared more easily between GDB and GDBServer.
Note also that since the intention is at some point to get rid of frame
completely in that function, memory reads have also been replaced by
read_memory_unsigned_integer rather than get_frame_memory_unsigned.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/ChangeLog:
* arm-linux-tdep.c (arm_linux_sigreturn_next_pc_offset): New function.
(arm_linux_sigreturn_next_pc): Likewise.
(arm_linux_syscall_next_pc): Use regcache instead of frame.
(arm_linux_software_single_step): Likewise.
* arm-tdep.c (arm_is_thumb): New function.
(shifted_reg_va): Use regcache instead of frame.
(thumb_get_next_pc_raw): Likewise.
(arm_get_next_pc_raw): Likewise.
(arm_get_next_pc): Likewise.
(thumb_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence_raw): Likewise.
(arm_deal_with_atomic_sequence): Likewise.
(arm_software_single_step): Likewise.
* arm-tdep.h (struct gdbarch_tdep): Use regcache for syscall_next_pc.
(arm_get_next_pc): Use regcache.
(arm_deal_with_atomic_sequence): Likewise.
(arm_is_thumb): New declaration.
* regcache.c (regcache_raw_get_unsigned): New function.
* regcache.h (regcache_raw_get_unsigned): New function declaration.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:58 +0000 (11:33 -0500)]
Share some ARM target dependent code from GDB with GDBServer
This patch is in preparation for software single stepping support on ARM
it shares some functions and definitions that will be needed.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
Not tested: wince/bsd build.
gdb/ChangeLog:
* arch/arm.c (bitcount): Move from arm-tdep.c.
(condition_true): Likewise.
* arch/arm.h (Instruction Definitions): Move form arm-tdep.h.
(condition_true): Move defenition from arm-tdep.h.
(bitcount): Likewise.
* arm-tdep.c (condition_true): Move to arch/arm.c.
(bitcount): Likewise.
* arm-tdep.h (Instruction Definitions): Move to arch/arm.h.
* arm-wince-tdep.c: Include arch/arm.h.
* armnbsd-tdep.c: Likewise.
Antoine Tremblay [Fri, 18 Dec 2015 16:33:58 +0000 (11:33 -0500)]
Replace breakpoint_reinsert_addr by get_next_pcs operation in GDBServer
This patch in preparation for software single step support on ARM. It refactors
breakpoint_reinsert_addr into get_next_pcs so that multiple location can be
returned.
When software single stepping there can be multiple possible next addresses
because we're stepping over a conditional branch instruction, for example.
The operation get_next_pcs handles that by returning a vector of all the
possible next addresses.
Software breakpoints are installed at each location returned.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
gdb/gdbserver/ChangeLog:
* linux-aarch64-low.c (the_low_targets): Rename
breakpoint_reinsert_addr to get_next_pcs.
* linux-arm-low.c (the_low_targets): Likewise.
* linux-bfin-low.c (the_low_targets): Likewise.
* linux-cris-low.c (the_low_targets): Likewise.
* linux-crisv32-low.c (the_low_targets): Likewise.
* linux-low.c (can_software_single_step): Likewise.
(install_software_single_step_breakpoints): New function.
(start_step_over): Use install_software_single_step_breakpoints.
* linux-low.h: New CORE_ADDR vector.
(struct linux_target_ops) Rename breakpoint_reinsert_addr to
get_next_pcs.
* linux-mips-low.c (the_low_targets): Likewise.
* linux-nios2-low.c (the_low_targets): Likewise.
* linux-sparc-low.c (the_low_targets): Likewise.
H.J. Lu [Fri, 18 Dec 2015 16:15:27 +0000 (08:15 -0800)]
Fix formatting in coff-x86_64.c
* coff-x86_64.c (coff_amd64_reloc): Fix formatting.
Nick Clifton [Fri, 18 Dec 2015 08:49:02 +0000 (08:49 +0000)]
Fix formatting of coff-i386.c
* coff-i386.c (coff_i386_reloc): Fix formatting.
Peter Collingbourne [Fri, 18 Dec 2015 00:50:35 +0000 (16:50 -0800)]
Implement --long-plt flag (ARM only).
gold/
PR gold/18780
* arm.cc (Target_arm::do_make_data_plt): Choose PLT generator based
on value of --long-plt flag.
(Output_data_plt_arm_standard::do_get_plt_entry_size): Moved to
Output_data_plt_arm_short.
(Output_data_plt_arm_standard::do_fill_plt_entry): Likewise.
(Output_data_plt_arm_standard::plt_entry): Likewise.
(Output_data_plt_arm_standard::do_fill_first_plt_entry): Fix
variable reference.
(Output_data_plt_arm_short): New class.
(Output_data_plt_arm_short::do_fill_plt_entry): Error out on too large
PLT offsets instead of asserting.
(Output_data_plt_arm_long): New class.
* options.h (General_options): Define --long-plt flag.
GDB Administrator [Fri, 18 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Maciej W. Rozycki [Thu, 17 Dec 2015 17:25:42 +0000 (17:25 +0000)]
MAINTAINERS: Add myself as MIPS maintainer
binutils/
* MAINTAINERS: Add myself as MIPS maintainer.
Ramana Radhakrishnan [Thu, 17 Dec 2015 16:33:24 +0000 (16:33 +0000)]
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
Add missing ChangeLog entry.
Pedro Alves [Thu, 17 Dec 2015 14:20:52 +0000 (14:20 +0000)]
Fix PR threads/19354: "info threads" error with multiple inferiors
Note: this applies on top of:
[PATCH] Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTL
https://sourceware.org/ml/gdb-patches/2015-12/msg00214.html
We try to avoid using libthread_db.so to list threads in the inferior
when debugging live processes, but the code that decides whether to
use it decides incorrectly if you have more than one inferior, and the
current inferior doesn't have execution yet. The result is visible
as:
(gdb) add-inferior
Added inferior 2
(gdb) inferior 2
[Switching to inferior 2 [<null>] (<noexec>)]
(gdb) info inferiors
Num Description Executable
1 process 15397 /home/pedro/gdb/tests/threads
* 2 <null>
(gdb) info threads
Cannot find new threads: generic error
(gdb)
Fix this by checking whether each inferior has execution rather than
just the current inferior.
By moving the core updating to linux-nat.c's update_thread_list
implementation, this also ends up fixing the
lwp-last-seen-running-on-core updating in the case we're debugging a
program that uses raw clone rather than pthreads, as linux-thread-db.c
isn't pushed in the target stack in that scenario.
Tested on x86_64 Fedora 20.
gdb/ChangeLog:
2015-12-17 Pedro Alves <palves@redhat.com>
PR threads/19354
* linux-nat.c (linux_nat_update_thread_list): Update process cores
each lwp was last seen running on here.
* linux-thread-db.c (update_thread_core): Delete.
(thread_db_update_thread_list_td_ta_thr_iter): Rename to ...
(thread_db_update_thread_list): ... this. Skip inferiors with
execution. Also call the target beneath.
(thread_db_update_thread_list): Delete.
gdb/testsuite/ChangeLog:
2015-12-17 Pedro Alves <palves@redhat.com>
PR threads/19354
* gdb.multi/info-threads.exp: New file.
Pedro Alves [Thu, 17 Dec 2015 14:20:51 +0000 (14:20 +0000)]
Remove support for LinuxThreads and vendor 2.4 kernels w/ backported NPTL
Since we now rely on PTRACE_EVENT_CLONE being available (added in
Linux 2.5.46), we're relying on NPTL.
This commit removes the support for older LinuxThreads, as well as the
workarounds for vendor 2.4 kernels with NPTL backported.
- Rely on tkill being available.
- Assume gdb doesn't get cancel signals.
- Remove code that checks the LinuxThreads restart and cancel signals
in the inferior.
- Assume that __WALL is available.
- Assume that non-leader threads report WIFEXITED.
- Thus, no longer need to send signal 0 to check whether threads are
still alive.
- Update comments throughout.
Tested on x86_64 Fedora 20, native and gdbserver.
gdb/ChangeLog:
* configure.ac: Remove tkill checks.
* configure, config.in: Regenerate.
* linux-nat.c: Remove HAVE_TKILL_SYSCALL check. Update top level
comments.
(linux_nat_post_attach_wait): Remove 'cloned' parameter. Use
__WALL.
(attach_proc_task_lwp_callback): Don't set the cloned flag.
(linux_nat_attach): Adjust.
(kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back
to 'kill'.
(linux_handle_extended_wait): Use __WALL. Don't set the cloned
flag.
(wait_lwp): Use __WALL. Update comments.
(running_callback, stop_and_resume_callback): Delete.
(linux_nat_filter_event): Don't stop and resume all lwps. Don't
check if the event LWP has previously exited.
(check_zombie_leaders): Update comments.
(linux_nat_wait_1): Use __WALL.
(kill_wait_callback): Don't handle clone processes separately.
Use __WALL instead.
(linux_thread_alive): Delete.
(linux_nat_thread_alive): Return true as long as the LWP is in the
LWP list.
(linux_nat_update_thread_list): Assume the kernel supports
PTRACE_EVENT_CLONE.
(get_signo): Delete.
(lin_thread_get_thread_signals): Remove LinuxThreads references.
No longer check __pthread_sig_restart / __pthread_sig_cancel in
the inferior.
* linux-nat.h (struct lwp_info) <cloned>: Delete field.
* linux-thread-db.c: Update comments.
(_initialize_thread_db): Remove LinuxThreads references.
* nat/linux-waitpid.c (my_waitpid): No longer emulate __WALL.
Pass down flags unmodified.
* linux-waitpid.h (my_waitpid): Update documentation.
gdb/gdbserver/ChangeLog:
* linux-low.c (linux_kill_one_lwp): Remove references to
LinuxThreads.
(kill_lwp): Remove HAVE_TKILL_SYSCALL check. No longer fall back
to 'kill'.
(linux_init_signals): Delete.
(initialize_low): Adjust.
* thread-db.c (thread_db_init): Remove LinuxThreads reference.
Yao Qi [Thu, 17 Dec 2015 13:07:54 +0000 (13:07 +0000)]
Fix one heap buffer overflow in aarch64_push_dummy_call
Hi,
AddressSanitizer reports an error like this,
(gdb) PASS: gdb.base/call-ar-st.exp: continue to tbreak9
print print_long_arg_list(a, b, c, d, e, f, *struct1, *struct2, *struct3, *struct4, *flags, *flags_combo, *three_char, *five_char, *int_char_combo, *d1, *d2, *d3, *f1, *f2, *f3)
=================================================================
==6236==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60200008eb50 at pc 0x89e432 bp 0x7fffa3df9080 sp 0x7fffa3df9078
READ of size 5 at 0x60200008eb50 thread T0
#0 0x89e431 in memory_xfer_partial gdb/target.c:1264
#1 0x89e6c7 in target_xfer_partial gdb/target.c:1320
#2 0x89f267 in target_write_partial gdb/target.c:1595^M
#3 0x8a014b in target_write_with_progress gdb/target.c:1889^M
#4 0x8a0262 in target_write gdb/target.c:1914^M
#5 0x89ee59 in target_write_memory gdb/target.c:1492^M
#6 0x9a1c74 in write_memory gdb/corefile.c:393^M
#7 0x467ea5 in aarch64_push_dummy_call gdb/aarch64-tdep.c:1388
The problem is that an instance of stack_item_t is created to adjust
stack for alignment, the item.len is correct, but item.data is buf,
which is wrong, because item.len can be greater than the length of
buf. This patch sets item.data to NULL, and only update sp (no
inferior memory writes on stack for this item).
gdb:
2015-12-17 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (struct stack_item_t): Update comments.
(pass_on_stack): Set item.data to NULL.
(aarch64_push_dummy_call): Call write_memory if si->data
isn't NULL.
Ramana Radhakrishnan [Thu, 17 Dec 2015 10:55:54 +0000 (10:55 +0000)]
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.
In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.
This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.
2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
TAG_ARCH_profile for armv8-a.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
Christophe Lyon [Thu, 17 Dec 2015 10:10:16 +0000 (11:10 +0100)]
Add forgotten ChangeLog updates for
72d98d16ed09584660d0cbb759d90f8dfeef2343:
2015-12-16 Mickael Guene <mickael.guene@st.com>
bfd/
* bfd-in2.h: Regenerate.
* reloc.c: Add new relocations.
* libbfd.h (bfd_reloc_code_real_names): Add new relocations
display names.
* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
relocations.
(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
(elf32_arm_final_link_relocate): Implement new relocations
resolution.
gas/
* doc/c-arm.texi: Add documentation about new directives
* config/tc-arm.c (group_reloc_table): Add mapping between gas
syntax and new relocations.
(do_t_add_sub): Keep new relocations for add operand.
(do_t_mov_cmp): Keep new relocations for mov operand.
(insns): Use 'shifter operand with possible group relocation'
operand parse code for movs operand.
(md_apply_fix): Implement mov and add encoding when new
relocations on them.
(tc_gen_reloc): Add new relocations.
(arm_fix_adjustable): Since offset has a limited range ([0:255])
we disable adjust_reloc_syms() for new relocations.
gas/testsuite/
* gas/arm/adds-thumb1-reloc-local.d: New
* gas/arm/adds-thumb1-reloc-local.s: New
* gas/arm/movs-thumb1-reloc-local.d: New
* gas/arm/movs-thumb1-reloc-local.s: New
include/
* elf/arm.h: Add new arm relocations.
ld/testsuite/
* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
tests.
* ld-arm/thumb1-adds.d: New
* ld-arm/thumb1-adds.s: New
* ld-arm/thumb1-movs.d: New
* ld-arm/thumb1-movs.s: New
Roland McGrath [Thu, 17 Dec 2015 00:35:27 +0000 (16:35 -0800)]
PR gold/17473: Fix gold build with system C++ headers that use <ctype.h>.
gold/
PR gold/17473
* binary.cc: Move #include "safe-ctype.h" to be last #include.
GDB Administrator [Thu, 17 Dec 2015 00:00:09 +0000 (00:00 +0000)]
Automatic date update in version.in
Pedro Alves [Wed, 16 Dec 2015 22:56:48 +0000 (22:56 +0000)]
Fix -Wno-unknown-warning support detection
Ref: https://sourceware.org/ml/gdb/2015-12/msg00024.html
We have code in configure.ac that tries to detect whether the compiler
supports each warning and suppress it if not, but that doesn't work
with "-Wno-" options, because gcc doesn't error out for
-Wno-unknown-warning unless other diagnostics are being produced.
See https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html.
Handle this by checking whether -Wfoo works when we actually want
-Wno-foo.
gdb/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* configure.ac (compiler warning flags): When testing a
-Wno-foo option, check whether -Wfoo works instead.
* configure: Regenerate.
gdb/gdbserver/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* configure.ac (compiler warning flags): When testing a
-Wno-foo option, check whether -Wfoo works instead.
* configure: Regenerate.
Pedro Alves [Wed, 16 Dec 2015 19:25:32 +0000 (19:25 +0000)]
[C++] Fix -Winvalid-offsetof warnings with g++ 4.4
Ref: https://sourceware.org/ml/gdb/2015-12/msg00014.html
Fixes the build in C++ mode with g++ 4.4:
gdb/btrace.h: In function ‘size_t VEC_btrace_insn_s_embedded_size(int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_alloc(int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_copy(VEC_btrace_insn_s*)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘VEC_btrace_insn_s* VEC_btrace_insn_s_merge(VEC_btrace_insn_s*, VEC_btrace_insn_s*)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/btrace.h: In function ‘int VEC_btrace_insn_s_reserve(VEC_btrace_insn_s**, int, const char*, unsigned int)’:
gdb/btrace.h:84: error: invalid access to non-static data member ‘VEC_btrace_insn_s::vec’ of NULL object
gdb/btrace.h:84: error: (perhaps the ‘offsetof’ macro was used incorrectly)
gdb/ChangeLog:
2015-12-16 Pedro Alves <palves@redhat.com>
* common/vec.h (vec_offset): New macro.
(DEF_VEC_ALLOC_FUNC_I, DEF_VEC_ALLOC_FUNC_O): Use it instead of
offsetof.
Mickael Guene [Wed, 16 Dec 2015 09:09:05 +0000 (10:09 +0100)]
[ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
movs r3, #:upper8_15:#foo
lsls r3, #8
adds r3, #:upper0_7:#foo
lsls r3, #8
adds r3, #:lower8_15:#foo
lsls r3, #8
adds r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
4: 2300 movs r3, #0
4: R_ARM_THM_ALU_ABS_G3_NC foo
6: 021b lsls r3, r3, #8
8: 3300 adds r3, #0
8: R_ARM_THM_ALU_ABS_G2_NC foo
a: 021b lsls r3, r3, #8
c: 3300 adds r3, #0
c: R_ARM_THM_ALU_ABS_G1_NC foo
e: 021b lsls r3, r3, #8
10: 3300 adds r3, #0
10: R_ARM_THM_ALU_ABS_G0_NC foo
GDB Administrator [Wed, 16 Dec 2015 00:00:18 +0000 (00:00 +0000)]
Automatic date update in version.in
Matthew Wahab [Tue, 15 Dec 2015 16:37:38 +0000 (16:37 +0000)]
[ARM] Enable CRC by default for ARMv8.1 and later.
ARMv8.1 includes CRC as a required extension but the +crc feature isn't
enabled by -march=armv8.1-a as it should be. This patch fixes that.
opcode/include
2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
* arm.h (ARM_ARCH_V8_1A): Add the CRC_EXT_ARMV8 co-processor
feature macro.
(ARM_ARCH_V8_2A): Likewise.
Change-Id: Id1fe0e6fa51dede19d61e1fd08e68628ea1b1e9e
Nick Clifton [Tue, 15 Dec 2015 16:21:29 +0000 (16:21 +0000)]
Remove refernces to a non-existent silicon errata.
* doc/c-msp430.texi (MSP430 Options): Remove references to a
non-existent silicon errata.
* config/tc-msp430.c: Likewise.
Yao Qi [Tue, 15 Dec 2015 16:09:41 +0000 (16:09 +0000)]
Tweak gdb.trace/ftrace.exp for aarch64
Some tests are skipped on aarch64 unexpectedly because arg0exp isn't
set. This patch is to set arg0exp to "$x0" for aarch64.
gdb/testsuite:
2015-12-15 Yao Qi <yao.qi@linaro.org>
* gdb.trace/ftrace.exp: Set arg0exp to "$x0" if target
is aarch64*-*-*.
Jan Beulich [Tue, 15 Dec 2015 13:31:25 +0000 (14:31 +0100)]
bfd: don't produce corrupt COFF symbol table due to long ELF file name symbols
The re-writing logic in _bfd_coff_final_link() overwrote the ".file"
part of the symbol table entry, due to not coping with the auxiliary
entry generated in all cases.
Note that while I would have wanted to add a test case,
(a) I didn't spot any one testing the base functionality here, and
(b) I wasn't able to figure out proper conditionals to use in e.g.
ld-elf/elf.exp to check for the necessary PE/PE+ support (which
varies by target).
Dominik Vogt [Tue, 15 Dec 2015 13:09:14 +0000 (14:09 +0100)]
Fix invalid left shift of negative value
Fix occurrences of left-shifting negative constants in C code.
sim/arm/ChangeLog:
* thumbemu.c (handle_T2_insn): Fix left shift of negative value.
* armemu.c (handle_v6_insn): Likewise.
sim/avr/ChangeLog:
* interp.c (sign_ext): Fix left shift of negative value.
sim/mips/ChangeLog:
* micromips.igen (process_isa_mode): Fix left shift of negative
value.
sim/msp430/ChangeLog:
* msp430-sim.c (get_op, put_op): Fix left shift of negative value.
sim/v850/ChangeLog:
* simops.c (v850_bins): Fix left shift of negative value.
Nick Clifton [Tue, 15 Dec 2015 12:28:38 +0000 (12:28 +0000)]
Update the copyright notices in the affected files.
PR 19339
* elf-vxworks.h: Update copyright notice.
* elf-vxworks.c: Update copyright notice.
* elf-nacl.h: Update copyright notice.
* elf-nacl.c: Update copyright notice.
Nick Clifton [Tue, 15 Dec 2015 11:01:03 +0000 (11:01 +0000)]
Add support for the MRS instruction to the AArch64 simulator.
* aarch64/simulator.c (system_get): New function. Provides read
access to the dczid system register.
(do_mrs): New function - implements the MRS instruction.
(dexSystem): Call do_mrs for the MRS instruction. Halt on
unimplemented system instructions.
Yoshinori Sato [Tue, 15 Dec 2015 09:26:56 +0000 (09:26 +0000)]
Add support for RX V2 Instruction Set
binutils
* readelf.c(get_machine_flags): Add v2 flag.
gas
* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
* config/tc-rx.c(cpu_type_list): New type lookup table.
(md_parse_option): Use lookup table for choose cpu.
(md_show_usage): Add rxv2 for mcpu option.
* doc/c-rx.texi: Likewise.
* config/rx-parse.y: Add v2 instructions and ACC register.
(rx_check_v2): check v2 type.
include/elf
* rx.h(E_FLAG_RX_V2): New RXv2 type.
include/opcode
* rx.h: Add new instructions.
opcoes
* rx-deocde.opc(rx_decode_opcode): Add new instructions pattern.
* rx-dis.c(register_name): Add new register.
gas/testsuite
* gas/rx/emaca.d: New.
* gas/rx/emaca.sm: New.
* gas/rx/emsba.d: New.
* gas/rx/emsba.sm: New.
* gas/rx/emula.d: New.
* gas/rx/emula.sm: New.
* gas/rx/fadd.d: Add new pattern.
* gas/rx/fadd.sm: Add new pattern.
* gas/rx/fmul.d: Add new pattern.
* gas/rx/fmul.sm: Add new pattern.
* gas/rx/fsqrt.d: New.
* gas/rx/fsqrt.sm: New.
* gas/rx/fsub.d: Add new pattern.
* gas/rx/fsub.sm: Add new pattern.
* gas/rx/ftou.d: New.
* gas/rx/ftou.sm: New.
* gas/rx/maclh.d: New.
* gas/rx/maclh.sm: New.
* gas/rx/maclo.d: Add new pattern.
* gas/rx/maclo.sm: Add new pattern.
* gas/rx/macros.inc: Add new register.
* gas/rx/movco.d: New.
* gas/rx/movco.sm: New.
* gas/rx/movli.d: New.
* gas/rx/movli.sm: New.
* gas/rx/msbhi.d: New.
* gas/rx/msbhi.sm: New.
* gas/rx/msblh.d: New.
* gas/rx/msblh.sm: New.
* gas/rx/msblo.d: New.
* gas/rx/msblo.sm: New.
* gas/rx/mullh.d: New.
* gas/rx/mullh.sm: New.
* gas/rx/mvfacgu.d: New.
* gas/rx/mvfacgu.sm: New.
* gas/rx/mvfachi.d: Add new pattern.
* gas/rx/mvfachi.sm: Add new pattern.
* gas/rx/mvfaclo.d: Add new pattern.
* gas/rx/mvfaclo.sm: Add new pattern.
* gas/rx/mvfacmi.d: Add new pattern.
* gas/rx/mvfacmi.sm: Add new pattern.
* gas/rx/mvfc.d: Add new pattern.
* gas/rx/mvtacgu.d: New.
* gas/rx/mvtacgu.sm: New.
* gas/rx/mvtc.d: Add new pattern.
* gas/rx/popc.d: Add new pattern.
* gas/rx/pushc.d: Add new pattern.
* gas/rx/racl.d: New.
* gas/rx/racl.sm: New.
* gas/rx/racw.d: Add new pattern.
* gas/rx/racw.sm: Add new pattern.
* gas/rx/rdacl.d: New.
* gas/rx/rdacl.sm: New.
* gas/rx/rdacw.d: New.
* gas/rx/rdacw.sm: New.
* gas/rx/rx.exp: Add option.
* gas/rx/stnz.d: Add new pattern.
* gas/rx/stnz.sm: Add new pattern.
* gas/rx/stz.d: Add new pattern.
* gas/rx/stz.sm: Add new pattern.
* gas/rx/utof.d: New.
* gas/rx/utof.sm: New.
GDB Administrator [Tue, 15 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Sandra Loosemore [Mon, 14 Dec 2015 23:22:12 +0000 (15:22 -0800)]
Check for readline support in gdb.base/history-duplicates.exp.
2015-12-14 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* gdb.base/history-duplicates.exp: Skip if no readline support.
Sandra Loosemore [Mon, 14 Dec 2015 23:17:23 +0000 (15:17 -0800)]
Skip gdb.base/gdbinit-history.exp on remote hosts.
2015-12-14 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* gdb.base/gdbinit-history.exp: Skip for remote-host testing.
Sandra Loosemore [Mon, 14 Dec 2015 23:14:03 +0000 (15:14 -0800)]
Skip gdb.base/gdbhistsize-history.exp on remote hosts.
2015-12-14 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* gdb.base/gdbhistsize-history.exp: Skip for remote-host testing.
Sandra Loosemore [Mon, 14 Dec 2015 23:02:59 +0000 (15:02 -0800)]
Skip tests that send ctrl-c to GDB if nointerrupts target property is set.
2015-12-14 Sandra Loosemore <sandra@codesourcery.com>
gdb/testsuite/
* gdb.base/completion.exp: Skip tests that interrupt GDB with
ctrl-C if nointerrupts target property is set.
* gdb.base/double-prompt-target-event-error.exp: Likewise.
* gdb.base/paginate-after-ctrl-c-running.exp: Likewise.
* gdb.base/paginate-bg-execution.exp: Likewise.
* gdb.base/paginate-execution-startup.exp: Likewise.
* gdb.base/random-signal.exp: Likewise.
* gdb.base/range-stepping.exp: Likewise.
* gdb.cp/annota2.exp: Likewise.
* gdb.cp/annota3.exp: Likewise.
* gdb.gdb/selftest.exp: Likewise.
* gdb.threads/continue-pending-status.exp: Likewise.
* gdb.threads/leader-exit.exp: Likewise.
* gdb.threads/manythreads.exp: Likewise.
* gdb.threads/pthreads.exp: Likewise.
* gdb.threads/schedlock.exp: Likewise.
* gdb.threads/sigthread.exp: Likewise.
Don Breazeal [Mon, 14 Dec 2015 19:18:06 +0000 (11:18 -0800)]
Target remote mode fork and exec event documentation
This patch implements documentation updates for target remote mode fork and
exec events. A summary of the rationale for the changes made here:
* Connecting to a remote target -- explain that the two protocols exist.
* Connecting in target remote mode -- explain invoking gdbserver for target
remote mode, and move remote-specific text from original "Connecting to a
remote target" section.
* Connecting in target extended-remote mode -- promote this section from
"Using the gdbserver Program | Running gdbserver | Multi-Process Mode for
gdbserver". Put it next to the target remote mode section.
* Host and target files -- collect paragraphs dealing with how to locate
symbol files from original sections "Connecting to a remote target" and
"Using the gdbserver program | Connecting to gdbserver".
* Steps for connecting to a remote target -- used to be "Using the
gdbserver program | Connecting to gdbserver"
* Remote connection commands -- used to be the bulk of "Connecting to a
remote target". Added "target extended-remote" commands and information.
gdb/ChangeLog:
* NEWS: Announce fork and exec event support for target remote.
gdb/doc/ChangeLog:
* gdb.texinfo (Forks): Correct Linux kernel version where
fork and exec events are supported, add notes about support
of these events in target remote mode.
(Connecting): Reorganize and clarify distinctions between
target remote, extended-remote, and multiprocess.
Reorganize related text from separate sections into new
sections.
(Server): Note effects of target extended-remote mode.
Delete section on Multi-Process Mode for gdbserver.
Move some text to "Connecting" node.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec event support
This patch implements support for fork and exec events with target remote
mode Linux targets. For such targets with Linux kernels 2.5.46 and later,
this enables follow-fork-mode, detach-on-fork and fork and exec
catchpoints.
The changes required to implement this included:
* Don't exit from gdbserver if there are still active inferiors.
* Allow changing the active process in remote mode.
* Enable fork and exec events in remote mode.
* Print "Ending remote debugging" only when disconnecting.
* Combine remote_kill and extended_remote_kill into a single function
that can handle the multiple inferior case for target remote. Also,
the same thing for remote_mourn and extended_remote_mourn.
* Enable process-style ptids in target remote.
* Remove restriction on multiprocess mode in target remote.
gdb/gdbserver/ChangeLog:
* server.c (process_serial_event): Don't exit from gdbserver
in remote mode if there are still active inferiors.
gdb/ChangeLog:
* inferior.c (number_of_live_inferiors): New function.
(have_live_inferiors): Use number_of_live_inferiors in place
of duplicate code.
* inferior.h (number_of_live_inferiors): Declare new function.
* remote.c (set_general_process): Remove restriction on target
remote mode.
(remote_query_supported): Likewise.
(remote_detach_1): Exit in target remote mode only when there
is just one live inferior left.
(remote_disconnect): Unpush the target directly instead of
calling remote_mourn.
(remote_kill): Rewrite function to handle both target remote
and extended-remote. Call remote_kill_k.
(remote_kill_k): New function.
(extended_remote_kill): Delete function.
(remote_mourn, extended_remote_mourn): Combine functions into
one, remote_mourn, and enable extended functionality for target
remote.
(remote_pid_to_str): Enable "process" style ptid string for
target remote.
(remote_supports_multi_process): Remove restriction on target
remote mode.
Don Breazeal [Mon, 14 Dec 2015 19:18:05 +0000 (11:18 -0800)]
Target remote mode fork and exec test updates
This patch updates tests for fork and exec events in target remote mode.
In the majority of cases this was a simple matter of removing some code
that disabled the test for target remote. In a few cases the test needed
to be disabled; in those cases the gdb_protocol was checked instead of
using the [is_remote target] etc.
In a couple of cases we needed to use clean_restart, since target remote
doesn't support the run command, and in one case we had to modify an expect
expression to allow for a "multiprocess-style" ptid.
Tested with the patch that implemented target remote mode fork and exec
event support.
gdb/testsuite/ChangeLog:
* gdb.base/execl-update-breakpoints.exp (main): Enable for target
remote.
* gdb.base/foll-exec-mode.exp (main): Disable for target remote.
* gdb.base/foll-exec.exp (main): Enable for target remote.
* gdb.base/foll-fork.exp (main): Likewise.
* gdb.base/foll-vfork.exp (main): Likewise.
* gdb.base/multi-forks.exp (main): Likewise, and use clean_restart.
(proc continue_to_exit_bp_loc): Use clean_restart.
* gdb.base/pie-execl.exp (main): Disable for target remote.
* gdb.base/watch-vfork.exp (main): Enable for target remote.
* gdb.mi/mi-nsthrexec.exp (main): Likewise.
* gdb.threads/execl.exp (main): Likewise.
* gdb.threads/fork-child-threads.exp (main): Likewise.
* gdb.threads/fork-plus-threads.exp (main): Disable for target
remote.
* gdb.threads/fork-thread-pending.exp (main): Enable for target
remote.
* gdb.threads/linux-dp.exp (check_philosopher_stack): Allow
pid.tid style ptids, instead of just tid.
* gdb.threads/thread-execl.exp (main): Enable for target remote.
* gdb.threads/watchpoint-fork.exp (main): Likewise.
* gdb.trace/report.exp (use_collected_data): Allow pid.tid style
ptids, instead of just tid.
Matthew Wahab [Mon, 14 Dec 2015 17:46:21 +0000 (17:46 +0000)]
[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Hd>, <Hs>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
by immediate instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD scalar shift by immediate group.
Change-Id: I40506496f52dd96909e7344f243b38a1870df7ff
Matthew Wahab [Mon, 14 Dec 2015 17:40:03 +0000 (17:40 +0000)]
[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.
The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.
The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, #<imm>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_VSHIFT_H): New.
(aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
and fcvtzu to the Adv.SIMD shift by immediate group.
Change-Id: I3480f63883d54db46562573185da6982f2365ee8
Matthew Wahab [Mon, 14 Dec 2015 17:35:47 +0000 (17:35 +0000)]
[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
Pairwise instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_PAIR_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345
Matthew Wahab [Mon, 14 Dec 2015 17:27:52 +0000 (17:27 +0000)]
[AArch64][PATCH 11/14] Add support for the 2H vector type.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.
The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.
include/opcode/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (enum aarch64_opnd_qualifier): Add
AARCH64_OPND_QLF_V_2H.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
Matthew Wahab [Mon, 14 Dec 2015 17:25:35 +0000 (17:25 +0000)]
[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.
The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.
The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.
This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.
gas/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
qualifier from per-type base and offet.
Change-Id: I95535864e342a6dec46f69d2696b3900a008f0b1
Matthew Wahab [Mon, 14 Dec 2015 17:22:36 +0000 (17:22 +0000)]
[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.
Change-Id: Ic66af44c494e6a53fb1cf01c372cdc62d12643e2
Matthew Wahab [Mon, 14 Dec 2015 17:16:50 +0000 (17:16 +0000)]
[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.
The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.
The general form for these instructions is
<OP> <Hd>, <V>.<T>
where T is 4h or 8h.
The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
instructions.
* gas/aarch64/illegal.d: Update expected output.
* gas/aarch64/illegal.s: Replace test for illegal use of 'h'
specifier.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_XLANES_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
fminnmv, fminv to the Adv.SIMD across lanes group.
Change-Id: Ib9a47e867f55e0272c2446eb7e16837503d2f94c
Matthew Wahab [Mon, 14 Dec 2015 17:07:51 +0000 (17:07 +0000)]
[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <Hd>, <Hs>, <V>.h[<idx>]
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
fmls, fmul and fmulx to the scalar indexed element group.
Change-Id: I6a4ee20a9ae1019b89d0fd05da55222f267c5627
Matthew Wahab [Mon, 14 Dec 2015 17:01:56 +0000 (17:01 +0000)]
[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.
The instructions added are: FMLA, FMLS, FMUL and FMULX.
The general form for these instructions is
<OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
where T is 4h or 8h
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_ELEMENT_FP_H): New.
(aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
fmulx to the vector indexed element group.
Change-Id: Ib70cd4eaa6ea2938f84ac41f31d72644dbb0ceb4
Matthew Wahab [Mon, 14 Dec 2015 16:57:04 +0000 (16:57 +0000)]
[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.
The general form for these instructions is
<OP> <Hd>, <Hs>
or
<OP> <Hd>, <Hs>, #0.0
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
(QL_S_2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
fcvtzu and frsqrte to the scalar two register misc. group.
Change-Id: I19b25baae33027ce1bade68cc8dc47a4321d045c
Matthew Wahab [Mon, 14 Dec 2015 16:54:38 +0000 (16:54 +0000)]
[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.
The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V2SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of frintn, frintm,
fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
and fsqrt to the vector register misc. group.
Change-Id: I0267511a7f7ea14247504d29fe4752e84c9af9ad
Matthew Wahab [Mon, 14 Dec 2015 16:49:34 +0000 (16:49 +0000)]
[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.
The general form for these instructions is
<OP> <Hd>, <Hs>, <Hm>
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
instructions.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
facgt to the scalar three same group.
Change-Id: I155eb8d7c1e9a7c89d691d7e4aae83be51ff1238
Matthew Wahab [Mon, 14 Dec 2015 16:44:02 +0000 (16:44 +0000)]
[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.
The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.
The general form for these instructions is
<OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
where T is 4h or 8h.
gas/testsuite/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: New.
* gas/aarch64/advsimd-fp16.s: New.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_V3SAMEH): New.
(aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
fcmgt, facgt and fminp to the vector three same group.
Change-Id: I3f1c5fe82ca73f7a17fe5329cf2b0de03c94328c
Matthew Wahab [Mon, 14 Dec 2015 16:34:47 +0000 (16:34 +0000)]
[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.
The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
Immediate.
This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_simd_f16): New.
(SIMD_F16): New.
Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
Matthew Wahab [Mon, 14 Dec 2015 16:28:46 +0000 (16:28 +0000)]
[AArch64] Fix errors rebasing the ARMv8.2 AT and system registers patch
A mistake with rebasing the ARMv8.2 AT instruction patch left this part
+ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
+ if ((reg->value == CPENS (0, C7, C9, 0)
+ || reg->value == CPENS (0, C7, C9, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
in aarch64_pstatefield_supported_p rather than in
aarch64_sys_ins_reg_supported_p, where it was supposed to be.
The patch adding support for id_aa64mmfr2_el1, also had the effect of
removing a conditional branch in aarch64_sys_reg_supported_p.
The effect of both of these is to suppress an error if some ARMv8.2
system registers are used with the wrong -march settings.
This patch fixes these mistakes.
opcodes/
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
removed statement.
(aarch64_pstatefield_supported_p): Move feature checks for AT
registers ..
(aarch64_sys_ins_reg_supported_p): .. to here.
Change-Id: I48783d118eaaf0f3312e8b08a8340ef7af4e36a4
Andrew Burgess [Fri, 11 Dec 2015 17:06:35 +0000 (17:06 +0000)]
gdb: Use TYPE_LENGTH macro
Fixes a couple of places where we access the length field of the type
structure directly, rather than using the TYPE_LENGTH macro.
gdb/ChangeLog:
* i386-tdep.c (i386_mpx_info_bounds): Use TYPE_LENGTH.
(i386_mpx_set_bounds): Likewise.
* solib-darwin.c (darwin_load_image_infos): Likewise.
(darwin_solib_read_all_image_info_addr): Likewise.
Jan Beulich [Mon, 14 Dec 2015 08:25:10 +0000 (09:25 +0100)]
gas: free allocated symbol name in .cfi_label handling
I've just noticed this further oversights of the original commit.
Jan Beulich [Mon, 14 Dec 2015 08:24:04 +0000 (09:24 +0100)]
nm: basic COFF symbol type support for SysV-style symbol table dumping
GDB Administrator [Mon, 14 Dec 2015 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Cary Coutant [Sun, 13 Dec 2015 22:04:24 +0000 (14:04 -0800)]
Remove const from return type of get_output_view.
gold/
* object.h (Object::get_output_view): remove const from return type.
(Object::do_get_output_view): Likewise.
(Sized_relobj_file::do_get_output_view): Likewise.
* reloc.cc (Sized_relobj_file::do_get_output_view): Likewise.
GDB Administrator [Sun, 13 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
Alan Modra [Sat, 12 Dec 2015 10:58:27 +0000 (21:28 +1030)]
Fix SH gas testsuite invalid assembly exposed by
ec9ab52c
* gas/sh/tlsd.s: Use .tdata not .tbss.
* gas/sh/tlsnopic.s: Likewise.
Alan Modra [Sat, 12 Dec 2015 06:56:33 +0000 (17:26 +1030)]
Enable 2 operand form of powerpc mfcr with -many
This is a workaround for a gcc bug.
PR 19359
* ppc-opc.c (insert_fxm): Remove "ignored" from error message.
(powerpc_opcodes): Remove single-operand mfcr.
GDB Administrator [Sat, 12 Dec 2015 00:00:08 +0000 (00:00 +0000)]
Automatic date update in version.in
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