Olof Johansson [Tue, 20 May 2014 06:29:46 +0000 (23:29 -0700)]
Merge tag 'renesas-soc-cleanup-for-v3.16' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC soc-cleanup Updates for v3.16" from Simon Horman:
r8a7791 (R-Car H2) SoC and its Koelsch board and,
r8a7740 (R-Mobile A1) SoC and its Armadillo800eva board
* Set CPU clock frequency from OF nodes
* tag 'renesas-soc-cleanup-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Set clock frequency in HZ from OF nodes
ARM: shmobile: Use shmobile_init_late() on r8a7740
ARM: shmobile: Remove unused r8a7791_init_early()
ARM: shmobile: Use r8a7791 DT CPU Frequency for Koelsch
ARM: shmobile: Use r8a7791 DT CPU Frequency in common case
ARM: shmobile: Remove unused r8a7740_init_delay()
ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT Ref
ARM: shmobile: Use r8a7740 DT CPU Frequency in common case
ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTS
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 20 May 2014 06:29:24 +0000 (23:29 -0700)]
Merge tag 'renesas-clock2-for-v3.16' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Clock Updates for v3.16" from
Simon Horman:
r8a7791 (R-Car M2) SoC
* Correct SYS-DMAC clock defines
r8a7740 (R-Mobile A1) SoC
* Correct name of DT Ethernet clock
* tag 'renesas-clock2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: Correct SYS-DMAC clock defines
ARM: shmobile: r8a7740: Correct name of DT Ethernet clock
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 20 May 2014 05:27:05 +0000 (22:27 -0700)]
Merge branch 'cleanup/kconfig' into next/soc
Bring in the cleanup branch due to conflicts in new additions. Should really
have been the base before the other branch, but this way works too.
* cleanup/kconfig:
ARM: qcom: clean-up unneeded kconfig selects
ARM: bcm: clean-up unneeded kconfig selects
ARM: mvebu: clean-up unneeded kconfig selects
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 20 May 2014 04:59:55 +0000 (21:59 -0700)]
Merge tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu into next/soc
Merge "ARM: mvebu: SoC changes for v3.16" from Jason Cooper:
mvebu SoC changes for v3.16
- Armada 375/38x coherency support
- Armada 375/38x SMP support
- mvebu PMSU and CPU reset support
- Armada 370/XP cpuidle support
- kirkwood remove platform init of audio device
- small fixes and cleanup for new SoC (375/38x)
Note:
- due to complex deps, cpuidle changes Acked by appropriate maintainer for
going though arm-soc tree.
* tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu: (46 commits)
ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
ARM: mvebu: conditionalize Armada 375 coherency workaround
ARM: mvebu: conditionalize Armada 375 SMP workaround
ARM: mvebu: add Armada 375 A0 revision definition
ARM: mvebu: initialize mvebu-soc-id earlier
ARM: mvebu: fix thermal quirk SoC revision check
ARM: Kirkwood: t5325: Remove platform device to instantiate audio
ARM: Kirkwood: Remove platform driver for codec
ARM: mvebu: Add thermal quirk for the Armada 375 DB board
ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
ARM: mvebu: Register notifier callback for the cpuidle transition
ARM: mvebu: refine which files are build in mach-mvebu
ARM: mvebu: Add the PMSU related part of the cpu idle functions
ARM: mvebu: Allow to power down L2 cache controller in idle mode
ARM: mvebu: Low level function to disable HW coherency support
ARM: mvebu: Split low level functions to manipulate HW coherency
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Tue, 20 May 2014 04:56:38 +0000 (21:56 -0700)]
Merge tag 'mvebu-soc-orion5x-3.16' of git://git.infradead.org/linux-mvebu into next/soc
Merge "ARM: mvebu: SoC orion5x DT conversion for v3.16" from Jason Cooper:
mvebu SoC orion5x DT conversion for v3.16
- orion5x
- convert to DT
* tag 'mvebu-soc-orion5x-3.16' of git://git.infradead.org/linux-mvebu: (29 commits)
ARM: orion: remove no longer needed gpio DT code
ARM: orion: remove no longer needed DT IRQ code
ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree
ARM: orion5x: convert d2net to Device Tree
ARM: orion5x: convert RD-
88F5182 to Device Tree
ARM: orion5x: remove unneeded code for edmini_v2
ARM: orion5x: keep TODO list in edmini_v2 DT
ARM: orion5x: use DT to describe NOR on edmini_v2
ARM: orion5x: use DT to describe EHCI on edmini_v2
ARM: orion5x: use DT to describe I2C devices on edmini_v2
ARM: orion5x: convert edmini_v2 to DT pinctrl
ARM: orion5x: add standard pinctrl configs for sata0 and sata1
ARM: orion5x: add Device Bus description at SoC level
ARM: orion5x: update I2C description at SoC level
ARM: orion5x: enable pinctrl driver at SoC level
ARM: orion5x: switch to DT interrupts and timer
ARM: orion: switch to a per-platform handle_irq() function
ARM: orion5x: convert to use 'clocks' property for UART controllers
ARM: orion5x: switch to use the clock driver for DT platforms
ARM: orion5x: add interrupt for Ethernet in Device Tree
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Fri, 16 May 2014 23:22:41 +0000 (16:22 -0700)]
Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/soc
Merge "at91: cleanup for 3.16 #1" from Nicolas Ferre:
First cleanup series for 3.15
- localize GPIO header in mach-at91 directory
- big update on the CCF front with main and slow clocks
- a cleanup of ADC and touchscreen driver with unification on IIO and
removal of old driver
[olof: Most of this branch is new code, not cleanups, so I'm merging this into
the SoC branch in spite of the branch name]
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91: (28 commits)
ARM: at91/dt: at91-cosino_mega2560 remove useless tsadcc node
ARM: at91: remove atmel_tsadcc platform_data
Input: atmel_tsadcc: remove driver
ARM: at91: remove atmel_tsadcc from sama5_defconfig
ARM: at91: sam9rl: switch from atmel_tsadcc to at91_adc
ARM: at91: sam9g45: switch from atmel_tsadcc to at91_adc
ARM: at91: sam9rlek add touchscreen support through at91_adc
ARM: at91: sam9rl: add at91_adc to support adc and touchscreen
iio: adc: at91: add sam9rl support
iio: adc: at91: remove unused include from include/mach
ARM: at91: sam9m10g45ek: Add touchscreen support through at91_adc
iio: adc: at91_adc: Add support for touchscreens without TSMR
iio: adc: at91: cleanup platform_data
ARM: at91: sam9260: remove unused platform_data
ARM: at91: sam9g45: remove unused platform_data
ARM: at91/dt: define sam9rlek crystal frequencies
ARM: at91/dt: move at91sam9rl SoC to the new slow/main clock models
ARM: at91/dt: define main xtal frequency of the at91sam9261ek board
ARM: at91/dt: move at91sam9261 SoC to the new main clock model
ARM: at91/dt: add xtal frequencies to sama5d3 xplained board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Simon Horman [Tue, 13 May 2014 06:59:18 +0000 (15:59 +0900)]
ARM: shmobile: Set clock frequency in HZ from OF nodes
shmobile_init_delay() looks for OF "clock-frequency" to determine
the delay which is set by calling shmobile_setup_delay().
Unfortunately this seems to be incorrect in detail as
"clock-frequency" node values are in HZ whereas the frequency
argument to shmobile_setup_delay() is in MHz.
Provide a variant of shmobile_setup_delay() that accepts HZ to
correct this problem.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Sun, 11 May 2014 23:10:50 +0000 (08:10 +0900)]
ARM: shmobile: Use shmobile_init_late() on r8a7740
Hook up ->init_late for r8a7740 to initialize Suspend-to-RAM
and CPUIdle in case of C-code less board support for r8a7740.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Mon, 12 May 2014 18:49:33 +0000 (20:49 +0200)]
ARM: shmobile: r8a7791: Correct SYS-DMAC clock defines
R-Car M2 has two MSTP bits for SYS-DMAC, not one.
Also bring the naming in sync with the documentation.
This issue was introduced in v3.14, in commit
4d8864c9e94ec727f1c675b9f6921525c360334b ("ARM: shmobile: r8a7791: Add
clock index macros for DT sources").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Sun, 11 May 2014 23:25:37 +0000 (08:25 +0900)]
ARM: shmobile: Remove unused r8a7791_init_early()
Remove the now unused r8a7791_init_early() function.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Sun, 11 May 2014 23:25:27 +0000 (08:25 +0900)]
ARM: shmobile: Use r8a7791 DT CPU Frequency for Koelsch
Convert the Koelsch board support to use shmobile_init_delay()
to be able to migrate away from per-SoC delay setup functions.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Sun, 11 May 2014 23:25:18 +0000 (08:25 +0900)]
ARM: shmobile: Use r8a7791 DT CPU Frequency in common case
Convert the common C-code-less r8a7791 DT board support
to use shmobile_init_delay() to be able to migrate away
from per-SoC delay setup functions.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 7 May 2014 23:32:56 +0000 (08:32 +0900)]
ARM: shmobile: Remove unused r8a7740_init_delay()
Remove the now unused r8a7740_init_delay() function.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Tested-by: Geert Uytterhoeven <geert@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 7 May 2014 23:32:47 +0000 (08:32 +0900)]
ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT Ref
Convert the Armadillo r8a7740 DT reference board support
to use shmobile_init_delay() to be able to migrate away
from per-SoC delay setup functions.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Tested-by: Geert Uytterhoeven <geert@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 7 May 2014 23:32:38 +0000 (08:32 +0900)]
ARM: shmobile: Use r8a7740 DT CPU Frequency in common case
Convert the common C-code-less r8a7740 DT board support
to use shmobile_init_delay() to be able to migrate away
from per-SoC delay setup functions.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Tested-by: Geert Uytterhoeven <geert@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 7 May 2014 23:32:29 +0000 (08:32 +0900)]
ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTS
Add 800 MHz to the r8a7740 DTS to describe the maximum CPU frequency.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Tested-by: Geert Uytterhoeven <geert@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Geert Uytterhoeven [Wed, 7 May 2014 20:32:28 +0000 (22:32 +0200)]
ARM: shmobile: r8a7740: Correct name of DT Ethernet clock
The preferred node name in DT for an Ethernet device is "ethernet".
"sh-eth" was used in preliminary and incomplete bindings.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Vincent Stehlé [Tue, 6 May 2014 20:23:02 +0000 (22:23 +0200)]
ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler
flags are for ARMv6, and we will get:
/tmp/ccwDEzd0.s: Assembler messages:
/tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb '
/tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb '
/tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb '
/tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb '
make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1
Fix this in a similar manner than done previously in commit
72533b77d30c2be02672e26b5dde1263d7b4c2be, by specifying ARMv7 flags for pmsu.o.
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Link: https://lkml.kernel.org/r/1399407782-29091-1-git-send-email-vincent.stehle@laposte.net
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 5 May 2014 15:05:26 +0000 (17:05 +0200)]
ARM: mvebu: conditionalize Armada 375 coherency workaround
The Armada 375 coherency workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 5 May 2014 15:05:25 +0000 (17:05 +0200)]
ARM: mvebu: conditionalize Armada 375 SMP workaround
The Armada 375 SMP workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.
Note that the initialization of the SMP workaround is delayed from
->smp_prepare_cpus() to ->smp_boot_secondary() because when
->smp_prepare_cpus() is called, the early initcalls have not be
called, so the mvebu-soc-id mechanism is not operational. Since the
workaround is anyway not needed before the secondary CPU is started,
we can delay its implementation until the ->smp_boot_secondary() call.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 5 May 2014 15:05:24 +0000 (17:05 +0200)]
ARM: mvebu: add Armada 375 A0 revision definition
Now that we have access to Armada 375 A0 platforms, we can add the
corresponding revision definition in mvebu-soc-id.h.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 5 May 2014 15:05:23 +0000 (17:05 +0200)]
ARM: mvebu: initialize mvebu-soc-id earlier
Currently, the mvebu-soc-id logic is initialized through a
core_initcall(). However, we will soon need to know the SoC revision
before booting secondary CPUs, because a workaround affects Armada 375
Z1 steppings, but should not be applied on Armada 375 A0 steppings.
Unfortunately, core_initcall() are called way too late compared to the
SMP initialization. Therefore, the mvebu-soc-id initialization is move
to an early_initcall(), which is called before the SMP initialization.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 5 May 2014 15:05:22 +0000 (17:05 +0200)]
ARM: mvebu: fix thermal quirk SoC revision check
In commit
54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add
thermal quirk for the Armada 375 DB board'), a check on the Armada SoC
revision was added to decide whether a quirk for the thermal device
should be applied or not.
However, the quirk implementation has a bug: it assumes
mvebu_get_soc_id() returns true on success, but it returns
0. Therefore, the condition:
if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV)
is always false (as long as mvebu-soc-id is properly initialized). As
a consequence, the quirk is always applied, even on A0 steppings, for
which the quirk should not be applied.
This was spotted by testing the thermal driver on Armada 375 A0, which
Ezequiel could not do since he does not have access to the A0 revision
of the SoC for the moment.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board')
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Andrew Lunn [Sat, 3 May 2014 18:30:16 +0000 (20:30 +0200)]
ARM: Kirkwood: t5325: Remove platform device to instantiate audio
Remove platform device instantiating of the audio, which results in
board-t5325.c being removed. A DT node will be added to take its
place.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399141819-23924-7-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Andrew Lunn [Sat, 3 May 2014 18:30:12 +0000 (20:30 +0200)]
ARM: Kirkwood: Remove platform driver for codec
Remove the platform driver and platform data for the audio codec.
A DT node will replace it.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399141819-23924-3-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Ezequiel Garcia [Thu, 24 Apr 2014 20:23:22 +0000 (17:23 -0300)]
ARM: mvebu: Add thermal quirk for the Armada 375 DB board
The initial release of the Armada 375 DB board has an Armada 375
Z1 stepping silicon. This commit introduces a quirk that allows
to workaround a series of issues with the thermal sensor in this
stepping, but updating the devicetree:
* Updates the compatible string for the thermal, so the driver
can perform a specific initialization of the sensor.
* Moves the offset of the thermal control register. This quirk
allows to specifiy the correct (A0 stepping) offset in the
devicetree.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Ezequiel Garcia [Thu, 24 Apr 2014 11:34:36 +0000 (08:34 -0300)]
ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
HAVE_ARM_TWD depends on SMP, so we should only select it if
SMP is enabled, as the others platforms do.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398339276-5754-1-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Sat, 19 Apr 2014 16:32:50 +0000 (18:32 +0200)]
ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
The name of the two parameters of mvebu_get_soc_id were inverted. This
patch fix it in order to have a more readable code.
Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Sat, 19 Apr 2014 16:32:49 +0000 (18:32 +0200)]
ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
l2x0_of_init function is always defined
arch/arm/include/asm/hardware/cache-l2x0.h: in case of
CONFIG_CACHE_L2X0 is not selected then a placeholder is defined.
Then there is no need to have ifdef around l2x0_of_init.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:14 +0000 (17:10 +0200)]
ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
The cpuidle is a platform driver so we register the device just after
the initialization of the board in an arch_initcall.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-12-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:13 +0000 (17:10 +0200)]
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
Add the wfi, cpu idle and cpu deep idle power states support for the
Armada XP SoCs.
All the latencies and the power consumption values used at the
"armada_370_xp_idle_driver" structure are preliminary and will be
modified in the future after running some measurements and analysis.
Based on the work of Nadav Haklai.
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-11-git-send-email-gregory.clement@free-electrons.com
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:12 +0000 (17:10 +0200)]
ARM: mvebu: Register notifier callback for the cpuidle transition
In order to have well encapsulated code, we use notifier callbacks for
CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-10-git-send-email-gregory.clement@free-electrons.com
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 28 Apr 2014 18:20:39 +0000 (20:20 +0200)]
ARM: mvebu: refine which files are build in mach-mvebu
Following the integration into mach-mvebu of the Kirkwood ARMv5
support, we need to be more careful about which files get built. For
example, the pmsu.c file now calls wfi(), which only exists on ARMv7
platforms.
Therefore, this commit changes mach-mvebu/Makefile to build the Armada
370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is
enabled.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398709239-6126-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:11 +0000 (17:10 +0200)]
ARM: mvebu: Add the PMSU related part of the cpu idle functions
The cpu idle support will need to access to Power Management Service
Unit. This commit adds the architecture related functions that will be
used in the idle path of the cpuidle driver.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-9-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:10 +0000 (17:10 +0200)]
ARM: mvebu: Allow to power down L2 cache controller in idle mode
This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.
This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-8-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:09 +0000 (17:10 +0200)]
ARM: mvebu: Low level function to disable HW coherency support
When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:08 +0000 (17:10 +0200)]
ARM: mvebu: Split low level functions to manipulate HW coherency
Actually enabling coherency and adding a CPU on a SMP group are two
different operations which can be done separately. This patch splits
this in two functions.
Moreover as they use common pattern, this patch also creates local low
level functions (ll_get_coherency_base and ll_get_cpuid) to be used by
the exposed functions (ll_add_cpu_to_smp_group and
ll_enable_coherency)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:07 +0000 (17:10 +0200)]
ARM: mvebu: Remove the unused argument of set_cpu_coherent()
set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:06 +0000 (17:10 +0200)]
ARM: mvebu: ll_set_cpu_coherent always uses the current CPU
ll_set_cpu_coherent is always used on the current CPU, so instead of
passing the CPU id as argument, ll_set_cpu_coherent() can find it by
itself.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 15:10:05 +0000 (17:10 +0200)]
ARM: mvebu: remove the address parameter for ll_set_cpu_coherent
In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.
This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:04 +0000 (15:54 +0200)]
ARM: mvebu: add Armada 38x compatible string to pmsu
Since the Armada 38x PMSU registers are slightly different than the
Armada 370/XP PMSU ones, we introduce a new compatible string
"armada-380-pmsu" in the PMSU driver. These differences are not
visible for the current usage of the PMSU, but they might become
visible in the future.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 13:54:06 +0000 (15:54 +0200)]
ARM: mvebu: add workaround for SMP support for Armada 375 stepping Z1
Due to internal bootrom issue, CPU[1] initial jump code (four
instructions) should be placed in SRAM memory of the SoC. In order to
achieve this, we have to unmap the BootROM and at some specific
location where the BootROM was place, create a specific MBus window
for the SRAM. This SRAM is initialized with a few instructions of code
that allows to jump into the real secondary CPU boot address.
This workaround will most likely be disabled when newer steppings of
the Armada 375 will be made available, in which case a dynamic test
based on mvebu-soc-id will be added.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 13:54:05 +0000 (15:54 +0200)]
ARM: mvebu: add SMP support for Armada 375 and Armada 38x
This commit adds the SMP support for Armada 375 and Armada 38x. It
turns out that the SMP logic for both of these SOCs are fairly
similar, the only differences being:
* A different method to set the secondary CPU boot address
* An Armada 375 specific workaround needed for the early Z1 stepping,
added by the following patch.
Other than that, the patch is fairly straightforward and adds the
usual platsmp and headsmp code, defining the smp_operations structure
that is referenced from the DT_MACHINE structures.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Gregory CLEMENT [Mon, 14 Apr 2014 13:54:03 +0000 (15:54 +0200)]
ARM: mvebu: add function to set the resume boot address for Armada 375
In order to boot the secondary CPUs on Armada 375, we need to set the
boot address of these CPUs, through a register part of the System
Controller (this deviates from the Armada XP design, where the boot
address was defined using a register part of the PMSU unit).
Therefore, this commit adds a new helper function in the System
Controller driver to set the secondary CPU boot address.
Moreover, it moves the System Controller initialization as an
early_initcall(), since arch_initcall() is too late for an SMP-related
initialization.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Jason Cooper [Thu, 8 May 2014 16:07:56 +0000 (16:07 +0000)]
Merge branch 'mvebu/irqchip' into mvebu/soc
Thomas Petazzoni [Mon, 14 Apr 2014 13:53:59 +0000 (15:53 +0200)]
ARM: mvebu: use CPU_METHOD_OF_DECLARE for SMP on Armada XP
This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 14 Apr 2014 13:53:58 +0000 (15:53 +0200)]
ARM: mvebu: move Armada XP specific SMP initialization to platsmp.c
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets
the boot address of a secondary CPUs and deasserts the reset. However,
the Armada 375 needs a slightly different logic, so it makes more
sense to move this code into the Armada XP specific platsmp.c.
In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function
is exported. It will be needed for both the Armada XP and Armada 38x
SMP implementations.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Jason Cooper [Thu, 8 May 2014 16:06:57 +0000 (16:06 +0000)]
Merge branch 'mvebu/soc-pmsu' into mvebu/soc
Sebastian Hesselbarth [Mon, 28 Apr 2014 21:12:08 +0000 (23:12 +0200)]
irqchip: orion: Reverse irq handling priority
Non-DT irq handlers were working through irq causes from most-significant
to least-significant bit, while DT irqchip driver does it the other way
round. This revealed some more HW issues on Kirkwood peripheral IP, where
spurious sdio irqs can happen although irqs are masked.
Also, the generated binaries show that original non-DT order compared
to DT order save two instructions for each bit count check:
irqchip DT order with ffs():
60:
e3a06001 mov r6, #1
64:
e2643000 rsb r3, r4, #0
68:
e0033004 and r3, r3, r4
6c:
e16f3f13 clz r3, r3
70:
e263301f rsb r3, r3, #31
74:
e1c44316 bic r4, r4, r6, lsl r3
78:
e5971004 ldr r1, [r7, #4]
Original non-DT order with fls():
60:
e3a07001 mov r7, #1
64:
e16f3f14 clz r3, r4
68:
e263301f rsb r3, r3, #31
6c:
e1c44317 bic r4, r4, r7, lsl r3
70:
e5951004 ldr r1, [r5, #4]
Therefore, reverse irq bit handling back to original order by replacing
ffs() with fls().
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1398719528-23607-1-git-send-email-sebastian.hesselbarth@gmail.com
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:02 +0000 (15:54 +0200)]
irqchip: irq-armada-370-xp: Use cpu notifier to initialize secondary CPUs
Some irqchip initialization must be done on secondary CPUs. On mvebu
platforms, this is currently achieved by having the
arch/arm/mach-mvebu/platsmp.c code directly call into a function
exported by the irqchip driver, which isn't really nice.
This commit changes this by using the same solution as the one used in
the GIC driver: the irqchip driver registers a CPU notifier, which is
used to do the secondary CPU IRQ initialization. This way, the irqchip
driver is completely autonomous, and the function no longer needs to
be exposed from the irqchip driver to the SoC code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Thomas Petazzoni [Mon, 14 Apr 2014 13:54:01 +0000 (15:54 +0200)]
irqchip: irq-armada-370-xp: Do the set_smp_cross_call() in the driver
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the
set_smp_cross_call() to register the IPI-triggering function, it makes
more sense to do exactly what the GIC driver is doing: let the irqchip
driver do it. This way, it avoids having to expose the
armada_mpic_send_doorbell() function between the irqchip driver and
the SoC code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:10 +0000 (12:28 +0200)]
ARM: at91/dt: at91-cosino_mega2560 remove useless tsadcc node
The tsadcc node is useless as it doesn't refer to anything and the touchscreen
is handled by the adc0 node.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rodolfo Giometti <giometti@linux.it>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:09 +0000 (12:28 +0200)]
ARM: at91: remove atmel_tsadcc platform_data
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:08 +0000 (12:28 +0200)]
Input: atmel_tsadcc: remove driver
The atmel_tsadcc driver is not used anymore, it has been replaced by at91_adc so
remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:07 +0000 (12:28 +0200)]
ARM: at91: remove atmel_tsadcc from sama5_defconfig
atmel_tsadcc has been removed, stop selecting it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:06 +0000 (12:28 +0200)]
ARM: at91: sam9rl: switch from atmel_tsadcc to at91_adc
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc
does. Completely switch to at91_adc and remove the tsadcc platform_data for
at91sam9rl and at91sam9rl based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:05 +0000 (12:28 +0200)]
ARM: at91: sam9g45: switch from atmel_tsadcc to at91_adc
atmel_tsadcc is not allowing to use the remaining ADC channels while at91_adc
does. Completely switch to at91_adc and remove the tsadcc platform_data for
at91sam9g45 and at91sam9g45 based boards.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:04 +0000 (12:28 +0200)]
ARM: at91: sam9rlek add touchscreen support through at91_adc
at91_adc now supports reading a touchscreen for ADCs without a TSMR register.
Enable touchscreen support through at91_adc. This allows to use both a
touchscreen and the remaining ADC channel at the same time.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:03 +0000 (12:28 +0200)]
ARM: at91: sam9rl: add at91_adc to support adc and touchscreen
The ADC clock needs to be defined to enable the at91_adc driver. It is defined
to the same speed that is used for atmel_tsadcc.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:02 +0000 (12:28 +0200)]
iio: adc: at91: add sam9rl support
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:01 +0000 (12:28 +0200)]
iio: adc: at91: remove unused include from include/mach
That include file is now only used by the at91_adc driver, remove it from
include/mach for better driver separation.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:28:00 +0000 (12:28 +0200)]
ARM: at91: sam9m10g45ek: Add touchscreen support through at91_adc
at91_adc now supports reading a touchscreen for ADCs without a TSMR register.
Enable touchscreen support through at91_adc. This allows to use both a
touchscreen and the remaining ADC channel at the same time.
Also, lower the clock for the ADC as it allows to have more stable reads and
this is the speed used by atmel_tsadcc.
It lowers the maximum throughput rate from 440000 samples per second to 12958
samples per second. It shouldn't be an issue as the CPU is not able to keep up
reading samples at that frequency.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:27:59 +0000 (12:27 +0200)]
iio: adc: at91_adc: Add support for touchscreens without TSMR
Old ADCs, as present on the sam9rl and the sam9g45 don't have a TSMR register
and the touchscreen support should be handled differently.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:27:58 +0000 (12:27 +0200)]
iio: adc: at91: cleanup platform_data
num_channels and registers are not used anymore since they are defined inside
the driver and assigned by matching the id_table.
Also, struct at91_adc_reg_desc is now only used inside the driver.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:27:57 +0000 (12:27 +0200)]
ARM: at91: sam9260: remove unused platform_data
num_channels and registers are not used anymore since they are defined inside
the at91_adc driver and assigned by matching the id_table.
Also, remove the mach/at91_adc.h include that is not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Alexandre Belloni [Tue, 15 Apr 2014 10:27:56 +0000 (12:27 +0200)]
ARM: at91: sam9g45: remove unused platform_data
num_channels and registers are not used anymore since they are defined inside
the at91_adc driver and assigned by matching the id_table.
Also, remove the mach/at91_adc.h include that is not necessary anymore.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:40 +0000 (15:12 +0200)]
ARM: at91/dt: define sam9rlek crystal frequencies
Define at91sam9rlek crystal frequencies.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:39 +0000 (15:12 +0200)]
ARM: at91/dt: move at91sam9rl SoC to the new slow/main clock models
Move at91sam9rl SoC to the new main/slow clock model.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:38 +0000 (15:12 +0200)]
ARM: at91/dt: define main xtal frequency of the at91sam9261ek board
Define at91sam9261ek main crystal frequency.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Jean-Jacques HIBLOT <jjhiblot@traphandler.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:37 +0000 (15:12 +0200)]
ARM: at91/dt: move at91sam9261 SoC to the new main clock model
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Jean-Jacques HIBLOT <jjhiblot@traphandler.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:36 +0000 (15:12 +0200)]
ARM: at91/dt: add xtal frequencies to sama5d3 xplained board
Define crystal properties of sama5d3 xplained board.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:35 +0000 (15:12 +0200)]
ARM: at91/dt: add xtal frequencies to sama5d3xcm boards
Define crystal frequencies of sama5d3xcm boards.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:34 +0000 (15:12 +0200)]
ARM: at91/dt: move sama5d3 SoC to the new main/slow clk model
Replace the old main and clk definitions (fixed rate clk) by the new main and
slow clk subtree definition (ck = mux(rc_osc, osc)).
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:33 +0000 (15:12 +0200)]
clk: at91: add slow clk documentation
Add slow clk, and slow oscillators documentation.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Wed, 7 May 2014 16:02:15 +0000 (18:02 +0200)]
clk: at91: add slow clks driver
AT91 slow clk is a clk multiplexer.
In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can
choose among 2 sources: an internal RC oscillator circuit and an oscillator
using an external crystal.
In other Socs (sam9260 family) the multiplexer source is hardcoded with
the OSCSEL signal.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Tue, 22 Apr 2014 13:12:31 +0000 (15:12 +0200)]
clk: at91: update main clk documentation
Update main clk documentation to match main clk implementation rework.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Boris BREZILLON [Wed, 7 May 2014 16:00:08 +0000 (18:00 +0200)]
clk: at91: rework main clk implementation
AT91 main clk is a clk multiplexer and not a simple fixed rate clk as
currently implemented.
In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can
choose among 2 sources: an internal RC oscillator circuit and an
oscillator using an external crystal.
In other Socs (sam9260, rm9200 families) the multiplexer source is
hardcoded to the external crystal oscillator.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Linus Walleij [Thu, 27 Mar 2014 13:18:51 +0000 (14:18 +0100)]
ARM: at91: localize GPIO header
This moves the <mach/gpio.h> header in the AT91 platform down
into the machine directory and removes the reliance on
MACH_NEED_GPIO_H from the AT91.
This does not move the platform to GENERIC_GPIO but localize
the remaining work to be done for this to the mach-at91
folder.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[nicolas.ferre@atmel.com: adapt to newer kernel, add rsi-ews board]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Nicolas Ferre [Mon, 14 Apr 2014 08:51:15 +0000 (10:51 +0200)]
ASoC: sam9g20_wm8731: remove useless mach/gpio.h
This include file is about to disapear. In addition it is
useless for this code. So it is time to remove it.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Mark Brown <broonie@linaro.org>
Olof Johansson [Tue, 6 May 2014 01:45:10 +0000 (18:45 -0700)]
Merge tag 'renesas-soc2-for-v3.16' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Updates for v3.16" from Simon
Horman:
Power management code which is only used by
sh7372 (SH-Mobile AP4) based Mackerl board
* Ignore callbacks for subsys generic_pm_domain_data
* tag 'renesas-soc2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Ignore callbacks for subsys generic_pm_domain_data
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Mon, 5 May 2014 20:51:15 +0000 (13:51 -0700)]
Merge tag 'renesas-clock-for-v3.16' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Clock Updates for v3.16" from Simon Horman:
SH Mobile shared clock code
* Introduce shmobile_clk_workaround()
r8a7791 (R-Car M2) SoC
* Rename VSP1_SY clocks to VSP1_S
* Correct the I2C clocks parents
r8a7790 (R-Car H2) SoC
* Remove old style audio clock
* Rename VSP1_(SY|RT) clocks to VSP1_(S|R)
* Fix the I2C clocks parents
r8a7778 (R-Car M1) SoC
* Remove old style audio clock
* tag 'renesas-clock-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: remove old style audio clock
ARM: shmobile: r8a7778: remove old style audio clock
ARM: shmobile: r8a7791: Rename VSP1_SY clocks to VSP1_S
ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)
ARM: shmobile: r8a7791: Fix the I2C clocks parents in legacy code
ARM: shmobile: r8a7790: Fix the I2C clocks parents in legacy code
ARM: shmobile: Introduce shmobile_clk_workaround()
ARM: shmobile: r8a7791: Use rcar_gen2_read_mode_pins() helper
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Mon, 5 May 2014 20:44:24 +0000 (13:44 -0700)]
Merge tag 'renesas-soc-for-v3.16' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v3.16" from Simon Horman:
SH Mobile shared SoC code
* Add shared shmobile_init_delay()
r8a7791 (R-Car M2) and r8a7790 (R-Car H2) SoCs (R-Car Gen2 shared code)
* Cache Mode Monitor Register Value
r8a7791 (R-Car M2) SoC
Check r8a7791 MD21 at SMP boot
r8a7790 (R-Car H2) SoC
* Make use of r8a7790_add_standard_devices()
* Update r8a7791 CPU freq to 1500MHz
r8a7778 (R-Car M1) SoC
* Move "select RENESAS_INTC_IRQPIN" under SoC
emev2 (Emma Mobale EV2) SoC
* Remove legacy EMEV2 SoC support
* tag 'renesas-soc-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7778/bockw: Move "select RENESAS_INTC_IRQPIN" under SoC
ARM: shmobile: Check r8a7791 MD21 at SMP boot
ARM: shmobile: rcar-gen2: Cache Mode Monitor Register Value
ARM: shmobile: Make use of r8a7790_add_standard_devices()
ARM: shmobile: Remove EMEV2 header file
ARM: shmobile: Remove legacy EMEV2 SoC support
ARM: shmobile: Add shared shmobile_init_delay()
ARM: shmobile: Update r8a7791 CPU freq to 1500MHz in C
Signed-off-by: Olof Johansson <olof@lixom.net>
Linus Torvalds [Mon, 5 May 2014 01:14:42 +0000 (18:14 -0700)]
Linux 3.15-rc4
Linus Torvalds [Sun, 4 May 2014 21:36:52 +0000 (14:36 -0700)]
Merge tag 'locks-v3.15-3' of git://git.samba.org/jlayton/linux
Pull file locking change from Jeff Layton:
"Only an email address change to the MAINTAINERS file"
* tag 'locks-v3.15-3' of git://git.samba.org/jlayton/linux:
MAINTAINERS: email address change for Jeff Layton
Linus Torvalds [Sun, 4 May 2014 21:34:50 +0000 (14:34 -0700)]
Merge tag 'arm64-fixes' of git://git./linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
"These are mostly arm64 fixes with an additional arm(64) platform fix
for the initialisation of vexpress clocks (the latter only affecting
arm64; the arch/arm64 code is SoC agnostic and does not rely on early
SoC-specific calls)
- vexpress platform clocks initialisation moved earlier following the
arm64 move of of_clk_init() call in a previous commit
- Default DMA ops changed to non-coherent to preserve compatibility
with 32-bit ARM DT files. The "dma-coherent" property can be used
to explicitly mark a device coherent. The Applied Micro DT file
has been updated to avoid DMA cache maintenance for the X-Gene SATA
controller (the only arm64 related driver with such assumption in
-rc mainline)
- Fixmap correction for earlyprintk
- kern_addr_valid() fix for huge pages"
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
vexpress: Initialise the sysregs before setting up the clocks
arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent
arm64: Use bus notifiers to set per-device coherent DMA ops
arm64: Make default dma_ops to be noncoherent
arm64: fixmap: fix missing sub-page offset for earlyprintk
arm64: Fix for the arm64 kern_addr_valid() function
Linus Torvalds [Sun, 4 May 2014 21:31:51 +0000 (14:31 -0700)]
Merge tag 'scsi-fixes' of git://git./linux/kernel/git/jejb/scsi
Pull SCSI fixes from James Bottomley:
"This is two patches both fixing bugs in drivers (virtio-scsi and
mpt2sas) causing an oops in certain circumstances"
* tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi:
[SCSI] virtio-scsi: Skip setting affinity on uninitialized vq
[SCSI] mpt2sas: Don't disable device twice at suspend.
Catalin Marinas [Mon, 28 Apr 2014 16:08:37 +0000 (17:08 +0100)]
vexpress: Initialise the sysregs before setting up the clocks
Following arm64 commit
bc3ee18a7a57 (arm64: init: Move of_clk_init to
time_init()), vexpress_osc_of_setup() is called via of_clk_init() long
before initcalls are issued. Initialising the vexpress oscillators
requires the vespress sysregs to be already initialised, so this patch
adds an explicit call to vexpress_sysreg_of_early_init() in vexpress
oscillator setup function.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Tested-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Mike Turquette <mturquette@linaro.org>
Catalin Marinas [Fri, 25 Apr 2014 15:39:49 +0000 (16:39 +0100)]
arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent
Since the default DMA ops for arm64 are non-coherent, mark the X-Gene
controller explicitly as dma-coherent to avoid additional cache
maintenance.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Loc Ho <lho@apm.com>
Catalin Marinas [Fri, 25 Apr 2014 14:31:45 +0000 (15:31 +0100)]
arm64: Use bus notifiers to set per-device coherent DMA ops
Recently, the default DMA ops have been changed to non-coherent for
alignment with 32-bit ARM platforms (and DT files). This patch adds bus
notifiers to be able to set the coherent DMA ops (with no cache
maintenance) for devices explicitly marked as coherent via the
"dma-coherent" DT property.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Ritesh Harjani [Wed, 23 Apr 2014 05:29:46 +0000 (06:29 +0100)]
arm64: Make default dma_ops to be noncoherent
Currently arm64 dma_ops is by default made coherent which makes it
opposite in default policy from arm.
Make default dma_ops to be noncoherent (same as arm), as currently there
aren't any dma-capable drivers which assumes coherent ops
Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Marc Zyngier [Mon, 28 Apr 2014 18:50:06 +0000 (19:50 +0100)]
arm64: fixmap: fix missing sub-page offset for earlyprintk
Commit
d57c33c5daa4 (add generic fixmap.h) added (among other
similar things) set_fixmap_io to deal with early ioremap of devices.
More recently, commit
bf4b558eba92 (arm64: add early_ioremap support)
converted the arm64 earlyprintk to use set_fixmap_io. A side effect of
this conversion is that my virtual machines have stopped booting when
I pass "earlyprintk=uart8250-8bit,0x3f8" to the guest kernel.
Turns out that the new earlyprintk code doesn't care at all about
sub-page offsets, and just assumes that the earlyprintk device will
be page-aligned. Obviously, that doesn't play well with the above example.
Further investigation shows that set_fixmap_io uses __set_fixmap instead
of __set_fixmap_offset. A fix is to introduce a set_fixmap_offset_io that
uses the latter, and to remove the superflous call to fix_to_virt
(which only returns the value that set_fixmap_io has already given us).
With this applied, my VMs are back in business. Tested on a Cortex-A57
platform with kvmtool as platform emulation.
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Mark Salter <msalter@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Dave Anderson [Tue, 15 Apr 2014 17:53:24 +0000 (18:53 +0100)]
arm64: Fix for the arm64 kern_addr_valid() function
Fix for the arm64 kern_addr_valid() function to recognize
virtual addresses in the kernel logical memory map. The
function fails as written because it does not check whether
the addresses in that region are mapped at the pmd level to
2MB or 512MB pages, continues the page table walk to the
pte level, and issues a garbage value to pfn_valid().
Tested on 4K-page and 64K-page kernels.
Signed-off-by: Dave Anderson <anderson@redhat.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Linus Torvalds [Sat, 3 May 2014 15:32:48 +0000 (08:32 -0700)]
Merge branch 'irq-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
"This udpate delivers:
- A fix for dynamic interrupt allocation on x86 which is required to
exclude the GSI interrupts from the dynamic allocatable range.
This was detected with the newfangled tablet SoCs which have GPIOs
and therefor allocate a range of interrupts. The MSI allocations
already excluded the GSI range, so we never noticed before.
- The last missing set_irq_affinity() repair, which was delayed due
to testing issues
- A few bug fixes for the armada SoC interrupt controller
- A memory allocation fix for the TI crossbar interrupt controller
- A trivial kernel-doc warning fix"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip: irq-crossbar: Not allocating enough memory
irqchip: armanda: Sanitize set_irq_affinity()
genirq: x86: Ensure that dynamic irq allocation does not conflict
linux/interrupt.h: fix new kernel-doc warnings
irqchip: armada-370-xp: Fix releasing of MSIs
irqchip: armada-370-xp: implement the ->check_device() msi_chip operation
irqchip: armada-370-xp: fix invalid cast of signed value into unsigned variable
Linus Torvalds [Sat, 3 May 2014 15:31:45 +0000 (08:31 -0700)]
Merge branch 'timers-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull timer fixes from Thomas Gleixner:
"This update brings along:
- Two fixes for long standing bugs in the hrtimer code, one which
prevents remote enqueuing and the other preventing arbitrary delays
after a interrupt hang was detected
- A fix in the timer wheel which prevents math overflow
- A fix for a long standing issue with the architected ARM timer
related to the C3STOP mechanism.
- A trivial compile fix for nspire SoC clocksource"
* 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
timer: Prevent overflow in apply_slack
hrtimer: Prevent remote enqueue of leftmost timers
hrtimer: Prevent all reprogramming if hang detected
clocksource: nspire: Fix compiler warning
clocksource: arch_arm_timer: Fix age-old arch timer C3STOP detection issue
Linus Torvalds [Sat, 3 May 2014 15:30:44 +0000 (08:30 -0700)]
Merge tag 'trace-fixes-v3.15-rc3' of git://git./linux/kernel/git/rostedt/linux-trace
Pull tracing fix from Steven Rostedt:
"This is a small fix where the trigger code used the wrong
rcu_dereference(). It required rcu_dereference_sched() instead of the
normal rcu_dereference(). It produces a nasty RCU lockdep splat due
to the incorrect rcu notation"
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
* tag 'trace-fixes-v3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
tracing: Use rcu_dereference_sched() for trace event triggers
Steven Rostedt (Red Hat) [Fri, 2 May 2014 17:30:04 +0000 (13:30 -0400)]
tracing: Use rcu_dereference_sched() for trace event triggers
As trace event triggers are now part of the mainline kernel, I added
my trace event trigger tests to my test suite I run on all my kernels.
Now these tests get run under different config options, and one of
those options is CONFIG_PROVE_RCU, which checks under lockdep that
the rcu locking primitives are being used correctly. This triggered
the following splat:
===============================
[ INFO: suspicious RCU usage. ]
3.15.0-rc2-test+ #11 Not tainted
-------------------------------
kernel/trace/trace_events_trigger.c:80 suspicious rcu_dereference_check() usage!
other info that might help us debug this:
rcu_scheduler_active = 1, debug_locks = 0
4 locks held by swapper/1/0:
#0: ((&(&j_cdbs->work)->timer)){..-...}, at: [<
ffffffff8104d2cc>] call_timer_fn+0x5/0x1be
#1: (&(&pool->lock)->rlock){-.-...}, at: [<
ffffffff81059856>] __queue_work+0x140/0x283
#2: (&p->pi_lock){-.-.-.}, at: [<
ffffffff8106e961>] try_to_wake_up+0x2e/0x1e8
#3: (&rq->lock){-.-.-.}, at: [<
ffffffff8106ead3>] try_to_wake_up+0x1a0/0x1e8
stack backtrace:
CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.15.0-rc2-test+ #11
Hardware name: /DG965MQ, BIOS MQ96510J.86A.0372.2006.0605.1717 06/05/2006
0000000000000001 ffff88007e083b98 ffffffff819f53a5 0000000000000006
ffff88007b0942c0 ffff88007e083bc8 ffffffff81081307 ffff88007ad96d20
0000000000000000 ffff88007af2d840 ffff88007b2e701c ffff88007e083c18
Call Trace:
<IRQ> [<
ffffffff819f53a5>] dump_stack+0x4f/0x7c
[<
ffffffff81081307>] lockdep_rcu_suspicious+0x107/0x110
[<
ffffffff810ee51c>] event_triggers_call+0x99/0x108
[<
ffffffff810e8174>] ftrace_event_buffer_commit+0x42/0xa4
[<
ffffffff8106aadc>] ftrace_raw_event_sched_wakeup_template+0x71/0x7c
[<
ffffffff8106bcbf>] ttwu_do_wakeup+0x7f/0xff
[<
ffffffff8106bd9b>] ttwu_do_activate.constprop.126+0x5c/0x61
[<
ffffffff8106eadf>] try_to_wake_up+0x1ac/0x1e8
[<
ffffffff8106eb77>] wake_up_process+0x36/0x3b
[<
ffffffff810575cc>] wake_up_worker+0x24/0x26
[<
ffffffff810578bc>] insert_work+0x5c/0x65
[<
ffffffff81059982>] __queue_work+0x26c/0x283
[<
ffffffff81059999>] ? __queue_work+0x283/0x283
[<
ffffffff810599b7>] delayed_work_timer_fn+0x1e/0x20
[<
ffffffff8104d3a6>] call_timer_fn+0xdf/0x1be^M
[<
ffffffff8104d2cc>] ? call_timer_fn+0x5/0x1be
[<
ffffffff81059999>] ? __queue_work+0x283/0x283
[<
ffffffff8104d823>] run_timer_softirq+0x1a4/0x22f^M
[<
ffffffff8104696d>] __do_softirq+0x17b/0x31b^M
[<
ffffffff81046d03>] irq_exit+0x42/0x97
[<
ffffffff81a08db6>] smp_apic_timer_interrupt+0x37/0x44
[<
ffffffff81a07a2f>] apic_timer_interrupt+0x6f/0x80
<EOI> [<
ffffffff8100a5d8>] ? default_idle+0x21/0x32
[<
ffffffff8100a5d6>] ? default_idle+0x1f/0x32
[<
ffffffff8100ac10>] arch_cpu_idle+0xf/0x11
[<
ffffffff8107b3a4>] cpu_startup_entry+0x1a3/0x213
[<
ffffffff8102a23c>] start_secondary+0x212/0x219
The cause is that the triggers are protected by rcu_read_lock_sched() but
the data is dereferenced with rcu_dereference() which expects it to
be protected with rcu_read_lock(). The proper reference should be
rcu_dereference_sched().
Cc: Tom Zanussi <tom.zanussi@linux.intel.com>
Cc: stable@vger.kernel.org # 3.14+
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Linus Torvalds [Sat, 3 May 2014 01:16:31 +0000 (18:16 -0700)]
Merge tag 'pm+acpi-3.15-rc4' of git://git./linux/kernel/git/rafael/linux-pm
Pull ACPI and power management fixes from Rafael Wysocki:
"A bunch of regression fixes this time. They fix two regressions in
the PNP subsystem, one in the ACPI processor driver and one in the
ACPI EC driver, four cpufreq driver regressions and an unrelated bug
in one of the drivers. The regressions are recent or introduced in
3.14.
Specifics:
- There are two bugs in the ACPI PNP core that cause errors to be
returned if optional ACPI methods are not present. After an ACPI
core change made in 3.14 one of those errors leads to serial port
suspend failures on some systems. Fix from Rafael J Wysocki.
- A recently added PNP quirk related to Intel chipsets intorduced a
build error in unusual configurations (PNP without PCI). Fix from
Bjorn Helgaas.
- An ACPI EC workaround related to system suspend on Samsung machines
added in 3.14 introduced a race causing some valid EC events to be
discarded. Fix from Kieran Clancy.
- The acpi-cpufreq driver fails to load on some systems after a 3.14
commit related to APIC ID parsing that overlooked one corner case.
Fix from Lan Tianyu.
- Fix for a recently introduced build problem in the ppc-corenet
cpufreq driver from Tim Gardner.
- A recent cpufreq core change to ensure serialization of frequency
transitions for drivers with a ->target_index() callback overlooked
the fact that some of those drivers had been doing operations
introduced by it into the core already by themselves. That
resulted in a mess in which the core and the drivers try to do the
same thing and block each other which leads to deadlocks. Fixes
for the powernow-k7, powernow-k6, and longhaul cpufreq drivers from
Srivatsa S Bhat.
- Fix for a computational error in the powernow-k6 cpufreq driver
from Srivatsa S Bhat"
* tag 'pm+acpi-3.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
ACPI / processor: Fix failure of loading acpi-cpufreq driver
PNP / ACPI: Do not return errors if _DIS or _SRS are not present
PNP: Fix compile error in quirks.c
ACPI / EC: Process rather than discard events in acpi_ec_clear
cpufreq: ppc-corenet-cpufreq: Fix __udivdi3 modpost error
cpufreq: powernow-k7: Fix double invocation of cpufreq_freq_transition_begin/end
cpufreq: powernow-k6: Fix double invocation of cpufreq_freq_transition_begin/end
cpufreq: powernow-k6: Fix incorrect comparison with max_multipler
cpufreq: longhaul: Fix double invocation of cpufreq_freq_transition_begin/end
Linus Torvalds [Sat, 3 May 2014 01:12:54 +0000 (18:12 -0700)]
Merge tag 'dt-for-linus' of git://git.secretlab.ca/git/linux
Pull driver core deferred probe fix from Grant Likely:
"Drivercore race condition fix (exposed by devicetree)
This branch fixes a bug where a device can get stuck in the deferred
list even though all its dependencies are met. The bug has existed
for a long time, but new platform conversions to device tree have
exposed it. This patch is needed to get those platforms working.
This was the pending bug fix I mentioned in my previous pull request.
Normally this would go through Greg's tree seeing that it is a
drivercore change, but devicetree exposes the problem. I've discussed
with Greg and he okayed me asking you to pull directly"
* tag 'dt-for-linus' of git://git.secretlab.ca/git/linux:
drivercore: deferral race condition fix
Rafael J. Wysocki [Fri, 2 May 2014 22:20:31 +0000 (00:20 +0200)]
Merge branches 'acpi-ec' and 'acpi-processor'
* acpi-ec:
ACPI / EC: Process rather than discard events in acpi_ec_clear
* acpi-processor:
ACPI / processor: Fix failure of loading acpi-cpufreq driver
Rafael J. Wysocki [Fri, 2 May 2014 22:20:18 +0000 (00:20 +0200)]
Merge branch 'pnp'
* pnp:
PNP / ACPI: Do not return errors if _DIS or _SRS are not present
PNP: Fix compile error in quirks.c
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