Stephen Boyd [Wed, 17 Apr 2013 23:26:18 +0000 (16:26 -0700)]
ARM: arch_timer: Silence debug preempt warnings
Hot-plugging with CONFIG_DEBUG_PREEMPT=y on a device with arm
architected timers causes a slew of "using smp_processor_id() in
preemptible" warnings:
BUG: using smp_processor_id() in preemptible [
00000000] code: sh/111
caller is arch_timer_cpu_notify+0x14/0xc8
This happens because sometimes the cpu notifier,
arch_timer_cpu_notify(), is called in preemptible context and
other times in non-preemptible context but we use this_cpu_ptr()
to retrieve the clockevent in all cases. We're only going to
actually use the pointer in non-preemptible context though, so
push the this_cpu_ptr() access down into the cases to force the
checks to occur only in non-preemptible contexts.
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Arnd Bergmann [Tue, 23 Apr 2013 21:16:44 +0000 (23:16 +0200)]
ARM: OMAP: remove unused variable
Commit
0583fe478a7 "ARM: convert arm/arm64 arch timer to use CLKSRC_OF init"
has left the omap5_realtime_timer_init() function with a stale variable and
broken whitespace. This fixes both.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Olof Johansson [Wed, 17 Apr 2013 17:10:01 +0000 (10:10 -0700)]
Merge tag 'clksrc-cleanup-for-3.10-part2' of git://sources.calxeda.com/kernel/linux into late/clksrc
This is the 2nd part of ARM timer clean-ups for 3.10. This series has
the following changes:
- Add sched_clock selection logic to select the highest frequency clock
- Use full 64-bit arch timer counter for sched_clock
- Convert arch timer, sp804 and integrator-cp timers to CLKSRC_OF and
adapt all users to use clocksource_of_init
* tag 'clksrc-cleanup-for-3.10-part2' of git://sources.calxeda.com/kernel/linux:
devtree: add binding documentation for sp804
ARM: integrator-cp: convert use CLKSRC_OF for timer init
ARM: versatile: use OF init for sp804 timer
ARM: versatile: add versatile dtbs to dtbs target
ARM: vexpress: remove extra timer-sp control register clearing
ARM: dts: vexpress: disable CA9 core tile sp804 timer
ARM: vexpress: remove sp804 OF init
ARM: highbank: use OF init for sp804 timer
ARM: timer-sp: convert to use CLKSRC_OF init
OF: add empty of_device_is_available for !OF
ARM: convert arm/arm64 arch timer to use CLKSRC_OF init
ARM: make machine_desc->init_time default to clocksource_of_init
ARM: arch_timer: use full 64-bit counter for sched_clock
ARM: make sched_clock just call a function pointer
ARM: sched_clock: allow changing to higher frequency counter
Signed-off-by: Olof Johansson <olof@lixom.net>
This has a nasty set of conflicts with the exynos MCT code, which was
moved in a separate branch, and then fixed up when merged in, but still
conflicts a bit here. It should have been sorted out by this merge though.
Haojian Zhuang [Wed, 13 Mar 2013 05:05:34 +0000 (13:05 +0800)]
devtree: add binding documentation for sp804
The sp804 binding is already in use by several platforms. This adds missing
documentation for the binding and also extends the binding to handle some
additional possible interrupt configurations.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Wed, 13 Mar 2013 20:31:12 +0000 (15:31 -0500)]
ARM: integrator-cp: convert use CLKSRC_OF for timer init
Move the integrator-cp timer init to timer-sp.c and use CLKSRC_OF. There is
no reason to use the aliases, so drop them from the init code.
The integrator-cp timers are mistakenly called sp804 timers in the dts, but
in fact they are not sp804 dual timers, but single timers with the same
programming model. Fix the dts to reflect this.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Rob Herring [Wed, 13 Mar 2013 22:07:44 +0000 (17:07 -0500)]
ARM: versatile: use OF init for sp804 timer
Enable DT based init for the sp804 timers on versatile DT platform.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Thu, 14 Mar 2013 02:31:42 +0000 (21:31 -0500)]
ARM: versatile: add versatile dtbs to dtbs target
Add the versatile platform dtbs to the dtbs make rule.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 25 Mar 2013 16:20:36 +0000 (11:20 -0500)]
ARM: vexpress: remove extra timer-sp control register clearing
The timer-sp initialization code clears the control register before
initializing the timers, so every platform doing this is redundant.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Thu, 7 Feb 2013 03:15:09 +0000 (21:15 -0600)]
ARM: dts: vexpress: disable CA9 core tile sp804 timer
The motherboard sp804 timer is used, but core tile sp804 timer is not.
According to Russell King, the clock configuration is undocumented and
defaults to 32kHz which is not desireable. So mark core tile sp804 timer
as disabled.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Thu, 7 Feb 2013 03:18:31 +0000 (21:18 -0600)]
ARM: vexpress: remove sp804 OF init
Remove the vexpress specific setup for the sp804 timer now that
clocksource_of_init will do it.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Rob Herring [Mon, 21 Jan 2013 20:19:23 +0000 (14:19 -0600)]
ARM: highbank: use OF init for sp804 timer
Remove the highbank specific setup for the sp804 timer now that
clocksource_of_init will do it.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 25 Mar 2013 16:23:52 +0000 (11:23 -0500)]
ARM: timer-sp: convert to use CLKSRC_OF init
This adds CLKSRC_OF based init for sp804 timer. The clock initialization is
refactored to support retrieving the clock(s) from the DT.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Wed, 20 Mar 2013 21:56:18 +0000 (16:56 -0500)]
OF: add empty of_device_is_available for !OF
Add an empty version of of_device_is_available.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Wed, 10 Apr 2013 23:27:51 +0000 (18:27 -0500)]
ARM: convert arm/arm64 arch timer to use CLKSRC_OF init
This converts arm and arm64 to use CLKSRC_OF DT based initialization for
the arch timer. A new function arch_timer_arch_init is added to allow for
arch specific setup.
This has a side effect of enabling sched_clock on omap5 and exynos5. There
should not be any reason not to use the arch timers for sched_clock.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Arnd Bergmann [Mon, 25 Mar 2013 16:14:57 +0000 (11:14 -0500)]
ARM: make machine_desc->init_time default to clocksource_of_init
Originally from a default machine descriptor patch from Arnd, pull out
just the default call to clocksource_of_init part. This is needed so that
platforms can simply remove .init_time calls as they are converted to use
clocksource_of_init.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 11 Mar 2013 21:23:46 +0000 (16:23 -0500)]
ARM: arch_timer: use full 64-bit counter for sched_clock
Only 32-bits of the arch timer were being used and wrapping was needlessly
being done in s/w. By using the full counter (56-64 bits), we don't need
to deal with wrapping and can simplify the implementation when using
arch timer.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Mon, 1 Apr 2013 18:53:38 +0000 (13:53 -0500)]
ARM: make sched_clock just call a function pointer
This converts sched_clock to simply a call to a function pointer in order
to allow overriding it. This will allow for use with 64-bit counters where
overflow handling is not needed.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Rob Herring [Fri, 8 Feb 2013 22:14:59 +0000 (16:14 -0600)]
ARM: sched_clock: allow changing to higher frequency counter
Allow multiple calls to setup_sched_clock and switch to the new counter
if it is higher frequency.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Arnd Bergmann [Tue, 9 Apr 2013 20:07:37 +0000 (22:07 +0200)]
Merge tag 'mct-exynos-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
add support exynos mct device tree and move into drivers/clocksource
* tag 'mct-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
clocksource: mct: Add terminating entry for exynos_mct_ids table
clocksource: mct: Add missing semicolons in exynos_mct.c
ARM: EXYNOS: move mct driver to drivers/clocksource
ARM: EXYNOS: remove static io-remapping of mct registers for Exynos5
ARM: dts: add mct device tree node for all supported Exynos SoC's
ARM: EXYNOS: allow dt based discovery of mct controller using clocksource_of_init
ARM: EXYNOS: add device tree support for MCT controller driver
ARM: EXYNOS: prepare an array of MCT interrupt numbers and use it
ARM: EXYNOS: add a register base address variable in mct controller driver
Conflicts:
drivers/clocksource/Makefile
drivers/clocksource/exynos_mct.c
[arnd: adapt to CLOCKSOURCE_OF_DECLARE interface change]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 20:05:50 +0000 (22:05 +0200)]
Merge tag 'irq-s3c24xx-for-v3.10' of git://git./linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>:
s3c24xx irq cleanup and move into drivers/irqchip
* tag 'irq-s3c24xx-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
irqchip: s3c24xx: add devicetree support
irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
irqchip: s3c24xx: globally keep track of the created intc instances
irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
irqchip: s3c24xx: fix irqlist of second s3c2416 controller
irqchip: s3c24xx: fix comments on some camera interrupts
ARM: S3C24XX: move irq driver to drivers/irqchip
ARM: S3C24XX: add handle_irq function
ARM: S3C24XX: make s3c24xx_init_intc static
ARM: S3C24XX: move s3c24xx_init_irq to s3c2410_init_irq
ARM: S3C24XX: fix irq parent check
ARM: S3C24XX: fix redundant checks in the irq mapping function
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:57:39 +0000 (17:57 +0200)]
Merge tag 'ux500-pinctrl' of git://git./linux/kernel/git/linusw/linux-stericsson into next/drivers
From Linus Walleij <linus.walleij@linaro.org>:
ux500 pinctrl updates for the ARM SoC tree.
* tag 'ux500-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: 8500: add ab8500-musb pinctrl support
ARM: ux500: remove redundant DB8500_PIN_SLEEP definition
ARM: ux500: Add Snowball pin configuration for user LED
ARM: ux500: u8500: fix pinctrl IDLE state definition for SPI2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:10:31 +0000 (17:10 +0200)]
Merge tag 'tegra-for-3.10-clk' of git://git./linux/kernel/git/swarren/linux-tegra into next/drivers
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: tegra: clock driver development
This branch contains most fixes and enhancements to the Tegra common
clock driver. The main new feature is a driver for Tegra114, which
coupled with later device tree changes enables many devices on that
chip, such as MMC, I2C, etc.
This branch depends on a patch in:
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
Mike has stated that this branch is stable, and is aware of this
dependency and merge.
Mike's branch is based on v3.9-rc3, which includes a USB change which
causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence,
this branch pulls in v3.9-rc4 to ensure bisectability as much as
possible.
This branch is based on v3.9-rc4, followed by a merge of previous Tegra
"soc" pull request, followed by a merge of clk-for-3.10.
* tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
clk: tegra: fix enum tegra114_clk to match binding
clk: tegra: Remove forced clk_enable of uartd
ARM: dt: Add references to tegra_car clocks
clk: tegra: devicetree match for nvidia,tegra114-car
clk: tegra: Implement clocks for Tegra114
ARM: tegra: Define Tegra114 CAR binding
clk: tegra: Workaround for Tegra114 MSENC problem
clk: tegra: Add flags to tegra_clk_periph()
clk: tegra: Add new fields and PLL types for Tegra114
clk: tegra: move from a lock bit idx to a lock mask
clk: tegra: Add PLL post divider table
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
clk: tegra: Add TEGRA_PLL_BYPASS flag
clk: tegra: Refactor PLL programming code
clk: tegra: provide dummy cpu car ops
clk: tegra: defer application of init table
clk: tegra: Fix cdev1 and cdev2 IDs
clk: tegra: Make gr2d and gr3d clocks children of pll_c
clk: tegra: Export peripheral reset functions
clk: tegra: Fix periph_clk_to_bit macro
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:09:35 +0000 (17:09 +0200)]
Merge branch 'depends/clk' into next/drivers
This is a snapshot of the stable clk branch at
git://git.linaro.org/people/mturquette/linux.git clk-for-3.10
which is a dependency for the tegra clock changes.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Tue, 9 Apr 2013 15:07:36 +0000 (17:07 +0200)]
Merge branch 'tegra/soc' into next/drivers
This is a dependency for the tegra/clk branch.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Conflicts:
drivers/clocksource/tegra20_timer.c
Arnd Bergmann [Mon, 8 Apr 2013 17:40:57 +0000 (19:40 +0200)]
Merge tag 'omap-for-v3.10/gpmc-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
GPMC updates from Jon Hunter <jon-hunter@ti.com>:
Adds GPMC (General Purpose Memory Controller) DT support for
NOR flash and Ethernet and includes various GPMC cleans-up
and fixes.
This series is dependent on commit
7185684 (ARM: OMAP: use
consistent error checking) from RMK's clean-up branch and commit
31d9adc (ARM: OMAP2+: Fix broken gpmc support).
* tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits)
ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes
ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails
ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
ARM: OMAP2+: Detect incorrectly aligned GPMC base address
ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
ARM: OMAP2+: Add device-tree support for NOR flash
ARM: OMAP2+: Add additional GPMC timing parameters
ARM: OMAP2+: Add function to read GPMC settings from device-tree
ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure()
ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings()
ARM: OMAP2+: Add function for configuring GPMC settings
ARM: OMAP2+: Add structure for storing GPMC settings
ARM: OMAP2+: Add variable to store number of GPMC waitpins
ARM: OMAP2+: Simplify code configuring ONENAND devices
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 17:30:48 +0000 (19:30 +0200)]
Merge tag 'omap-for-v3.10/timer-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on
7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and
960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of
7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 17:06:51 +0000 (19:06 +0200)]
Merge tag 'omap-for-v3.10/usb-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit
1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 16:34:19 +0000 (18:34 +0200)]
Merge branch 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx into next/drivers
From Michal Simek <michal.simek@xilinx.com>:
* 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Move timer to generic location
arm: zynq: Do not use xilinx specific function names
arm: zynq: Move timer to clocksource interface
arm: zynq: Use standard timer binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 16:26:15 +0000 (18:26 +0200)]
Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
From Tony Prisk <linux@prisktech.co.nz>:
arm: vt8500: Add pinctrl driver for arch-vt8500
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
* tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits)
pinctrl: bcm2835: make use of of_property_read_u32_index()
gpio: vt8500: Remove arch-vt8500 gpio driver
arm: vt8500: Remove gpio devicetree nodes
arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
arm: vt8500: Increase available GPIOs on arch-vt8500
of: Remove duplicated code for validating property and value
of: Add support for reading a u32 from a multi-value property.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Arnd Bergmann [Mon, 8 Apr 2013 15:52:35 +0000 (17:52 +0200)]
Merge tag 'renesas-intc-external-irq2-for-v3.10' of git://git./linux/kernel/git/horms/renesas into next/drivers
From Simon Horman <horms+renesas@verge.net.au>:
Update for Renesas INTC External IRQ pin driver for v3.10
This adds support for shared interrupt lines to the
Renesas INTC External IRQ pin driver which has already
been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10).
* tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
irqchip: intc-irqpin: Add support for shared interrupt lines
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Wei Yongjun [Fri, 5 Apr 2013 06:58:52 +0000 (14:58 +0800)]
ARM: tegra: pm: remove duplicated include from pm.c
Remove duplicated include.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Thu, 4 Apr 2013 23:13:54 +0000 (17:13 -0600)]
clk: tegra: fix enum tegra114_clk to match binding
A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:
ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:49 +0000 (17:40 +0300)]
clk: tegra: Remove forced clk_enable of uartd
The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:48 +0000 (17:40 +0300)]
ARM: dt: Add references to tegra_car clocks
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:46 +0000 (17:40 +0300)]
clk: tegra: devicetree match for nvidia,tegra114-car
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:45 +0000 (17:40 +0300)]
clk: tegra: Implement clocks for Tegra114
Implement clocks for Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Thu, 4 Apr 2013 17:48:28 +0000 (20:48 +0300)]
ARM: tegra: Define Tegra114 CAR binding
The device tree binding models Tegra114 CAR (Clock And Reset) as a single
monolithic clock provider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:44 +0000 (17:40 +0300)]
clk: tegra: Workaround for Tegra114 MSENC problem
Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:42 +0000 (17:40 +0300)]
clk: tegra: Add flags to tegra_clk_periph()
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:41 +0000 (17:40 +0300)]
clk: tegra: Add new fields and PLL types for Tegra114
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:40 +0000 (17:40 +0300)]
clk: tegra: move from a lock bit idx to a lock mask
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:39 +0000 (17:40 +0300)]
clk: tegra: Add PLL post divider table
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:38 +0000 (17:40 +0300)]
clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:37 +0000 (17:40 +0300)]
clk: tegra: Add TEGRA_PLL_BYPASS flag
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:36 +0000 (17:40 +0300)]
clk: tegra: Refactor PLL programming code
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Wed, 3 Apr 2013 14:40:35 +0000 (17:40 +0300)]
clk: tegra: provide dummy cpu car ops
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Mon, 25 Mar 2013 19:22:24 +0000 (13:22 -0600)]
clk: tegra: defer application of init table
The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Prashant Gaikwad [Thu, 4 Apr 2013 09:05:04 +0000 (14:35 +0530)]
clk: tegra: Fix cdev1 and cdev2 IDs
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Tue, 2 Apr 2013 14:18:44 +0000 (16:18 +0200)]
clk: tegra: Make gr2d and gr3d clocks children of pll_c
By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.
gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Thu, 28 Mar 2013 20:31:27 +0000 (21:31 +0100)]
clk: tegra: Export peripheral reset functions
The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.
Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Yen Lin [Wed, 6 Mar 2013 11:47:24 +0000 (11:47 +0000)]
clk: tegra: Fix periph_clk_to_bit macro
The parameter name should be "gate", not "periph". This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Thu, 4 Apr 2013 22:08:13 +0000 (16:08 -0600)]
Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-3.10/clk
Stephen Warren [Thu, 4 Apr 2013 22:08:06 +0000 (16:08 -0600)]
Merge branch 'for-3.10/soc' into for-3.10/clk
Tony Lindgren [Thu, 4 Apr 2013 18:22:33 +0000 (11:22 -0700)]
Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc
Michal Simek [Wed, 20 Mar 2013 09:46:01 +0000 (10:46 +0100)]
arm: zynq: Move timer to generic location
Move zynq timer out of mach folder to generic location
and enable it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 27 Mar 2013 11:05:28 +0000 (12:05 +0100)]
arm: zynq: Do not use xilinx specific function names
Remove all xilinx specific names from the driver
because this is generic driver for cadence ttc.
xttc->ttc
ttcps->ttc
...
No functional changes in this driver.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 20 Mar 2013 09:24:59 +0000 (10:24 +0100)]
arm: zynq: Move timer to clocksource interface
Use clocksource timer initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 20 Mar 2013 09:15:28 +0000 (10:15 +0100)]
arm: zynq: Use standard timer binding
Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.
Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Axel Lin [Thu, 4 Apr 2013 06:34:45 +0000 (15:34 +0900)]
clocksource: mct: Add terminating entry for exynos_mct_ids table
The of_device_id table is supposed to be zero-terminated.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Doug Anderson [Thu, 4 Apr 2013 06:24:32 +0000 (15:24 +0900)]
clocksource: mct: Add missing semicolons in exynos_mct.c
The CLOCKSOURCE_OF_DECLARE lines were added without a semicolon at the
end. On my system this causes a compile-time error that looks like:
drivers/clocksource/exynos_mct.c:557:202: warning: comparison of distinct pointer types lacks a cast [enabled by default]
drivers/clocksource/exynos_mct.c:558:1: error: expected ',' or ';' before 'static'
The error didn't show up till now because there was an extra semicolon
at end of the CLOCKSOURCE_OF_DECLARE definition that was removed by
Arnd Bergmann in "clocksource: make CLOCKSOURCE_OF_DECLARE type safe"
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:55:10 +0000 (14:55 +0900)]
irqchip: s3c24xx: add devicetree support
Add the necessary code to initialize the interrupt controller
thru devicetree data using the irqchip infrastructure.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:52 +0000 (14:53 +0900)]
irqchip: s3c24xx: make interrupt handling independent of irq_domain structure
Keep a pointer to the corresponding s3c_irq_data struct as irq_chip_data.
This removes the need to fetch the intc struct from the irq_domains
host_data, thus making it independent of the underlying irq_domain
structure.
Also keep the real register offset of the interrupt in the s3c_irq_data
struct to make it independent of the hwirq structure in the irq_domain
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:49 +0000 (14:53 +0900)]
irqchip: s3c24xx: globally keep track of the created intc instances
For dt-enabled machines we want to use a big irq_domain over all controllers
and therefore need to access not only the main controllers but the
sub-controller as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:45 +0000 (14:53 +0900)]
irqchip: s3c24xx: add irq_set_type callback for basic interrupt types
Enables post-init setting of the desired typehandler for the interrupt.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:41 +0000 (14:53 +0900)]
irqchip: s3c24xx: fix irqlist of second s3c2416 controller
The list in used was from the s3c2450, a close cousin of the s3c2416.
As it's not possible to distinguish between the s3c2416 and s3c2450
the additional interrupts of the s3c2450 will only be available thru
devicetree later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:37 +0000 (14:53 +0900)]
irqchip: s3c24xx: fix comments on some camera interrupts
Might be confusing for people to read the code without having the
datasheet nearby.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Heiko Stuebner [Thu, 4 Apr 2013 05:53:33 +0000 (14:53 +0900)]
ARM: S3C24XX: move irq driver to drivers/irqchip
This move is necessary to make use of the irqchip infrastructure
for the following devicetree support for s3c24xx architectures.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Stephen Warren [Thu, 28 Mar 2013 05:09:57 +0000 (05:09 +0000)]
pinctrl: bcm2835: make use of of_property_read_u32_index()
Use the new standard API of_property_read_u32_index() instead of open-
coding it.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Tony Prisk [Wed, 20 Feb 2013 04:29:33 +0000 (17:29 +1300)]
gpio: vt8500: Remove arch-vt8500 gpio driver
With the move to a combined pinctrl/gpio driver, the arch-vt8500
gpio driver is no longer required.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tony Prisk [Wed, 20 Feb 2013 04:28:56 +0000 (17:28 +1300)]
arm: vt8500: Remove gpio devicetree nodes
Remove the gpio related devicetree nodes as these are no longer required
with the move to a combined pinctrl/gpio driver.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tony Prisk [Tue, 19 Feb 2013 20:52:23 +0000 (09:52 +1300)]
arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
This patch adds pinctrl nodes to the VIA VT8500 and Wondermedia SoC dtsi
files to support the pinctrl driver.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tony Prisk [Tue, 19 Feb 2013 20:32:19 +0000 (09:32 +1300)]
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.
Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.
All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tony Prisk [Sat, 9 Mar 2013 05:22:30 +0000 (18:22 +1300)]
arm: vt8500: Increase available GPIOs on arch-vt8500
With the inclusion of the pin control driver, more GPIO pins have been
identified on the arch-vt8500 SoCs requiring an increase in the available
GPIOs.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tony Prisk [Wed, 3 Apr 2013 04:57:11 +0000 (17:57 +1300)]
of: Remove duplicated code for validating property and value
Several functions in of/base.c have the same code duplicated for
finding and validating a property and value.
struct property *prop = of_find_property(np, propname, NULL);
if (!prop)
return -EINVAL;
if (!prop->value)
return -ENODATA;
if (<some length> > prop->length)
return -EOVERFLOW;
This patch adds of_find_property_value_of_size() which performs the
equivalent of the above code and removes the instances where it was
duplicated in several functions.
Reported-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Tony Prisk [Sat, 23 Mar 2013 04:02:15 +0000 (17:02 +1300)]
of: Add support for reading a u32 from a multi-value property.
This patch adds an of_property_read_u32_index() function to allow
reading a single indexed u32 value from a property containing multiple
u32 values.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robherring2@gmail.com>
Javier Martinez Canillas [Thu, 14 Mar 2013 21:54:11 +0000 (22:54 +0100)]
ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes
Besides being used to interface with external memory devices,
the General-Purpose Memory Controller can be used to connect
Pseudo-SRAM devices such as ethernet controllers to OMAP2+
processors using the TI GPMC as a data bus.
This patch allows an ethernet chip to be defined as an GPMC
child device node.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Javier Martinez Canillas [Thu, 14 Mar 2013 15:09:21 +0000 (16:09 +0100)]
ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child()
The gpmc_probe_nor_child() function is used in the GPMC driver to
configure the GPMC for a NOR child device node.
But this function is quite generic and all the NOR specific configuration
is made by the driver of the actual NOR flash memory used.
Other Pseudo-SRAM devices such as ethernet controllers need a similar
setup so by making this function generic it can be used for those too.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Javier Martinez Canillas [Thu, 14 Mar 2013 15:09:20 +0000 (16:09 +0100)]
ARM: OMAP2+: return -ENODEV if GPMC child device creation fails
gpmc_probe_nor_child() calls of_platform_device_create() to create a
platform device for the NOR child. If this function fails the value
of ret is returned to the caller but this value is zero since it was
assigned the return of a previous call to gpmc_cs_program_settings()
that had to succeed or otherwise gpmc_probe_nor_child() would have
returned before.
This means that if of_platform_device_create() fails, 0 will be returned
to the caller instead of an appropriate error code.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Wed, 6 Mar 2013 20:36:47 +0000 (14:36 -0600)]
ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails
When the GPMC driver is probed, we call gpmc_mem_init() to see which
chip-selects have already been configured and enabled by the boot-loader
and allocate space for them. If we fail to allocate space for one
chip-select, then we return failure from the probe and the GPMC driver
will not be available.
Rather than render the GPMC useless for all GPMC devices, if we fail to
allocate space for one chip-select print a warning and disable the
chip-select. This way other GPMC clients can still be used.
There is no downside to this approach, because all GPMC clients need to
request a chip-select before they can use the GPMC and on requesting a
chip-select, if memory has not already been reserved for the chip-select
then it will be.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Wed, 6 Mar 2013 20:12:59 +0000 (14:12 -0600)]
ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable
With commit
21cc2bd (ARM: OMAP2+: Remove apollon board support) the
variable "boot_rom_space" is now not needed and the code surrounding
this variable can be cleaned up and simplified. Remove unnecessary
definitions and clean-up the comment as well.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Wed, 6 Mar 2013 18:00:10 +0000 (12:00 -0600)]
ARM: OMAP2+: Detect incorrectly aligned GPMC base address
Each GPMC chip-select can be configured to map 16MB, 32MB, 64MB or 128MB
of address space. The physical base address where a chip-select starts
is also configurable and must be aligned on a boundary that is equal to
or greater than the size of the address space mapped bt the chip-select.
When enabling a GPMC chip-select, ensure that the base address is aligned
to the appropriate boundary.
Reported-by: Mark Jackson <mpfj-list@mimc.co.uk>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Mon, 25 Feb 2013 17:37:58 +0000 (11:37 -0600)]
ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT
When booting with device-tree, retrieve GPMC settings for ONENAND from
the device-tree blob. This will allow us to remove all static settings
stored in the gpmc-nand.c in the future once the migration to
device-tree is complete.
The user must now specify the ONENAND device width in the device-tree
binding so that the GPMC can be programmed correctly. Therefore, update
the device-tree binding documentation for ONENAND devices connected to
the GPMC to reflect this.
Please note that this does not include GPMC timings for ONENAND. The
timings are being calculated at runtime.
There is some legacy code that only enables read wait monitoring for
non-OMAP3 devices. There are no known OMAP3 device issues that prevent
this feature being enabled and so when booting with device-tree use the
wait-monitoring settings described in the device-tree blob.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Mon, 25 Feb 2013 17:36:47 +0000 (11:36 -0600)]
ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT
When booting with device-tree, retrieve GPMC settings for NAND from
the device-tree blob. This will allow us to remove all static settings
stored in the gpmc-nand.c in the future once the migration to
device-tree is complete.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Fri, 8 Feb 2013 22:46:13 +0000 (16:46 -0600)]
ARM: OMAP2+: Add device-tree support for NOR flash
NOR flash is not currently supported when booting with device-tree
on OMAP2+ devices. Add support to detect and configure NOR devices
when booting with device-tree.
Add documentation for the TI GPMC NOR binding.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Jon Hunter [Fri, 22 Feb 2013 00:51:27 +0000 (18:51 -0600)]
ARM: OMAP2+: Add additional GPMC timing parameters
Some of the GPMC timings parameters are currently missing from the GPMC
device-tree binding. Add these parameters to the binding documentation
as well as code to read them. Also add either "-ps" or "-ns" suffix to
the GPMC timing properties to indicate whether the timing is in
picoseconds or nanoseconds.
The existing code in gpmc_read_timings_dt() is checking the value of
of_property_read_u32() and only is successful storing the value read
in the gpmc_timings structure. Checking the return value in this case
is not necessary and we can simply read the value, if present, and
store directly in the gpmc_timings structure. Therefore, simplify the
code by removing these checks.
The comment in the gpmc_read_timings_dt() function, "only for OMAP3430"
is also incorrect as it is applicable to all OMAP3+ devices. So correct
this too.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Patrice Chotard [Fri, 29 Mar 2013 12:29:47 +0000 (13:29 +0100)]
ARM: ux500: 8500: add ab8500-musb pinctrl support
Add necessary definitions to support ab8500-musb pinctrl default and
sleep states.
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fabio Baltieri [Thu, 28 Mar 2013 16:21:08 +0000 (17:21 +0100)]
ARM: ux500: remove redundant DB8500_PIN_SLEEP definition
DB8500_PIN_SLEEP was defined twice, drop one of the two.
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Joseph Lo [Tue, 2 Apr 2013 01:20:50 +0000 (01:20 +0000)]
ARM: tegra: cpuidle: remove redundant parameters for powered-down mode
After the patch series for system suspending support, tegra_idle_lp2_last()
no longer uses its parameters cpu_on_time or cpu_off_time, so remove them.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:47 +0000 (19:31 +0800)]
ARM: tegra: pm: add platform suspend support
Adding suspend to RAM support for Tegra platform. There are three suspend
mode for Tegra. The difference were below.
* LP2: CPU voltage off
* LP1: CPU voltage off, DRAM in self-refresh
* LP0: CPU + Core voltage off, DRAM in self-refresh
After this patch, the LP2 suspend mode will be supported.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:46 +0000 (19:31 +0800)]
ARM: dt: tegra: add bindings of power management configurations for PMC
The PMC mostly controls the entry and exit of the system from different
sleep modes. Different platform or system may have different configurations.
The power management configurations of PMC is represented as some properties.
The system needs to define the properties when the system supports deep sleep
mode (i.e. suspend).
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:45 +0000 (19:31 +0800)]
ARM: tegra: irq: add wake up handling
Add the wake up handling for legacy irq controller, and using
IRQCHIP_MASK_ON_SUSPEND for wake irq handling.
Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:44 +0000 (19:31 +0800)]
gpio: tegra: add gpio wakeup source handling
This patch add the gpio wakeup source handling for the Tegra platform. It
was be done by enabling the irq for the gpio in the gpio controller and
enabling the bank irq of the gpio in the Tegra legacy irq controller when
the system going to suspend.
Based on the work by:
Varun Wadekar <vwadekar@nvidia.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:28 +0000 (19:31 +0800)]
ARM: tegra: moving the CPU power timer function to PMC driver
The CPU power timer set up function was related to PMC register. Now moving
it to PMC driver. And it also help to clean up the PM related code later.
The timer was calculated based on the input clock of PMC. In this patch, we
also get the clock from DT.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 3 Apr 2013 11:31:27 +0000 (19:31 +0800)]
ARM: tegra: add clock source of PMC to device trees
Adding the bindings of the clock source of PMC in DT.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tony Lindgren [Wed, 3 Apr 2013 17:47:59 +0000 (10:47 -0700)]
Merge branch 'omap-timer-for-v3.10' of git://github.com/jonhunter/linux into omap-for-v3.10/timer
Conflicts:
arch/arm/mach-omap2/timer.c
Tony Lindgren [Wed, 3 Apr 2013 17:32:47 +0000 (10:32 -0700)]
Merge commit '
7185684' into omap-for-v3.10/timer
Conflicts:
arch/arm/plat-omap/dmtimer.c
Resolve merge conflict in omap_device.c as per
Lothar Waßmann <LW@KARO-electronics.de>.
Mike Turquette [Thu, 28 Mar 2013 20:59:02 +0000 (13:59 -0700)]
clk: allow reentrant calls into the clk framework
Reentrancy into the clock framework is necessary for clock operations
that result in nested calls to the clk api. A common example is a clock
that is prepared via an i2c transaction, such as a clock inside of a
discrete audio chip or a power management IC. The i2c subsystem itself
will use the clk api resulting in a deadlock:
clk_prepare(audio_clk)
i2c_transfer(..)
clk_prepare(i2c_controller_clk)
The ability to reenter the clock framework prevents this deadlock.
Other use cases exist such as allowing .set_rate callbacks to call
clk_set_parent to achieve the best rate, or to save power in certain
configurations. Yet another example is performing pinctrl operations
from a clk_ops callback. Calls into the pinctrl subsystem may call
clk_{un}prepare on an unrelated clock. Allowing for nested calls to
reenter the clock framework enables both of these use cases.
Reentrancy is implemented by two global pointers that track the owner
currently holding a global lock. One pointer tracks the owner during
sleepable, mutex-protected operations and the other one tracks the owner
during non-interruptible, spinlock-protected operations.
When the clk framework is entered we try to hold the global lock. If it
is held we compare the current task against the current owner; a match
implies a nested call and we reenter. If the values do not match then
we block on the lock until it is released.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Mike Turquette [Thu, 28 Mar 2013 20:59:01 +0000 (13:59 -0700)]
clk: abstract locking out into helper functions
Create locking helpers for the global mutex and global spinlock. The
definitions of these helpers will be expanded upon in the next patch
which introduces reentrancy into the locking scheme.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Roger Quadros [Wed, 20 Mar 2013 15:45:00 +0000 (17:45 +0200)]
ARM: dts: omap3-beagle: Add USB Host support
Provide RESET and Power regulators for the USB PHY,
the USB Host port mode and the PHY device.
Also provide pin multiplexer information for USB host
pins.
CC: Benoît Cousson <b-cousson@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Roger Quadros [Wed, 20 Mar 2013 15:44:59 +0000 (17:44 +0200)]
ARM: dts: OMAP3: Add HS USB Host IP nodes
Adds device nodes for HS USB Host module, TLL module,
OHCI and EHCI controllers.
CC: Benoît Cousson <b-cousson@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This page took 0.047146 seconds and 5 git commands to generate.