From fab7c86ea474291776621eba042132f47af124e1 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 21 May 2019 11:03:45 +0100 Subject: [PATCH] AArch64: Add SVE DWARF registers The SVE DRAWF register names are missing from binutils, this may cause objdump and readelf to ignore certain DRAWF output as the registers are unknown (most notably CIEs). This patch adds the registers in accordance to the "DWARF for ARM(r) 64-bit Architecture (AARch64) with SVE support" documentation [1]. [1] https://developer.arm.com/docs/100985/latest/dwarf-for-the-arm-64-bit-architecture-aarch64-with-sve-support binutils/ChangeLog: * dwarf.c (dwarf_regnames_aarch64): Add SVE registers. * testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test. * testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test. --- binutils/ChangeLog | 6 +++++ binutils/dwarf.c | 10 +++++--- .../aarch64/sve-dwarf-registers.d | 25 +++++++++++++++++++ .../aarch64/sve-dwarf-registers.s | 6 +++++ 4 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.d create mode 100644 binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.s diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 184c93accd..9905cf6a90 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,9 @@ +2019-05-21 Tamar Christina + + * dwarf.c (dwarf_regnames_aarch64): Add SVE registers. + * testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test. + * testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test. + 2019-05-20 Faraz Shahbazker PR 14798 diff --git a/binutils/dwarf.c b/binutils/dwarf.c index 9f17af9ff8..f86e20db40 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -7175,13 +7175,17 @@ static const char *const dwarf_regnames_aarch64[] = "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", NULL, "elr", NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, "vg", "ffr", + "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", + "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", + "z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", + "z8", "z9", "z10", "z11", "z12", "z13", "z14", "z15", + "z16", "z17", "z18", "z19", "z20", "z21", "z22", "z23", + "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", }; void diff --git a/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.d b/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.d new file mode 100644 index 0000000000..84613668d2 --- /dev/null +++ b/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.d @@ -0,0 +1,25 @@ +#PROG: objcopy +#readelf: --debug-dump=frames + +Contents of the .eh_frame section: + + +00000000 0000000000000018 00000000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 4 + Data alignment factor: -8 + Return address column: 30 + Augmentation data: 1b + DW_CFA_def_cfa: r31 \(sp\) ofs 0 + DW_CFA_def_cfa_register: r96 \(z0\) + DW_CFA_def_cfa_offset: 5 + DW_CFA_restore_extended: r96 \(z0\) + DW_CFA_nop + DW_CFA_nop + +0000001c 0000000000000010 00000020 FDE cie=00000000 pc=0000000000000000..0000000000000000 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + diff --git a/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.s b/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.s new file mode 100644 index 0000000000..69f17f5eb3 --- /dev/null +++ b/binutils/testsuite/binutils-all/aarch64/sve-dwarf-registers.s @@ -0,0 +1,6 @@ + .arch armv8-a+sve + .cfi_startproc + .cfi_def_cfa_register 96 + .cfi_adjust_cfa_offset 5 + .cfi_restore 96 + .cfi_endproc -- 2.34.1