From c958a8a8fb341605fa49cb30d62e98f1b833f542 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Thu, 3 Sep 2009 16:17:36 +0000 Subject: [PATCH] gas/ * config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions. --- gas/ChangeLog | 8 ++ gas/config/bfin-defs.h | 19 ++++ gas/config/bfin-parse.y | 13 ++- gas/testsuite/ChangeLog | 6 ++ gas/testsuite/gas/bfin/expected_move_errors.l | 1 + gas/testsuite/gas/bfin/expected_move_errors.s | 1 + gas/testsuite/gas/bfin/move.d | 94 +++++++++---------- gas/testsuite/gas/bfin/move.s | 1 - opcodes/ChangeLog | 10 ++ opcodes/bfin-dis.c | 24 ++++- 10 files changed, 126 insertions(+), 51 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 204d8bff2e..8ea492817c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2009-09-03 Jie Zhang + + * config/bfin-defs.h (IS_GENREG): Define. + (IS_DAGREG): Define. + (IS_SYSREG): Define. + * config/bfin-parse.y (asm_1): Check illegal register move + instructions. + 2009-09-03 Jie Zhang * config/bfin-parse.y (asm_1): Fix a typo. diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h index 8923b73f80..8846a02531 100644 --- a/gas/config/bfin-defs.h +++ b/gas/config/bfin-defs.h @@ -201,6 +201,25 @@ enum reg_class #define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1) #define IS_ALLREG(r) ((r).regno < T_NOGROUP) +#define IS_GENREG(r) \ + (IS_DREG (r) || IS_PREG (r) \ + || (r).regno == REG_A0x || (r).regno == REG_A0w \ + || (r).regno == REG_A1x || (r).regno == REG_A1w) + +#define IS_DAGREG(r) \ + (IS_IREG (r) || IS_MREG (r) || IS_BREG (r) || IS_LREG (r)) + +#define IS_SYSREG(r) \ + ((r).regno == REG_ASTAT || (r).regno == REG_SEQSTAT \ + || (r).regno == REG_SYSCFG || (r).regno == REG_RETI \ + || (r).regno == REG_RETX || (r).regno == REG_RETN \ + || (r).regno == REG_RETE || (r).regno == REG_RETS \ + || (r).regno == REG_LC0 || (r).regno == REG_LC1 \ + || (r).regno == REG_LT0 || (r).regno == REG_LT1 \ + || (r).regno == REG_LB0 || (r).regno == REG_LB1 \ + || (r).regno == REG_CYCLES || (r).regno == REG_CYCLES2 \ + || (r).regno == REG_EMUDAT) + /* Expression value macros. */ typedef enum diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y index 81bfef8b52..952859e945 100644 --- a/gas/config/bfin-parse.y +++ b/gas/config/bfin-parse.y @@ -1720,9 +1720,18 @@ asm_1: | REG ASSIGN REG { - if (IS_ALLREG ($1) && IS_ALLREG ($3)) + if ((IS_GENREG ($1) && IS_GENREG ($3)) + || (IS_GENREG ($1) && IS_DAGREG ($3)) + || (IS_DAGREG ($1) && IS_GENREG ($3)) + || (IS_DAGREG ($1) && IS_DAGREG ($3)) + || (IS_GENREG ($1) && $3.regno == REG_USP) + || ($1.regno == REG_USP && IS_GENREG ($3)) + || (IS_DREG ($1) && IS_SYSREG ($3)) + || (IS_PREG ($1) && IS_SYSREG ($3)) + || (IS_SYSREG ($1) && IS_DREG ($3)) + || (IS_SYSREG ($1) && IS_PREG ($3)) + || (IS_SYSREG ($1) && $3.regno == REG_USP)) { - notethat ("REGMV: allregs = allregs\n"); $$ = bfin_gen_regmv (&$3, &$1); } else diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 13c83336ed..0c8b3e44db 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2009-09-03 Jie Zhang + + * gas/bfin/expected_move_errors.s, + gas/bfin/expected_move_errors.l: Add "LC1 = I0;". + * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". + 2009-09-03 Jie Zhang * gas/bfin/expected_comparison_errors.l: Expect error on Line 13. diff --git a/gas/testsuite/gas/bfin/expected_move_errors.l b/gas/testsuite/gas/bfin/expected_move_errors.l index 9b8b1aa15b..9a9874611e 100644 --- a/gas/testsuite/gas/bfin/expected_move_errors.l +++ b/gas/testsuite/gas/bfin/expected_move_errors.l @@ -3,3 +3,4 @@ .*:4: Error: Cannot move A0 to high half of register. Input text was A0. .*:5: Error: Cannot move A1 to even register. .*:6: Error: Cannot move A0 to odd register. +.*:7: Error: Register mismatch. diff --git a/gas/testsuite/gas/bfin/expected_move_errors.s b/gas/testsuite/gas/bfin/expected_move_errors.s index d73525f935..91f55780ff 100644 --- a/gas/testsuite/gas/bfin/expected_move_errors.s +++ b/gas/testsuite/gas/bfin/expected_move_errors.s @@ -4,3 +4,4 @@ R0.H = A0; R0 = A1; R1 = A0; + LC1 = I0; diff --git a/gas/testsuite/gas/bfin/move.d b/gas/testsuite/gas/bfin/move.d index 1a83e25939..d81f81fe90 100644 --- a/gas/testsuite/gas/bfin/move.d +++ b/gas/testsuite/gas/bfin/move.d @@ -27,56 +27,56 @@ Disassembly of section .text: 26: 96 31 R2 = CYCLES; 28: 9f 31 R3 = CYCLES2; 2a: cf 31 R1 = EMUDAT; - 2c: 31 3d CYCLES = A0.W; - 2e: 7f 38 RETS = FP; - 30: e0 3d LT1 = USP; - 32: 72 38 ASTAT = P2; - 34: 08 c4 [0|3][0|f] c0 A0 = A1; - 38: 08 c4 [0|3][0|f] e0 A1 = A0; - 3c: 09 c4 00 20 A0 = R0; - 40: 09 c4 08 a0 A1 = R1; - 44: 8b c0 00 39 R4 = A0 \(FU\); - 48: 2f c1 00 19 R5 = A1 \(ISS2\); - 4c: 0b c0 80 39 R6 = A0; - 50: 0f c0 80 19 R7 = A1; - 54: 0f c0 80 39 R7 = A1, R6 = A0; - 58: 8f c0 00 38 R1 = A1, R0 = A0 \(FU\); + 2c: 7f 38 RETS = FP; + 2e: e0 3d LT1 = USP; + 30: 72 38 ASTAT = P2; + 32: 08 c4 [0|3][0|f] c0 A0 = A1; + 36: 08 c4 [0|3][0|f] e0 A1 = A0; + 3a: 09 c4 00 20 A0 = R0; + 3e: 09 c4 08 a0 A1 = R1; + 42: 8b c0 00 39 R4 = A0 \(FU\); + 46: 2f c1 00 19 R5 = A1 \(ISS2\); + 4a: 0b c0 80 39 R6 = A0; + 4e: 0f c0 80 19 R7 = A1; + 52: 0f c0 80 39 R7 = A1, R6 = A0; + 56: 8f c0 00 38 R1 = A1, R0 = A0 \(FU\); -0000005c : - 5c: 6a 07 IF CC R5 = P2; - 5e: b0 06 IF !CC SP = R0; +0000005a : + 5a: 6a 07 IF CC R5 = P2; + 5c: b0 06 IF !CC SP = R0; -00000060 : - 60: fa 42 R2 = R7.L \(Z\); - 62: c8 42 R0 = R1.L \(Z\); +0000005e : + 5e: fa 42 R2 = R7.L \(Z\); + 60: c8 42 R0 = R1.L \(Z\); -00000064 : - 64: 8d 42 R5 = R1.L \(X\); - 66: 93 42 R3 = R2.L \(X\); +00000062 : + 62: 8d 42 R5 = R1.L \(X\); + 64: 93 42 R3 = R2.L \(X\); -00000068 : - 68: 09 c4 28 40 A0.X = R5.L; - 6c: 09 c4 10 c0 A1.X = R2.L; - 70: 0a c4 [0|3][0|6] 00 R0.L = A0.X; - 74: 0a c4 [0|3][0|6] 4e R7.L = A1.X; - 78: 09 c4 18 00 A0.L = R3.L; - 7c: 09 c4 20 80 A1.L = R4.L; - 80: 29 c4 30 00 A0.H = R6.H; - 84: 29 c4 28 80 A1.H = R5.H; - 88: 83 c1 00 38 R0.L = A0 \(IU\); - 8c: 27 c0 40 18 R1.H = A1 \(S2RND\); - 90: 07 c0 40 18 R1.H = A1; - 94: 67 c1 80 38 R2.H = A1, R2.L = A0 \(IH\); - 98: 07 c0 80 38 R2.H = A1, R2.L = A0; - 9c: 47 c0 00 38 R0.H = A1, R0.L = A0 \(T\); - a0: 87 c0 00 38 R0.H = A1, R0.L = A0 \(FU\); - a4: 07 c1 00 38 R0.H = A1, R0.L = A0 \(IS\); - a8: 07 c0 00 38 R0.H = A1, R0.L = A0; +00000066 : + 66: 09 c4 28 40 A0.X = R5.L; + 6a: 09 c4 10 c0 A1.X = R2.L; + 6e: 0a c4 [0|3][0|6] 00 R0.L = A0.X; + 72: 0a c4 [0|3][0|6] 4e R7.L = A1.X; + 76: 09 c4 18 00 A0.L = R3.L; + 7a: 09 c4 20 80 A1.L = R4.L; + 7e: 29 c4 30 00 A0.H = R6.H; + 82: 29 c4 28 80 A1.H = R5.H; + 86: 83 c1 00 38 R0.L = A0 \(IU\); + 8a: 27 c0 40 18 R1.H = A1 \(S2RND\); + 8e: 07 c0 40 18 R1.H = A1; + 92: 67 c1 80 38 R2.H = A1, R2.L = A0 \(IH\); + 96: 07 c0 80 38 R2.H = A1, R2.L = A0; + 9a: 47 c0 00 38 R0.H = A1, R0.L = A0 \(T\); + 9e: 87 c0 00 38 R0.H = A1, R0.L = A0 \(FU\); + a2: 07 c1 00 38 R0.H = A1, R0.L = A0 \(IS\); + a6: 07 c0 00 38 R0.H = A1, R0.L = A0; -000000ac : - ac: 57 43 R7 = R2.B \(Z\); - ae: 48 43 R0 = R1.B \(Z\); +000000aa : + aa: 57 43 R7 = R2.B \(Z\); + ac: 48 43 R0 = R1.B \(Z\); -000000b0 : - b0: 4e 43 R6 = R1.B \(Z\); - b2: 65 43 R5 = R4.B \(Z\); +000000ae : + ae: 4e 43 R6 = R1.B \(Z\); + b0: 65 43 R5 = R4.B \(Z\); + ... diff --git a/gas/testsuite/gas/bfin/move.s b/gas/testsuite/gas/bfin/move.s index 253367159b..7eee721b71 100644 --- a/gas/testsuite/gas/bfin/move.s +++ b/gas/testsuite/gas/bfin/move.s @@ -23,7 +23,6 @@ move_register: R2 = Cycles; R3 = Cycles2; r1 = emudat; - CYCLES = A0.W; Rets = Fp; Lt1 = USP; ASTAT = P2; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index de8083c0a6..0cdc676e02 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2009-09-03 Jie Zhang + + * bfin-dis.c (IS_DREG): Define. + (IS_PREG): Define. + (IS_AREG): Define. + (IS_GENREG): Define. + (IS_DAGREG): Define. + (IS_SYSREG): Define. + (decode_REGMV_0): Check illegal register move instructions. + 2009-09-03 Dave Korn * Makefile.am (BUILD_LIBINTL): New variable. diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 0ab656483d..18887a9c81 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -432,9 +432,18 @@ static enum machine_registers decode_allregs[] = REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, - REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG, + REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, + REG_LASTREG, }; +#define IS_DREG(g,r) ((g) == 0) +#define IS_PREG(g,r) ((g) == 1) +#define IS_AREG(g,r) ((g) == 4 && (r) >= 0 && (r) < 4) +#define IS_GENREG(g,r) ((g) == 0 || (g) == 1 || IS_AREG (g, r)) +#define IS_DAGREG(g,r) ((g) == 2 || (g) == 3) +#define IS_SYSREG(g,r) \ + (((g) == 4 && ((r) == 6 || (r) == 7)) || (g) == 6 || (g) == 7) + #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x]) #define uimm16s4(x) fmtconst (c_uimm16s4, x, 0, outf) #define uimm16s4d(x) fmtconst (c_uimm16s4d, x, 0, outf) @@ -1324,6 +1333,19 @@ decode_REGMV_0 (TIword iw0, disassemble_info *outf) int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask); int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask); + if (!((IS_GENREG (gd, dst) && IS_GENREG (gs, src)) + || (IS_GENREG (gd, dst) && IS_DAGREG (gs, src)) + || (IS_DAGREG (gd, dst) && IS_GENREG (gs, src)) + || (IS_DAGREG (gd, dst) && IS_DAGREG (gs, src)) + || (IS_GENREG (gd, dst) && gs == 7 && src == 0) + || (gd == 7 && dst == 0 && IS_GENREG (gs, src)) + || (IS_DREG (gd, dst) && IS_SYSREG (gs, src)) + || (IS_PREG (gd, dst) && IS_SYSREG (gs, src)) + || (IS_SYSREG (gd, dst) && IS_DREG (gs, src)) + || (IS_SYSREG (gd, dst) && IS_PREG (gs, src)) + || (IS_SYSREG (gd, dst) && gs == 7 && src == 0))) + return 0; + OUTS (outf, allregs (dst, gd)); OUTS (outf, " = "); OUTS (outf, allregs (src, gs)); -- 2.34.1