From 7e3670d611cbfb643179b307fb41ea37f2042cb8 Mon Sep 17 00:00:00 2001 From: Fred Fish Date: Sat, 14 Dec 1996 17:52:07 +0000 Subject: [PATCH] * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. * v850.h: Fix comment, v850_operand not powerpc_operand. --- include/opcode/ChangeLog | 15 ++++++ include/opcode/mn10200.h | 106 +++++++++++++++++++++++++++++++++++++++ include/opcode/v850.h | 16 +++++- 3 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 include/opcode/mn10200.h diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 628bc59bbb..32993b56a5 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,18 @@ +Sat Dec 14 10:48:31 1996 Fred Fish + + * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. + * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. + * v850.h: Fix comment, v850_operand not powerpc_operand. + +Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) + + * mn10200.h: Flesh out structures and definitions needed by + the mn10200 assembler & disassembler. + +Tue Nov 26 10:46:56 1996 Ian Lance Taylor + + * mips.h: Add mips16 definitions. + Mon Nov 25 17:56:54 1996 J.T. Conklin * m68k.h: Document new <, >, m, n, o and p operand specifiers. diff --git a/include/opcode/mn10200.h b/include/opcode/mn10200.h new file mode 100644 index 0000000000..5b610eb84a --- /dev/null +++ b/include/opcode/mn10200.h @@ -0,0 +1,106 @@ +/* mn10200.h -- Header file for Matsushita 10200 opcode table + Copyright 1996 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef MN10200_H +#define MN10200_H + +/* The opcode table is an array of struct mn10200_opcode. */ + +struct mn10200_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* The format of this opcode. */ + unsigned char format; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10200_opcode mn10200_opcodes[]; +extern const int mn10200_num_opcodes; + + +/* The operands table is an array of struct mn10200_operand. */ + +struct mn10200_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10200_opcodes table. */ + +extern const struct mn10200_operand mn10200_operands[]; + +/* Values defined for the flags field of a struct mn10200_operand. */ +#define MN10200_OPERAND_DREG 0x1 + +#define MN10200_OPERAND_AREG 0x2 + +#define MN10200_OPERAND_PSW 0x4 + +#define MN10200_OPERAND_MDR 0x8 + +#define MN10200_OPERAND_SIGNED 0x10 + +#define MN10200_OPERAND_PROMOTE 0x20 + +#define MN10200_OPERAND_PAREN 0x40 + +#define MN10200_OPERAND_REPEATED 0x80 + +#define MN10200_OPERAND_EXTENDED 0x100 + +#define MN10200_OPERAND_PCREL 0x400 + +#define MN10200_OPERAND_MEMADDR 0x800 + +#define FMT_1 1 +#define FMT_2 2 +#define FMT_3 3 +#define FMT_4 4 +#define FMT_5 5 +#define FMT_6 6 +#define FMT_7 7 +#endif /* MN10200_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h index f1100d2673..e7965c297a 100644 --- a/include/opcode/v850.h +++ b/include/opcode/v850.h @@ -42,6 +42,9 @@ struct v850_opcode operand table. They appear in the order which the operands must appear in assembly code, and are terminated by a zero. */ unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; }; /* The table itself is sorted by major opcode number, and is otherwise @@ -51,7 +54,7 @@ extern const struct v850_opcode v850_opcodes[]; extern const int v850_num_opcodes; -/* The operands table is an array of struct powerpc_operand. */ +/* The operands table is an array of struct v850_operand. */ struct v850_operand { @@ -122,4 +125,15 @@ extern const struct v850_operand v850_operands[]; /* This operand takes signed values */ #define V850_OPERAND_SIGNED 0x08 +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x10 + +/* This operand is a PC displacement */ +#define V850_OPERAND_DISP 0x20 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?) */ +#define V850_OPERAND_RELAX 0x40 + #endif /* V850_H */ -- 2.34.1