From b2e3f8442ac20d4c63e2a474117e761be1fd93fa Mon Sep 17 00:00:00 2001 From: Martin Hunt Date: Wed, 19 Feb 1997 01:53:26 +0000 Subject: [PATCH] Tue Feb 18 17:43:43 1997 Martin M. Hunt * Makefile.in: Added d30v object files. * configure: (bfd_d30v_arch) Rebuilt. * configure.in: (bfd_d30v_arch) Added new case. * d30v-dis.c: New file. * d30v-opc.c: New file. * disassemble.c (disassembler) Add entry for d30v. --- opcodes/.Sanitize | 36 ++++ opcodes/ChangeLog | 11 ++ opcodes/Makefile.in | 7 +- opcodes/configure | 6 + opcodes/configure.in | 11 +- opcodes/d30v-dis.c | 345 +++++++++++++++++++++++++++++++++++ opcodes/d30v-opc.c | 414 ++++++++++++++++++++++++++++++++++++++++++ opcodes/disassemble.c | 40 +++- 8 files changed, 859 insertions(+), 11 deletions(-) create mode 100644 opcodes/d30v-dis.c create mode 100644 opcodes/d30v-opc.c diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize index 536f4575d9..4858844418 100644 --- a/opcodes/.Sanitize +++ b/opcodes/.Sanitize @@ -31,6 +31,14 @@ else lose_these_too="${d10v_files} ${lose_these_too}" fi +d30v_files="d30v-dis.c d30v-opc.c" + +if ( echo $* | grep keep\-d30v > /dev/null ) ; then + keep_these_too="${d30v_files} ${keep_these_too}" +else + lose_these_too="${d30v_files} ${lose_these_too}" +fi + v850_files="v850-opc.c v850-dis.c" if ( echo $* | grep keep\-v850 > /dev/null ) ; then @@ -163,6 +171,34 @@ else done fi +d30v_files="ChangeLog Makefile.in configure.in configure disassemble.c" +if ( echo $* | grep keep\-d30v > /dev/null ) ; then + for i in $d30v_files ; do + if test ! -d $i && (grep sanitize-d30v $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Keeping d30v stuff in $i + fi + fi + done +else + for i in $d30v_files ; do + if test ! -d $i && (grep sanitize-d30v $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Removing traces of \"d30v\" from $i... + fi + cp $i new + sed '/start\-sanitize\-d30v/,/end-\sanitize\-d30v/d' < $i > new + if [ -n "${safe}" -a ! -f .Recover/$i ] ; then + if [ -n "${verbose}" ] ; then + echo Caching $i in .Recover... + fi + mv $i .Recover + fi + mv new $i + fi + done +fi + v850_files="ChangeLog Makefile.in configure.in configure disassemble.c" if ( echo $* | grep keep\-v850 > /dev/null ) ; then for i in $v850_files ; do diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 774597e60a..3444eda83e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +start-sanitize-d30v +Tue Feb 18 17:43:43 1997 Martin M. Hunt + + * Makefile.in: Added d30v object files. + * configure: (bfd_d30v_arch) Rebuilt. + * configure.in: (bfd_d30v_arch) Added new case. + * d30v-dis.c: New file. + * d30v-opc.c: New file. + * disassemble.c (disassembler) Add entry for d30v. + +end-sanitize-d30v start-sanitize-tic80 Tue Feb 18 16:32:08 1997 Fred Fish diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 5bf753cfce..d2542f54ae 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -83,6 +83,9 @@ ALL_MACHINES = a29k-dis.o alpha-dis.o alpha-opc.o h8300-dis.o h8500-dis.o \ $(start-sanitize-d10v) \ d10v-dis.o d10v-opc.o \ $(end-sanitize-d10v) \ + $(start-sanitize-d30v) \ + d30v-dis.o d30v-opc.o \ + $(end-sanitize-d30v) \ hppa-dis.o i386-dis.o i960-dis.o m68k-dis.o m68k-opc.o \ m88k-dis.o mn10200-dis.o mn10200-opc.o mn10300-dis.o \ mn10300-opc.o mips-dis.o mips-opc.o mips16-opc.o sh-dis.o \ @@ -109,7 +112,7 @@ FLAGS_TO_PASS = \ "INSTALL_DATA=$(INSTALL_DATA)" \ "INSTALL_PROGRAM=$(INSTALL_PROGRAM)" -ALL_CFLAGS = $(CSEARCH) @HDEFINES@ $(CFLAGS) +ALL_CFLAGS = -D_GNU_SOURCE $(CSEARCH) @HDEFINES@ $(CFLAGS) .c.o: if [ -n "$(PICFLAG)" ]; then \ @@ -306,7 +309,7 @@ config.status: configure $(srcdir)/../bfd/configure.host $(srcdir)/../bfd/config $(SHELL) config.status --recheck dep: $(CFILES) - mkdep $(CFLAGS) $? + mkdep $(ALL_CFLAGS) $? stamp-picdir: if [ -n "$(PICFLAG)" ] && [ ! -d pic ]; then \ diff --git a/opcodes/configure b/opcodes/configure index f8517fee47..6e84417413 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -1176,6 +1176,9 @@ if test x${all_targets} = xfalse ; then # start-sanitize-d10v bfd_d10v_arch) ta="$ta d10v-dis.o d10v-opc.o" ;; # end-sanitize-d10v +# start-sanitize-d30v + bfd_d30v_arch) ta="$ta d30v-dis.o d30v-opc.o" ;; +# end-sanitize-d30v bfd_h8300_arch) ta="$ta h8300-dis.o" ;; bfd_h8500_arch) ta="$ta h8500-dis.o" ;; bfd_hppa_arch) ta="$ta hppa-dis.o" ;; @@ -1195,6 +1198,9 @@ if test x${all_targets} = xfalse ; then bfd_sh_arch) ta="$ta sh-dis.o" ;; bfd_sparc_arch) ta="$ta sparc-dis.o sparc-opc.o" ;; bfd_tahoe_arch) ;; +# start-sanitize-tic80 + bfd_tic80_arch) ta="$ta tic80-dis.o tic80-opc.o" ;; +# end-sanitize-tic80 # start-sanitize-v850 bfd_v850_arch) ta="$ta v850-opc.o v850-dis.o" ;; # end-sanitize-v850 diff --git a/opcodes/configure.in b/opcodes/configure.in index 76c576821e..9785ba22c0 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -166,6 +166,9 @@ if test x${all_targets} = xfalse ; then # start-sanitize-d10v bfd_d10v_arch) ta="$ta d10v-dis.o d10v-opc.o" ;; # end-sanitize-d10v +# start-sanitize-d30v + bfd_d30v_arch) ta="$ta d30v-dis.o d30v-opc.o" ;; +# end-sanitize-d30v bfd_h8300_arch) ta="$ta h8300-dis.o" ;; bfd_h8500_arch) ta="$ta h8500-dis.o" ;; bfd_hppa_arch) ta="$ta hppa-dis.o" ;; @@ -174,8 +177,9 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.o" ;; bfd_m68k_arch) ta="$ta m68k-dis.o m68k-opc.o" ;; bfd_m88k_arch) ta="$ta m88k-dis.o" ;; - bfd_mips_arch) ta="$ta mips-dis.o mips-opc.o" ;; - bfd_mn10x00_arch) ta="$ta mn10x00-dis.o mn10x00-opc.o" ;; + bfd_mips_arch) ta="$ta mips-dis.o mips-opc.o mips16-opc.o" ;; + bfd_mn10200_arch) ta="$ta mn10200-dis.o mn10200-opc.o" ;; + bfd_mn10300_arch) ta="$ta mn10300-dis.o mn10300-opc.o" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.o" ;; bfd_powerpc_arch) ta="$ta ppc-dis.o ppc-opc.o" ;; bfd_pyramid_arch) ;; @@ -184,6 +188,9 @@ if test x${all_targets} = xfalse ; then bfd_sh_arch) ta="$ta sh-dis.o" ;; bfd_sparc_arch) ta="$ta sparc-dis.o sparc-opc.o" ;; bfd_tahoe_arch) ;; +# start-sanitize-tic80 + bfd_tic80_arch) ta="$ta tic80-dis.o tic80-opc.o" ;; +# end-sanitize-tic80 # start-sanitize-v850 bfd_v850_arch) ta="$ta v850-opc.o v850-dis.o" ;; # end-sanitize-v850 diff --git a/opcodes/d30v-dis.c b/opcodes/d30v-dis.c new file mode 100644 index 0000000000..91262adce8 --- /dev/null +++ b/opcodes/d30v-dis.c @@ -0,0 +1,345 @@ +/* Disassemble D30V instructions. + Copyright (C) 1997 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "opcode/d30v.h" +#include "dis-asm.h" + +#define PC_MASK 0xFFFFFFFF + +static int lookup_opcode PARAMS (( struct d30v_insn *insn, long num, int is_long )); +static void print_insn PARAMS (( struct disassemble_info *info, bfd_vma memaddr, long long num, + struct d30v_insn *insn, int is_long )); +static int extract_value PARAMS (( long long num, struct d30v_operand *oper, int is_long )); + +int +print_insn_d30v (memaddr, info) + bfd_vma memaddr; + struct disassemble_info *info; +{ + int status, i; + bfd_byte buffer[12]; + unsigned long in1,in2; + struct d30v_insn insn; + long long num; + + insn.form = (struct d30v_format *)NULL; + + status = (*info->read_memory_func) (memaddr, buffer, 8, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + info->bytes_per_line = 8; + info->bytes_per_chunk = 4; + info->display_endian = BFD_ENDIAN_BIG; + in1 = bfd_getb32 (buffer); + in2 = bfd_getb32 (buffer+4); + + if (in1 & in2 & FM01) + { + /* LONG instruction */ + if (!lookup_opcode(&insn, in1, 1)) + { + (*info->fprintf_func) (info->stream, ".long\t0x%x,0x%x",in1,in2); + return 8; + } + num = (long long)in1 << 32 | in2; + print_insn(info, memaddr, num, &insn, 1); + } + else + { + num = in1; + if (!lookup_opcode(&insn, in1, 0)) + (*info->fprintf_func) (info->stream, ".long\t0x%x",in1); + else + print_insn(info, memaddr, num, &insn, 0); + + switch ( ((in1>>31)<<1) | (in2>>31) ) + { + case 0: + (*info->fprintf_func) (info->stream, "\t||\t"); + break; + case 1: + (*info->fprintf_func) (info->stream, "\t->\t"); + break; + case 2: + (*info->fprintf_func) (info->stream, "\t<-\t"); + default: + break; + } + + insn.form = (struct d30v_format *)NULL; + num = in2; + if (!lookup_opcode(&insn, in2, 0)) + (*info->fprintf_func) (info->stream, ".long\t0x%x",in2); + else + print_insn(info, memaddr, num, &insn, 0); + + } + return 8; +} + + +static int +lookup_opcode (insn, num, is_long) + struct d30v_insn *insn; + long num; + int is_long; +{ + int i=0, index; + struct d30v_format *f; + struct d30v_opcode *op = (struct d30v_opcode *)d30v_opcode_table; + int op1 = (num >> 25) & 0x7; + int op2 = (num >> 20) & 0x1f; + int mod = (num >> 18) & 0x3; + + /* find the opcode */ + do { + if ((op->op1 == op1) && (op->op2 == op2)) + break; + op++; + } while (op->name); + + if (!op || !op->name) + return 0; + + while (op->op1 == op1 && op->op2 == op2) + { + /* scan through all the formats for the opcode */ + while (index = op->format[i++]) + { + f = (struct d30v_format *)&d30v_format_table[index]; + while (f->form == index) + { + if ((!is_long || f->form >= LONG) && (f->modifier == mod)) + { + insn->form = f; + break; + } + f++; + } + if (insn->form) + break; + } + if (insn->form) + break; + op++; + i=0; + } + if (insn->form == NULL) + return 0; + + insn->op = op; + insn->ecc = (num >> 28) & 0x7; + return 1; +} + + +static void +print_insn ( info, memaddr, num, insn, is_long ) + struct disassemble_info *info; + bfd_vma memaddr; + long long num; + struct d30v_insn *insn; + int is_long; +{ + char buffer[128]; + int val, opnum, need_comma=0; + struct d30v_operand *oper; + int i, match, opind=0, need_paren=0, found_control=0; + + (*info->fprintf_func) (info->stream, "%s",insn->op->name); + + /* check for CMP or CMPU */ + if (d30v_operand_table[insn->form->operands[0]].flags & OPERAND_NAME) + { + opind++; + val = extract_value(num,(struct d30v_operand *)&d30v_operand_table[insn->form->operands[0]],is_long); + (*info->fprintf_func) (info->stream, "%s",d30v_cc_names[val]); + } + + if (insn->ecc) + (*info->fprintf_func) (info->stream, "/%s",d30v_ecc_names[insn->ecc]); + + (*info->fprintf_func) (info->stream, "\t"); + + while (opnum = insn->form->operands[opind++]) + { + oper = (struct d30v_operand *)&d30v_operand_table[opnum]; + + if (need_comma && oper->flags != OPERAND_PLUS && oper->flags != OPERAND_MINUS) + { + need_comma=0; + (*info->fprintf_func) (info->stream, ", "); + } + + if (oper->flags == OPERAND_ATMINUS) + { + (*info->fprintf_func) (info->stream, "@-"); + continue; + } + if (oper->flags == OPERAND_MINUS) + { + (*info->fprintf_func) (info->stream, "-"); + continue; + } + if (oper->flags == OPERAND_PLUS) + { + (*info->fprintf_func) (info->stream, "+"); + continue; + } + if (oper->flags == OPERAND_ATSIGN) + { + (*info->fprintf_func) (info->stream, "@"); + continue; + } + if (oper->flags == OPERAND_ATPAR) + { + (*info->fprintf_func) (info->stream, "@("); + need_paren = 1; + continue; + } + + if (oper->flags == OPERAND_SPECIAL) + continue; + + val = extract_value(num, oper, is_long); + + if (oper->flags & OPERAND_REG) + { + match = 0; + if (oper->flags & OPERAND_CONTROL) + { + struct d30v_operand *oper3 = + (struct d30v_operand *)&d30v_operand_table[insn->form->operands[2]]; + int id = extract_value (num, oper3, is_long ); + found_control = 1; + switch ( id ) + { + case 0: + val |= OPERAND_CONTROL; + break; + case 1: + case 2: + val = OPERAND_CONTROL + MAX_CONTROL_REG + id; + break; + case 3: + val |= OPERAND_FLAG; + break; + default: + fprintf(stderr,"illegal id (%d)\n",id); + } + } + else if (oper->flags & OPERAND_ACC) + val |= OPERAND_ACC; + else if (oper->flags & OPERAND_FLAG) + val |= OPERAND_FLAG; + for (i=0;ifprintf_func) (info->stream, "%s",pre_defined_registers[i].pname); + else + (*info->fprintf_func) (info->stream, "%s",pre_defined_registers[i].name); + match=1; + break; + } + } + if (match==0) + { + /* this would only get executed if a register was not in the + register table */ + (*info->fprintf_func) (info->stream, "",val & 0x3F); + } + } + else if (insn->op->reloc_flag == RELOC_PCREL) + { + long max; + int neg=0; + max = (1 << (oper->bits - 1)); + if (val & max) + { + if (oper->bits == 32) + val = -val; + else + val = -val & ((1 << oper->bits)-1); + neg = 1; + } + if (neg) + (*info->print_address_func) ((memaddr - val) & PC_MASK, info); + else + (*info->print_address_func) ((memaddr + val) & PC_MASK, info); + } + else if (insn->op->reloc_flag == RELOC_ABS) + { + (*info->print_address_func) (val, info); + } + else + { + if (oper->flags & OPERAND_SIGNED) + { + int max = (1 << (oper->bits - 1)); + if (val & max) + { + val = -val & ((1 << oper->bits) - 1); + (*info->fprintf_func) (info->stream, "-"); + } + } + (*info->fprintf_func) (info->stream, "0x%x",val); + } + /* if there is another operand, then write a comma and space */ + if (insn->form->operands[opind] && !(found_control && opind == 2)) + need_comma = 1; + } + if (need_paren) + (*info->fprintf_func) (info->stream, ")"); +} + + + +static int +extract_value (num, oper, is_long) + long long num; + struct d30v_operand *oper; + int is_long; +{ + int val; + int shift = 12 - oper->position; + int mask = (0xFFFFFFFF >> (32 - oper->bits)); + + if (is_long) + { + if (oper->bits == 32) + { + /* piece together 32-bit constant */ + val = num & 0x3FFFF | (num & 0xFF00000) >> 2 | + (num & 0x3F00000000LL) >> 6; + } + else + val = (num >> (32 + shift)) & mask; + } + else + val = (num >> shift) & mask; + + if (oper->flags & OPERAND_SHIFT) + val <<= 3; + + return val; +} diff --git a/opcodes/d30v-opc.c b/opcodes/d30v-opc.c new file mode 100644 index 0000000000..cdc8e0e437 --- /dev/null +++ b/opcodes/d30v-opc.c @@ -0,0 +1,414 @@ +/* d30v-opc.c -- D30V opcode list + Copyright 1997 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +2, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#include +#include "ansidecl.h" +#include "opcode/d30v.h" + + +/* This table is sorted. */ +/* If you add anything, it MUST be in alphabetical order */ +/* The first field is the name the assembler uses when looking */ +/* up orcodes. The second field is the name the disassembler will use. */ +/* This allows the assembler to assemble references to r63 (for example) */ +/* or "sp". The disassembler will always use the preferred form (sp) */ +const struct pd_reg pre_defined_registers[] = +{ + { "a0", NULL, OPERAND_ACC+0 }, + { "a1", NULL, OPERAND_ACC+1 }, + { "bpc", NULL, OPERAND_CONTROL+2 }, + { "bpsw", NULL, OPERAND_CONTROL+3 }, + { "c", "c", OPERAND_FLAG+7 }, + { "cr0", "pc", OPERAND_CONTROL }, + { "cr1", "psw", OPERAND_CONTROL+1 }, + { "cr10", "mod_e", OPERAND_CONTROL+10 }, + { "cr11", "iba", OPERAND_CONTROL+11 }, + { "cr12", NULL, OPERAND_CONTROL+12 }, + { "cr13", NULL, OPERAND_CONTROL+13 }, + { "cr14", NULL, OPERAND_CONTROL+14 }, + { "cr15", NULL, OPERAND_CONTROL+15 }, + { "cr2", "bpc", OPERAND_CONTROL+2 }, + { "cr3", "bpsw", OPERAND_CONTROL+3 }, + { "cr4", NULL, OPERAND_CONTROL+4 }, + { "cr5", NULL, OPERAND_CONTROL+5 }, + { "cr6", "rpt_c", OPERAND_CONTROL+6 }, + { "cr7", "rpt_s", OPERAND_CONTROL+7 }, + { "cr8", "rpt_e", OPERAND_CONTROL+8 }, + { "cr9", "mod_s", OPERAND_CONTROL+9 }, + { "f0", NULL, OPERAND_FLAG+0 }, + { "f1", NULL, OPERAND_FLAG+1 }, + { "f2", NULL, OPERAND_FLAG+2 }, + { "f3", NULL, OPERAND_FLAG+3 }, + { "f4", "s", OPERAND_FLAG+4 }, + { "f5", "v", OPERAND_FLAG+5 }, + { "f6", "va", OPERAND_FLAG+6 }, + { "f7", "c", OPERAND_FLAG+7 }, + { "iba", NULL, OPERAND_CONTROL+11 }, + { "link", "r62", 62 }, + { "mod_e", NULL, OPERAND_CONTROL+10 }, + { "mod_s", NULL, OPERAND_CONTROL+9 }, + { "pc", NULL, OPERAND_CONTROL+0 }, + { "psw", NULL, OPERAND_CONTROL+1 }, + { "pswh", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+2 }, + { "pswl", NULL, OPERAND_CONTROL+MAX_CONTROL_REG+1 }, + { "r0", "0", 0 }, + { "r1", NULL, 1 }, + { "r10", NULL, 10 }, + { "r11", NULL, 11 }, + { "r12", NULL, 12 }, + { "r13", NULL, 13 }, + { "r14", NULL, 14 }, + { "r15", NULL, 15 }, + { "r16", NULL, 16 }, + { "r17", NULL, 17 }, + { "r18", NULL, 18 }, + { "r19", NULL, 19 }, + { "r2", NULL, 2 }, + { "r20", NULL, 20 }, + { "r21", NULL, 21 }, + { "r22", NULL, 22 }, + { "r23", NULL, 23 }, + { "r24", NULL, 24 }, + { "r25", NULL, 25 }, + { "r26", NULL, 26 }, + { "r27", NULL, 27 }, + { "r28", NULL, 28 }, + { "r29", NULL, 29 }, + { "r3", NULL, 3 }, + { "r30", NULL, 30 }, + { "r31", NULL, 31 }, + { "r32", NULL, 32 }, + { "r33", NULL, 33 }, + { "r34", NULL, 34 }, + { "r35", NULL, 35 }, + { "r36", NULL, 36 }, + { "r37", NULL, 37 }, + { "r38", NULL, 38 }, + { "r39", NULL, 39 }, + { "r4", NULL, 4 }, + { "r40", NULL, 40 }, + { "r41", NULL, 41 }, + { "r42", NULL, 42 }, + { "r43", NULL, 43 }, + { "r44", NULL, 44 }, + { "r45", NULL, 45 }, + { "r46", NULL, 46 }, + { "r47", NULL, 47 }, + { "r48", NULL, 48 }, + { "r49", NULL, 49 }, + { "r5", NULL, 5 }, + { "r50", NULL, 50 }, + { "r51", NULL, 51 }, + { "r52", NULL, 52 }, + { "r53", NULL, 53 }, + { "r54", NULL, 54 }, + { "r55", NULL, 55 }, + { "r56", NULL, 56 }, + { "r57", NULL, 57 }, + { "r58", NULL, 58 }, + { "r59", NULL, 59 }, + { "r6", NULL, 6 }, + { "r60", NULL, 60 }, + { "r61", NULL, 61 }, + { "r62", "link", 62 }, + { "r63", "sp", 63 }, + { "r7", NULL, 7 }, + { "r8", NULL, 8 }, + { "r9", NULL, 9 }, + { "rpt_c", NULL, OPERAND_CONTROL+6 }, + { "rpt_e", NULL, OPERAND_CONTROL+8 }, + { "rpt_s", NULL, OPERAND_CONTROL+7 }, + { "s", NULL, OPERAND_FLAG+4 }, + { "sp", NULL, 63 }, + { "v", NULL, OPERAND_FLAG+5 }, + { "va", NULL, OPERAND_FLAG+6 }, +}; + +int +reg_name_cnt() +{ + return (sizeof(pre_defined_registers) / sizeof(struct pd_reg)); +} + +/* OPCODE TABLE */ +/* The format of this table is defined in opcode/d30v.h */ +const struct d30v_opcode d30v_opcode_table[] = { + { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 }, + { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 }, + { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, + { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER, 0, 0, 0 }, + { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER, 0, 0, 0 }, + { "bra", BRA, 0, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratnz", BRA, 0x4, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bratzr", BRA, 0x4, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_PCREL }, + { "bset", LOGIC, 0x2, { SHORT_A }, EITHER, 0, 0, 0 }, + { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtnz", BRA, 0x6, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "bsrtzr", BRA, 0x6, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_PCREL }, + { "btst", LOGIC, 0, { SHORT_AF }, EITHER, 0, FLAG_X, 0 }, + { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 }, + { "cmpu", LOGIC, 0xD, { SHORT_CMP, LONG_CMP }, EITHER, 0, FLAG_X, 0 }, + { "dbra", BRA, 0x10, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL }, + { "dbrai", BRA, 0x14, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_PCREL }, + { "dbsr", BRA, 0x12, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL }, + { "dbsri", BRA, 0x16, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_PCREL }, + { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS }, + { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP, FLAG_RP, RELOC_ABS }, + { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS }, + { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR, FLAG_RP, RELOC_ABS }, + { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS }, + { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS }, + { "ld2h", IMEM, 0x3, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ld2w", IMEM, 0x6, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ld4bh", IMEM, 0x5, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ld4bhu", IMEM, 0xd, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 }, + { "mac0", IALU2, 0x14, { SHORT_A }, IU, 0, 0, 0 }, + { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, 0, 0, 0 }, + { "macs0", IALU2, 0x15, { SHORT_A }, IU, 0, 0, 0 }, + { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, 0, 0, 0 }, + { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 }, + { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 }, + { "msub0", IALU2, 0x16, { SHORT_A }, IU, 0, 0, 0 }, + { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, 0, 0, 0 }, + { "msubs0", IALU2, 0x17, { SHORT_A }, IU, 0, 0, 0 }, + { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, 0, 0, 0 }, + { "mul", IALU2, 0x10, { SHORT_A }, IU, 0, 0, 0 }, + { "mul2h", IALU2, 0, { SHORT_A }, IU, 0, 0, 0 }, + { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, 0, 0, 0 }, + { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, 0, 0, 0 }, + { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, 0, 0, 0 }, + { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, 0, 0, 0 }, + { "mulx", IALU2, 0x18, { SHORT_AA }, IU, 0, 0, 0 }, + { "mulx2h", IALU2, 0x1, { SHORT_A }, IU, 0, 0, 0 }, + { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, 0, 0, 0 }, + { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 }, + { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "mvtacc", IALU2, 0xf, { SHORT_AA }, IU, 0, 0, 0 }, + { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 }, + { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 }, + { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 }, + { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, FLAG_X, FLAG_X, 0 }, + { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, + { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM, FLAG_SM, 0 }, + { "repeat", BRA, 0x18, { SHORT_D1, LONG_2 }, MU, FLAG_RP, FLAG_RP, 0 }, + { "repeati", BRA, 0x1a, { SHORT_D2, LONG_D }, MU, FLAG_RP, FLAG_RP, 0 }, + { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 }, + { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 }, + { "sat", IALU2, 0x8, { SHORT_A }, IU, 0, 0, 0 }, + { "sat2h", IALU2, 0x9, { SHORT_A }, IU, 0, 0, 0 }, + { "sathl", IALU2, 0x1c, { SHORT_A }, IU, 0, 0, 0 }, + { "sathh", IALU2, 0x1d, { SHORT_A }, IU, 0, 0, 0 }, + { "satz", IALU2, 0xa, { SHORT_A }, IU, 0, 0, 0 }, + { "satz2h", IALU2, 0xb, { SHORT_A }, IU, 0, 0, 0 }, + { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 }, + { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 }, + { "src", LOGIC, 0x16, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, + { "srl2h", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 }, + { "st2h", IMEM, 0x13, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "st2w", IMEM, 0x16, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "st4hb", IMEM, 0x15, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM, 0 }, + { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 }, + { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 }, + { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 }, + { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, 0, FLAG_SM, 0 }, + { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 }, + { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, FLAG_X, FLAG_X, 0 }, + { NULL, 0, 0, { 0 }, 0, 0, 0, 0 }, +}; + + +/* now define the operand types */ +/* format is length, bits, position, flags */ +const struct d30v_operand d30v_operand_table[] = +{ +#define UNUSED (0) + { 0, 0, 0, 0 }, +#define Ra (UNUSED + 1) + { 6, 6, 0, OPERAND_REG|OPERAND_DEST }, +#define Rb (Ra + 1) + { 6, 6, 6, OPERAND_REG }, +#define Rc (Rb + 1) + { 6, 6, 12, OPERAND_REG }, +#define Aa (Rc + 1) + { 6, 1, 0, OPERAND_ACC|OPERAND_REG|OPERAND_DEST }, +#define Ab (Aa + 1) + { 6, 1, 6, OPERAND_ACC|OPERAND_REG }, +#define IMM5 (Ab + 1) + { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, +#define IMM5S3 (IMM5 + 1) + { 6, 5, 12, OPERAND_NUM|OPERAND_SIGNED }, +#define IMM6 (IMM5S3 + 1) + { 6, 6, 12, OPERAND_NUM|OPERAND_SIGNED }, +#define IMM12 (IMM6 + 1) + { 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED }, +#define IMM12S3 (IMM12 + 1) + { 12, 12, 6, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, +#define IMM18S3 (IMM12S3 + 1) + { 18, 18, 12, OPERAND_NUM|OPERAND_SIGNED|OPERAND_SHIFT }, +#define IMM32 (IMM18S3 + 1) + { 32, 32, 0, OPERAND_NUM }, +#define Fa (IMM32 + 1) + { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST }, +#define Fb (Fa + 1) + { 6, 3, 6, OPERAND_REG | OPERAND_FLAG }, +#define Fc (Fb + 1) + { 6, 3, 12, OPERAND_REG | OPERAND_FLAG }, +#define ATSIGN (Fc + 1) + { 0, 0, 0, OPERAND_ATSIGN}, +#define ATPAR (ATSIGN + 1) /* "@(" */ + { 0, 0, 0, OPERAND_ATPAR}, +#define PLUS (ATPAR + 1) /* postincrement */ + { 0, 0, 0, OPERAND_PLUS}, +#define MINUS (PLUS + 1) /* postdecrement */ + { 0, 0, 0, OPERAND_MINUS}, +#define ATMINUS (MINUS + 1) /* predecrement */ + { 0, 0, 0, OPERAND_ATMINUS}, +#define Ca (ATMINUS + 1) /* control register */ + { 6, 4, 0, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST}, +#define Cb (Ca + 1) /* control register */ + { 6, 4, 6, OPERAND_REG|OPERAND_CONTROL}, +#define CC (Cb + 1) /* condition code (CMPcc and CMPUcc) */ + { 3, 3, -3, OPERAND_NAME}, +#define Fa2 (CC + 1) /* flag register (CMPcc and CMPUcc) */ + { 3, 3, 0, OPERAND_REG|OPERAND_FLAG|OPERAND_DEST}, +#define Fake (Fa2 + 1) /* place holder for "id" field in mvfsys and mvtsys */ + { 6, 2, 12, OPERAND_SPECIAL}, +}; + +/* now we need to define the instruction formats */ +const struct d30v_format d30v_format_table[] = +{ + { 0, 0, { 0 } }, + { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */ + { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */ + { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */ + { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,@(Rb-,Rc) */ + { SHORT_A, 0, { Ra, Rb, Rc } }, /* Ra,Rb,Rc */ + { SHORT_A, 2, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 */ + { SHORT_B1, 0, { Rc } }, /* Rc */ + { SHORT_B2, 2, { IMM18S3 } }, /* imm18 */ + { SHORT_B3, 0, { Ra, Rc } }, /* Ra,Rc */ + { SHORT_B3, 2, { Ra, IMM12 } }, /* Ra,imm12 */ + { SHORT_B3b, 1, { Ra, Rc } }, /* Ra,Rc */ + { SHORT_B3b, 3, { Ra, IMM12 } }, /* Ra,imm12 */ + { SHORT_D1, 0, { Ra, Rc } }, /* Ra,Rc */ + { SHORT_D1, 2, { Ra, IMM12S3 } }, /* Ra,imm12s3 */ + { SHORT_D2, 0, { IMM6, Rc } }, /* imm6,Rc */ + { SHORT_D2, 2, { IMM6, IMM12S3 } }, /* imm6,imm12s3 */ + { SHORT_U, 0, { Ra, Rb } }, /* Ra,Rb */ + { SHORT_U, 2, { Ra, IMM12 } }, /* Ra,imm12 (repeat) */ + { SHORT_F, 0, { Fa, Fb, Fc } }, /* Fa,Fb,Fc (orfg, xorfg) */ + { SHORT_F, 2, { Fa, Fb, IMM6 } }, /* Fa,Fb,imm6 */ + { SHORT_AF, 0, { Fa, Rb, Rc } }, /* Fa,Rb,Rc */ + { SHORT_AF, 2, { Fa, Rb, IMM6 } }, /* Fa,Rb,imm6 */ + { SHORT_T, 2, { IMM5S3 } }, /* imm5s3 (trap) */ + { SHORT_A5, 2, { Ra, Rb, IMM5 } }, /* Ra,Rb,imm5 (sat*) */ + { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} }, /* CC Fa2,Rb,Rc */ + { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC Fa2,Rb,imm6 */ + { SHORT_A1, 1, { Ra, Rb, Rc } }, /* Ra,Rb,Rc for MAC where a=1 */ + { SHORT_A1, 3, { Ra, Rb, IMM6 } }, /* Ra,Rb,imm6 for MAC where a=1 */ + { SHORT_AA, 0, { Aa, Rb, Rc } }, /* Aa,Rb,Rc */ + { SHORT_AA, 2, { Aa, Rb, IMM6 } }, /* Aa,Rb,imm6 */ + { SHORT_RA, 0, { Ra, Ab, Rc } }, /* Ra,Ab,Rc */ + { SHORT_RA, 2, { Ra, Ab, IMM5 } }, /* Ra,Ab,imm5 */ + { SHORT_MODINC, 1, { Rb, IMM5 } }, /* Rb,imm5 (modinc) */ + { SHORT_MODDEC, 3, { Rb, IMM5 } }, /* Rb,imm5 (moddec) */ + { SHORT_C1, 2, { Ra, Cb, Fake } }, /* Ra,Cb (mvfsys) */ + { SHORT_C2, 2, { Ca, Rb, Fake } }, /* Ca,Rb (mvtsys) */ + { SHORT_UF, 0, { Fa, Fb } }, /* Fa,Fb (notfg) */ + { SHORT_NONE, 0, { 0 } }, /* no operands (nop, reit) */ + { LONG, 2, { Ra, Rb, IMM32 } }, /* Ra,Rb,imm32 */ + { LONG_U, 2, { IMM32 } }, /* imm32 */ + { LONG_AF, 2, { Fa, Rb, IMM32 } }, /* Fa,Rb,imm32 */ + { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC Fa2,Rb,imm32 */ + { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } }, /* Ra,@(Rb,imm32) */ + { LONG_2, 2, { Ra, IMM32 } }, /* Ra,imm32 */ + { LONG_2b, 3, { Ra, IMM32 } }, /* Ra,imm32 */ + { LONG_D, 2, { IMM6, IMM32 } }, /* imm6,imm32 */ + { 0, 0, { 0 } }, +}; + +const char *d30v_ecc_names[] = +{ + "al", + "tx", + "fx", + "xt", + "xf", + "tt", + "tf", + "res" +}; + +const char *d30v_cc_names[] = +{ + "eq", + "ne", + "gt", + "ge", + "lt", + "le", + "ps", + "ng", + NULL +}; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index c5ba659c1f..67aa6f9509 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -28,9 +28,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* start-sanitize-d10v */ #define ARCH_d10v /* end-sanitize-d10v */ -/* start-sanitize-v850 */ -#define ARCH_v850 -/* end-sanitize-v850 */ +/* start-sanitize-d30v */ +#define ARCH_d30v +/* end-sanitize-d30v */ #define ARCH_h8300 #define ARCH_h8500 #define ARCH_hppa @@ -39,12 +39,19 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_m68k #define ARCH_m88k #define ARCH_mips -#define ARCH_mn10x00 +#define ARCH_mn10200 +#define ARCH_mn10300 #define ARCH_ns32k #define ARCH_powerpc #define ARCH_rs6000 #define ARCH_sh #define ARCH_sparc +/* start-sanitize-tic80 */ +#define ARCH_tic80 +/* end-sanitize-tic80 */ +/* start-sanitize-v850 */ +#define ARCH_v850 +/* end-sanitize-v850 */ #define ARCH_w65 #define ARCH_z8k #endif @@ -96,6 +103,13 @@ disassembler (abfd) break; #endif /* end-sanitize-d10v */ +/* start-sanitize-d30v */ +#ifdef ARCH_d30v + case bfd_arch_d30v: + disassemble = print_insn_d30v; + break; +#endif +/* end-sanitize-d30v */ #ifdef ARCH_h8300 case bfd_arch_h8300: if (bfd_get_mach(abfd) == bfd_mach_h8300h) @@ -149,9 +163,14 @@ disassembler (abfd) disassemble = print_insn_little_mips; break; #endif -#ifdef ARCH_mn10x00 - case bfd_arch_mn10x00: - disassemble = print_insn_mn10x00; +#ifdef ARCH_mn10200 + case bfd_arch_mn10200: + disassemble = print_insn_mn10200; + break; +#endif +#ifdef ARCH_mn10300 + case bfd_arch_mn10300: + disassemble = print_insn_mn10300; break; #endif #ifdef ARCH_powerpc @@ -180,6 +199,13 @@ disassembler (abfd) disassemble = print_insn_sparc; break; #endif +/* start-sanitize-tic80 */ +#ifdef ARCH_tic80 + case bfd_arch_tic80: + disassemble = print_insn_tic80; + break; +#endif +/* end-sanitize-tic80 */ /* start-sanitize-v850 */ #ifdef ARCH_v850 case bfd_arch_v850: -- 2.34.1