From f4950f76fa56bd60314f05620c39fb31e96bb088 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 3 Jan 2020 10:12:49 +0100 Subject: [PATCH] Arm64: correct 64-bit element fmmla encoding There's just one bit of difference to the 32-bit element form, as per the documentation. --- gas/ChangeLog | 5 ++ gas/testsuite/gas/aarch64/f64mm.d | 4 +- gas/testsuite/gas/aarch64/sve-movprfx-mm.d | 2 +- opcodes/ChangeLog | 6 ++ opcodes/aarch64-dis-2.c | 90 +++++++++++----------- opcodes/aarch64-tbl.h | 2 +- 6 files changed, 60 insertions(+), 49 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 86134cb5b6..933c17e603 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2020-01-03 Jan Beulich + + * testsuite/gas/aarch64/f64mm.d, + testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations. + 2020-01-02 Sergey Belyashov * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add diff --git a/gas/testsuite/gas/aarch64/f64mm.d b/gas/testsuite/gas/aarch64/f64mm.d index a09179a93b..b2aa86132a 100644 --- a/gas/testsuite/gas/aarch64/f64mm.d +++ b/gas/testsuite/gas/aarch64/f64mm.d @@ -6,8 +6,8 @@ Disassembly of section \.text: 0+ <\.text>: - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d - *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\] *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\] *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\] diff --git a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d index 88415ef098..f2b480dfe4 100644 --- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d +++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d @@ -21,4 +21,4 @@ Disassembly of section \.text: *[0-9a-f]+: 0420bc11 movprfx z17, z0 *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s *[0-9a-f]+: 0420bc11 movprfx z17, z0 - *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d + *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e3be019ec9..bf031a76d8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2020-01-03 Jan Beulich + + * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit + FMMLA encoding. + * opcodes/aarch64-dis-2.c: Re-generate. + 2020-01-02 Sergey Belyashov * z80-dis.c: Add support for eZ80 and Z80 instructions. diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 3de1dc3dca..950a5f2e99 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -8839,9 +8839,9 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -8855,69 +8855,58 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x11001x00001xxxx111xxxxxxxxxxxxx - stnt1b. */ - return 1933; + x11001x00100xxxx111xxxxxxxxxxxxx + st1b. */ + return 1872; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x11001x01001xxxx111xxxxxxxxxxxxx - stnt1h. */ - return 1937; + x11001x01100xxxx111xxxxxxxxxxxxx + st1h. */ + return 1893; } } } else { - if (((word >> 23) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x11001x00100xxxx111xxxxxxxxxxxxx - st1b. */ - return 1872; + x11001x00001xxxx111xxxxxxxxxxxxx + stnt1b. */ + return 1933; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x11001x00101xxxx111xxxxxxxxxxxxx - st3b. */ - return 1917; + x11001x01001xxxx111xxxxxxxxxxxxx + stnt1h. */ + return 1937; } } else { - if (((word >> 31) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - 011001x0110xxxxx111xxxxxxxxxxxxx - fmmla. */ - return 2398; + x11001x00101xxxx111xxxxxxxxxxxxx + st3b. */ + return 1917; } else { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x01100xxxx111xxxxxxxxxxxxx - st1h. */ - return 1893; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 111001x01101xxxx111xxxxxxxxxxxxx - st3h. */ - return 1921; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x11001x01101xxxx111xxxxxxxxxxxxx + st3h. */ + return 1921; } } } @@ -9780,21 +9769,32 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 31) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x11001x01110xxxx111xxxxxxxxxxxxx - st1h. */ - return 1895; + 011001x0111xxxxx111xxxxxxxxxxxxx + fmmla. */ + return 2398; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x11001x01111xxxx111xxxxxxxxxxxxx - st4h. */ - return 1929; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x01110xxxx111xxxxxxxxxxxxx + st1h. */ + return 1895; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 111001x01111xxxx111xxxxxxxxxxxxx + st4h. */ + return 1929; + } } } } diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 6a8f794909..8a74777eed 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5073,7 +5073,7 @@ struct aarch64_opcode aarch64_opcode_table[] = INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), - F64MATMUL_SVE_INSNC ("fmmla", 0x64c0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), + F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), -- 2.34.1