From 0f3f71676a8971e0376d7d99b383660f06ff4d95 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Wed, 24 Jul 2019 16:52:23 +0300 Subject: [PATCH] [ARC] Update disassembler opcode selection New instruction are added, and some of them are overlapping. Update disassembler to correctly recognize them. Introduce nps400 option. opcodes/ xxxx-xx-xx Claudiu Zissulescu * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, and MPY class instructions. (parse_option): Add nps400 option. (print_arc_disassembler_options): Add nps400 info. gas/ xxxx-xx-xx Claudiu Zissulescu * testsuite/gas/arc/nps400-6.d: Update test. --- gas/ChangeLog | 4 ++++ gas/testsuite/gas/arc/nps400-6.d | 2 +- opcodes/ChangeLog | 7 +++++++ opcodes/arc-dis.c | 24 +++++++++++++++++++++++- 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index c08ccbc9b6..ab519fa403 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2019-07-24 Claudiu Zissulescu + + * testsuite/gas/arc/nps400-6.d: Update test. + 2019-07-24 Alan Modra * config/obj-elf.c (obj_elf_section, obj_elf_type): Set has_gnu_osabi. diff --git a/gas/testsuite/gas/arc/nps400-6.d b/gas/testsuite/gas/arc/nps400-6.d index 3adf756130..95344082bf 100644 --- a/gas/testsuite/gas/arc/nps400-6.d +++ b/gas/testsuite/gas/arc/nps400-6.d @@ -1,5 +1,5 @@ #as: -mcpu=arc700 -mnps400 -#objdump: -dr +#objdump: -dr -Mnps400 .*: +file format .*arc.* diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e0e6bdb4d9..ba0be86704 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2019-07-24 Claudiu Zissulescu + + * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, + and MPY class instructions. + (parse_option): Add nps400 option. + (print_arc_disassembler_options): Add nps400 info. + 2019-07-24 Claudiu Zissulescu * arc-ext-tbl.h (bspeek): Remove it, added to main table. diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index ee598918c5..8207c05519 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -181,7 +181,9 @@ skip_this_opcode (const struct arc_opcode *opcode) /* Check opcode for major 0x06, return if it is not in. */ if (arc_opcode_len (opcode) == 4 - && OPCODE_32BIT_INSN (opcode->opcode) != 0x06) + && (OPCODE_32BIT_INSN (opcode->opcode) != 0x06 + /* Can be an APEX extensions. */ + && OPCODE_32BIT_INSN (opcode->opcode) != 0x07)) return FALSE; /* or not a known truble class. */ @@ -190,6 +192,7 @@ skip_this_opcode (const struct arc_opcode *opcode) case FLOAT: case DSP: case ARITH: + case MPY: break; default: return FALSE; @@ -764,6 +767,23 @@ parse_option (const char *option) else if (disassembler_options_cmp (option, "fpuda") == 0) add_to_decodelist (FLOAT, DPA); + else if (disassembler_options_cmp (option, "nps400") == 0) + { + add_to_decodelist (ACL, NPS400); + add_to_decodelist (ARITH, NPS400); + add_to_decodelist (BITOP, NPS400); + add_to_decodelist (BMU, NPS400); + add_to_decodelist (CONTROL, NPS400); + add_to_decodelist (DMA, NPS400); + add_to_decodelist (DPI, NPS400); + add_to_decodelist (MEMORY, NPS400); + add_to_decodelist (MISC, NPS400); + add_to_decodelist (NET, NPS400); + add_to_decodelist (PMU, NPS400); + add_to_decodelist (PROTOCOL_DECODE, NPS400); + add_to_decodelist (ULTRAIP, NPS400); + } + else if (disassembler_options_cmp (option, "fpus") == 0) { add_to_decodelist (FLOAT, SP); @@ -1411,6 +1431,8 @@ with -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\ fpud Recognize double precision FPU instructions.\n")); fprintf (stream, _("\ + nps400 Recognize NPS400 instructions.\n")); + fprintf (stream, _("\ hex Use only hexadecimal number to print immediates.\n")); } -- 2.34.1