From 3cc17af5890d5877b8ac53eb5cd9a2adf82467e6 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Wed, 30 Oct 2019 09:07:40 +0100 Subject: [PATCH] x86: re-do "shorthand" handling Now that the opcode table gets preprocessed, undo parts of commit dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the preprocessor handle the expansion there, while making the expansions explicit in i386-gen and the register table. --- opcodes/ChangeLog | 12 ++ opcodes/i386-gen.c | 55 ++----- opcodes/i386-opc.tbl | 12 ++ opcodes/i386-reg.tbl | 354 +++++++++++++++++++++---------------------- 4 files changed, 214 insertions(+), 219 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 41cb087a35..dc22f41115 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2019-10-30 Jan Beulich + + * i386-gen.c (operand_type_shorthands): Delete. + (operand_type_init): Expand previous shorthands. + (set_bitfield_from_shorthand): Rename back to ... + (set_bitfield_from_cpu_flag_init): ... this. Drop processing + of operand_type_init[]. + (set_bitfield): Adjust call to the above function. + * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg, + RegXMM, RegYMM, RegZMM): Define. + * i386-reg.tbl: Expand prior shorthands. + 2019-10-30 Jan Beulich * i386-gen.c (output_i386_opcode): Change order of fields diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index c48c67591a..a3160f2c3d 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -379,31 +379,18 @@ static initializer cpu_flag_init[] = "CpuAVX512_VP2INTERSECT" }, }; -static const initializer operand_type_shorthands[] = -{ - { "Reg8", "Reg|Byte" }, - { "Reg16", "Reg|Word" }, - { "Reg32", "Reg|Dword" }, - { "Reg64", "Reg|Qword" }, - { "FloatAcc", "Acc|Tbyte" }, - { "FloatReg", "Reg|Tbyte" }, - { "RegXMM", "RegSIMD|Xmmword" }, - { "RegYMM", "RegSIMD|Ymmword" }, - { "RegZMM", "RegSIMD|Zmmword" }, -}; - static initializer operand_type_init[] = { { "OPERAND_TYPE_NONE", "0" }, { "OPERAND_TYPE_REG8", - "Reg8" }, + "Reg|Byte" }, { "OPERAND_TYPE_REG16", - "Reg16" }, + "Reg|Word" }, { "OPERAND_TYPE_REG32", - "Reg32" }, + "Reg|Dword" }, { "OPERAND_TYPE_REG64", - "Reg64" }, + "Reg|Qword" }, { "OPERAND_TYPE_IMM1", "Imm1" }, { "OPERAND_TYPE_IMM8", @@ -441,9 +428,9 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_DEBUG", "Debug" }, { "OPERAND_TYPE_FLOATREG", - "FloatReg" }, + "Reg|Tbyte" }, { "OPERAND_TYPE_FLOATACC", - "FloatAcc" }, + "Acc|Tbyte" }, { "OPERAND_TYPE_SREG", "SReg" }, { "OPERAND_TYPE_JUMPABSOLUTE", @@ -451,11 +438,11 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_REGMMX", "RegMMX" }, { "OPERAND_TYPE_REGXMM", - "RegXMM" }, + "RegSIMD|Xmmword" }, { "OPERAND_TYPE_REGYMM", - "RegYMM" }, + "RegSIMD|Ymmword" }, { "OPERAND_TYPE_REGZMM", - "RegZMM" }, + "RegSIMD|Zmmword" }, { "OPERAND_TYPE_REGMASK", "RegMask" }, { "OPERAND_TYPE_ESSEG", @@ -830,8 +817,8 @@ next_field (char *str, char sep, char **next, char *last) static void set_bitfield (char *, bitfield *, int, unsigned int, int); static int -set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size, - int lineno) +set_bitfield_from_cpu_flag_init (char *f, bitfield *array, unsigned int size, + int lineno) { char *str, *next, *last; unsigned int i; @@ -852,22 +839,6 @@ set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size, return 0; } - for (i = 0; i < ARRAY_SIZE (operand_type_shorthands); i++) - if (strcmp (operand_type_shorthands[i].name, f) == 0) - { - /* Turn on selective bits. */ - char *init = xstrdup (operand_type_shorthands[i].init); - last = init + strlen (init); - for (next = init; next && next < last; ) - { - str = next_field (next, '|', &next, last); - if (str) - set_bitfield (str, array, 1, size, lineno); - } - free (init); - return 0; - } - return -1; } @@ -918,8 +889,8 @@ set_bitfield (char *f, bitfield *array, int value, } } - /* Handle shorthands. */ - if (value == 1 && !set_bitfield_from_shorthand (f, array, size, lineno)) + /* Handle CPU_XXX_FLAGS. */ + if (value == 1 && !set_bitfield_from_cpu_flag_init (f, array, size, lineno)) return; if (lineno != -1) diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index cf366b0ea1..02c83a30f8 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -22,6 +22,18 @@ #include "i386-opc.h" #undef None +#define Reg8 Reg|Byte +#define Reg16 Reg|Word +#define Reg32 Reg|Dword +#define Reg64 Reg|Qword + +#define FloatAcc Acc|Tbyte +#define FloatReg Reg|Tbyte + +#define RegXMM RegSIMD|Xmmword +#define RegYMM RegSIMD|Ymmword +#define RegZMM RegSIMD|Zmmword + #define Size16 Size=SIZE16 #define Size32 Size=SIZE32 #define Size64 Size=SIZE64 diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index ba4c51c046..61e9fe07c2 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -19,82 +19,82 @@ // 02110-1301, USA. // Make %st first as we test for it. -st, FloatReg|Acc, 0, 0, 11, 33 +st, Reg|Acc|Tbyte, 0, 0, 11, 33 // 8 bit regs -al, Reg8|Acc, 0, 0, Dw2Inval, Dw2Inval -cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval -dl, Reg8, 0, 2, Dw2Inval, Dw2Inval -bl, Reg8, 0, 3, Dw2Inval, Dw2Inval -ah, Reg8, 0, 4, Dw2Inval, Dw2Inval -ch, Reg8, 0, 5, Dw2Inval, Dw2Inval -dh, Reg8, 0, 6, Dw2Inval, Dw2Inval -bh, Reg8, 0, 7, Dw2Inval, Dw2Inval -axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval -cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval -dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval -bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval -spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval -bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval -sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval -dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval -r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval -r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval -r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval -r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval -r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval -r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval -r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval -r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval +al, Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval +cl, Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval +dl, Reg|Byte, 0, 2, Dw2Inval, Dw2Inval +bl, Reg|Byte, 0, 3, Dw2Inval, Dw2Inval +ah, Reg|Byte, 0, 4, Dw2Inval, Dw2Inval +ch, Reg|Byte, 0, 5, Dw2Inval, Dw2Inval +dh, Reg|Byte, 0, 6, Dw2Inval, Dw2Inval +bh, Reg|Byte, 0, 7, Dw2Inval, Dw2Inval +axl, Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval +cxl, Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval +dxl, Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval +bxl, Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval +spl, Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval +bpl, Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval +sil, Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval +dil, Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval +r8b, Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval +r9b, Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval +r10b, Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval +r11b, Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval +r12b, Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval +r13b, Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval +r14b, Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval +r15b, Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval // 16 bit regs -ax, Reg16|Acc, 0, 0, Dw2Inval, Dw2Inval -cx, Reg16, 0, 1, Dw2Inval, Dw2Inval -dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval -bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval -sp, Reg16, 0, 4, Dw2Inval, Dw2Inval -bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval -si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval -di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval -r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval -r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval -r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval -r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval -r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval -r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval -r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval -r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval +ax, Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval +cx, Reg|Word, 0, 1, Dw2Inval, Dw2Inval +dx, Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval +bx, Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval +sp, Reg|Word, 0, 4, Dw2Inval, Dw2Inval +bp, Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval +si, Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval +di, Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval +r8w, Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval +r9w, Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval +r10w, Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval +r11w, Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval +r12w, Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval +r13w, Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval +r14w, Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval +r15w, Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval // 32 bit regs -eax, Reg32|BaseIndex|Acc, 0, 0, 0, Dw2Inval -ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval -edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval -ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval -esp, Reg32, 0, 4, 4, Dw2Inval -ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval -esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval -edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval -r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval -r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval -r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval -r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval -r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval -r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval -r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval -r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval -rax, Reg64|BaseIndex|Acc, 0, 0, Dw2Inval, 0 -rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2 -rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1 -rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3 -rsp, Reg64, 0, 4, Dw2Inval, 7 -rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6 -rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4 -rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5 -r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8 -r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9 -r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10 -r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11 -r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12 -r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13 -r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14 -r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15 +eax, Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval +ecx, Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval +edx, Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval +ebx, Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval +esp, Reg|Dword, 0, 4, 4, Dw2Inval +ebp, Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval +esi, Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval +edi, Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval +r8d, Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval +r9d, Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval +r10d, Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval +r11d, Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval +r12d, Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval +r13d, Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval +r14d, Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval +r15d, Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval +rax, Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0 +rcx, Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2 +rdx, Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1 +rbx, Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3 +rsp, Reg|Qword, 0, 4, Dw2Inval, 7 +rbp, Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6 +rsi, Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4 +rdi, Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5 +r8, Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8 +r9, Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9 +r10, Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10 +r11, Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11 +r12, Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12 +r13, Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13 +r14, Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14 +r15, Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15 // Vector mask registers. k0, RegMask, 0, 0, 93, 118 k1, RegMask, 0, 1, 94, 119 @@ -180,104 +180,104 @@ mm4, RegMMX, 0, 4, 33, 45 mm5, RegMMX, 0, 5, 34, 46 mm6, RegMMX, 0, 6, 35, 47 mm7, RegMMX, 0, 7, 36, 48 -xmm0, RegXMM|Acc, 0, 0, 21, 17 -xmm1, RegXMM, 0, 1, 22, 18 -xmm2, RegXMM, 0, 2, 23, 19 -xmm3, RegXMM, 0, 3, 24, 20 -xmm4, RegXMM, 0, 4, 25, 21 -xmm5, RegXMM, 0, 5, 26, 22 -xmm6, RegXMM, 0, 6, 27, 23 -xmm7, RegXMM, 0, 7, 28, 24 -xmm8, RegXMM, RegRex, 0, Dw2Inval, 25 -xmm9, RegXMM, RegRex, 1, Dw2Inval, 26 -xmm10, RegXMM, RegRex, 2, Dw2Inval, 27 -xmm11, RegXMM, RegRex, 3, Dw2Inval, 28 -xmm12, RegXMM, RegRex, 4, Dw2Inval, 29 -xmm13, RegXMM, RegRex, 5, Dw2Inval, 30 -xmm14, RegXMM, RegRex, 6, Dw2Inval, 31 -xmm15, RegXMM, RegRex, 7, Dw2Inval, 32 -xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67 -xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68 -xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69 -xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70 -xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71 -xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72 -xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73 -xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74 -xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75 -xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76 -xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77 -xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78 -xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79 -xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80 -xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81 -xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82 +xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17 +xmm1, RegSIMD|Xmmword, 0, 1, 22, 18 +xmm2, RegSIMD|Xmmword, 0, 2, 23, 19 +xmm3, RegSIMD|Xmmword, 0, 3, 24, 20 +xmm4, RegSIMD|Xmmword, 0, 4, 25, 21 +xmm5, RegSIMD|Xmmword, 0, 5, 26, 22 +xmm6, RegSIMD|Xmmword, 0, 6, 27, 23 +xmm7, RegSIMD|Xmmword, 0, 7, 28, 24 +xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25 +xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26 +xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27 +xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28 +xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29 +xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30 +xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31 +xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32 +xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67 +xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68 +xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69 +xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70 +xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71 +xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72 +xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73 +xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74 +xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75 +xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76 +xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77 +xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78 +xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79 +xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 +xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 +xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 // AVX registers. -ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval -ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval -ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval -ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval -ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval -ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval -ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval -ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval -ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval -ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval -ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval -ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval -ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval -ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval -ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval -ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval -ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval -ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval -ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval -ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval -ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval -ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval -ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval -ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval -ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval +ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval +ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval +ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval +ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval +ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval +ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval +ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval +ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval +ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval +ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval +ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval +ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval +ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval +ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval +ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval +ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval +ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval +ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval +ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval +ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval +ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval +ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval +ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval +ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval +ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval +ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval +ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval +ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval +ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval +ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval +ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval // AVX512 registers. -zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval -zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval -zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval -zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval -zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval -zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval -zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval -zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval -zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval -zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval -zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval -zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval -zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval -zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval -zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval -zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval -zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval -zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval -zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval -zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval -zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval -zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval -zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval -zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval -zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval +zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval +zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval +zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval +zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval +zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval +zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval +zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval +zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval +zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval +zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval +zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval +zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval +zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval +zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval +zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval +zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval +zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval +zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval +zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval +zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval +zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval +zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval +zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval +zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval +zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval +zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval +zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval +zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval +zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval +zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval +zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval // Bound registers for MPX bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval @@ -292,14 +292,14 @@ eip, Dword, RegRex64, RegIP, 8, Dw2Inval riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval // fp regs. -st(0), FloatReg|Acc, 0, 0, 11, 33 -st(1), FloatReg, 0, 1, 12, 34 -st(2), FloatReg, 0, 2, 13, 35 -st(3), FloatReg, 0, 3, 14, 36 -st(4), FloatReg, 0, 4, 15, 37 -st(5), FloatReg, 0, 5, 16, 38 -st(6), FloatReg, 0, 6, 17, 39 -st(7), FloatReg, 0, 7, 18, 40 +st(0), Reg|Acc|Tbyte, 0, 0, 11, 33 +st(1), Reg|Tbyte, 0, 1, 12, 34 +st(2), Reg|Tbyte, 0, 2, 13, 35 +st(3), Reg|Tbyte, 0, 3, 14, 36 +st(4), Reg|Tbyte, 0, 4, 15, 37 +st(5), Reg|Tbyte, 0, 5, 16, 38 +st(6), Reg|Tbyte, 0, 6, 17, 39 +st(7), Reg|Tbyte, 0, 7, 18, 40 // Pseudo-register names only used in .cfi_* directives eflags, 0, 0, 0, 9, 49 rflags, 0, 0, 0, Dw2Inval, 49 -- 2.34.1