From 47b1a55a55bf15212bd64e27b10023d10499d9e3 Mon Sep 17 00:00:00 2001 From: Stan Cox Date: Fri, 3 Jan 2003 19:52:23 +0000 Subject: [PATCH] * iq2000-asm.c: New file. * iq2000-desc.c: Likewise. * iq2000-desc.h: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * iq2000-opc.c: Likewise. * iq2000-opc.h: Likewise. * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, iq2000-ibld.c, iq2000-opc.c. (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, iq2000-ibld.lo, iq2000-opc.lo. (CLEANFILES): Add stamp-iq2000. (IQ2000_DEPS): New macro. (stamp-iq2000): New target. * Makefile.in: Regenerate. * configure.in: Handle bfd_iq2000_arch. * configure: Regenerate. --- opcodes/ChangeLog | 22 + opcodes/Makefile.am | 21 +- opcodes/Makefile.in | 38 +- opcodes/configure | 1 + opcodes/configure.in | 1 + opcodes/disassemble.c | 6 + opcodes/iq2000-asm.c | 891 +++++++++++ opcodes/iq2000-desc.c | 2222 ++++++++++++++++++++++++++ opcodes/iq2000-desc.h | 302 ++++ opcodes/iq2000-dis.c | 619 ++++++++ opcodes/iq2000-ibld.c | 1394 +++++++++++++++++ opcodes/iq2000-opc.c | 3482 +++++++++++++++++++++++++++++++++++++++++ opcodes/iq2000-opc.h | 181 +++ 13 files changed, 9178 insertions(+), 2 deletions(-) create mode 100644 opcodes/iq2000-asm.c create mode 100644 opcodes/iq2000-desc.c create mode 100644 opcodes/iq2000-desc.h create mode 100644 opcodes/iq2000-dis.c create mode 100644 opcodes/iq2000-ibld.c create mode 100644 opcodes/iq2000-opc.c create mode 100644 opcodes/iq2000-opc.h diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 18a16d36fc..277904b477 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,25 @@ +2002-01-02 Ben Elliston + Jeff Johnston + + * iq2000-asm.c: New file. + * iq2000-desc.c: Likewise. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * iq2000-opc.c: Likewise. + * iq2000-opc.h: Likewise. + * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. + (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c. + (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, + iq2000-ibld.lo, iq2000-opc.lo. + (CLEANFILES): Add stamp-iq2000. + (IQ2000_DEPS): New macro. + (stamp-iq2000): New target. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_iq2000_arch. + * configure: Regenerate. + 2003-01-02 Chris Demetriou * mips-dis.c (print_insn_args): Use position extracted by "+A" diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index ba0072681c..fe6f9b7496 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -31,6 +31,7 @@ HFILES = \ ia64-asmtab.h \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -96,6 +97,11 @@ CFILES = \ ip2k-dis.c \ ip2k-ibld.c \ ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -201,6 +207,11 @@ ALL_MACHINES = \ ip2k-dis.lo \ ip2k-ibld.lo \ ip2k-opc.lo \ + iq2000-asm.lo \ + iq2000-desc.lo \ + iq2000-dis.lo \ + iq2000-ibld.lo \ + iq2000-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -326,7 +337,7 @@ uninstall_libopcodes: CLEANFILES = \ stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-xstormy16 \ + stamp-iq2000 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -350,6 +361,7 @@ M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv OPENRISC_DEPS = stamp-openrisc +IQ2000_DEPS = stamp-iq2000 XSTORMY16_DEPS = stamp-xstormy16 else IP2K_DEPS = @@ -357,6 +369,7 @@ M32R_DEPS = FR30_DEPS = FRV_DEPS = OPENRISC_DEPS = +IQ2000_DEPS = XSTORMY16_DEPS = endif @@ -401,6 +414,12 @@ $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(s stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= +$(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) + @true +stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ + $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= extrafiles= + $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 08ea4b222d..7ffd66ca37 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -141,6 +141,7 @@ HFILES = \ ia64-asmtab.h \ ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -207,6 +208,11 @@ CFILES = \ ip2k-dis.c \ ip2k-ibld.c \ ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -313,6 +319,11 @@ ALL_MACHINES = \ ip2k-dis.lo \ ip2k-ibld.lo \ ip2k-opc.lo \ + iq2000-asm.lo \ + iq2000-desc.lo \ + iq2000-dis.lo \ + iq2000-ibld.lo \ + iq2000-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -392,7 +403,7 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ + stamp-ip2k stamp-iq2000 stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -413,6 +424,8 @@ CGENDEPS = \ CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 @CGEN_MAINT_TRUE@IP2K_DEPS = @CGEN_MAINT_TRUE@stamp-ip2k @CGEN_MAINT_FALSE@IP2K_DEPS = +@CGEN_MAINT_TRUE@IQ2000_DEPS = @CGEN_MAINT_TRUE@stamp-ip2000 +@CGEN_MAINT_FALSE@IQ2000_DEPS = @CGEN_MAINT_TRUE@M32R_DEPS = @CGEN_MAINT_TRUE@stamp-m32r @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @@ -877,6 +890,12 @@ $(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k- stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc $(MAKE) run-cgen arch=ip2k prefix=ip2k options= extrafiles= +$(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) + @true +stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ + $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= extrafiles= + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc @@ -1114,6 +1133,23 @@ ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ ip2k-opc.h $(INCDIR)/libiberty.h +iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h iq2000-desc.h \ + $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h +iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h iq2000-desc.h \ + $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h +iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h +iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h +iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(BFD_H) \ + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h iq2000-desc.h \ + $(INCDIR)/opcode/cgen.h iq2000-opc.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ diff --git a/opcodes/configure b/opcodes/configure index 8eed735ed5..171fadde4a 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -4615,6 +4615,7 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index bc8d6f8e94..6e74b15cc3 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -190,6 +190,7 @@ if test x${all_targets} = xfalse ; then bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 1c2c21c178..7e6ba0b807 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -70,6 +70,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_xstormy16 #define ARCH_z8k #define ARCH_frv +#define ARCH_iq2000 #define INCLUDE_SHMEDIA #endif @@ -359,6 +360,11 @@ disassembler (abfd) case bfd_arch_frv: disassemble = print_insn_frv; break; +#endif +#ifdef ARCH_iq2000 + case bfd_arch_iq2000: + disassemble = print_insn_iq2000; + break; #endif default: return 0; diff --git a/opcodes/iq2000-asm.c b/opcodes/iq2000-asm.c new file mode 100644 index 0000000000..17b93eb2f4 --- /dev/null +++ b/opcodes/iq2000-asm.c @@ -0,0 +1,891 @@ +/* Assembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-asm.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +static const char * parse_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + +/* -- assembler routines inserted here. */ + +/* -- asm.c */ +static const char * parse_mimm PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_imm PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_hi16 PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +static const char * parse_lo16 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); + +/* Special check to ensure that instruction exists for given machine */ +int +iq2000_cgen_insn_supported (cd, insn) + CGEN_CPU_DESC cd; + CGEN_INSN *insn; +{ + int machs = cd->machs; + + return ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0); +} + +static int iq2000_cgen_isa_register (strp) + const char **strp; +{ + int len; + int ch1, ch2; + if (**strp == 'r' || **strp == 'R') + { + len = strlen (*strp); + if (len == 2) + { + ch1 = (*strp)[1]; + if ('0' <= ch1 && ch1 <= '9') + return 1; + } + else if (len == 3) + { + ch1 = (*strp)[1]; + ch2 = (*strp)[2]; + if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) + return 1; + if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) + return 1; + } + } + if (**strp == '%' && tolower((*strp)[1]) != 'l' && tolower((*strp)[1]) != 'h') + return 1; + return 0; +} + +/* Handle negated literal. */ + +static const char * +parse_mimm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + const char *errmsg; + long value; + + /* Verify this isn't a register */ + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = (-value) & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (-value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle signed/unsigned literal. */ + +static const char * +parse_imm (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + const char *errmsg; + long value; + + if (iq2000_cgen_isa_register (strp)) + errmsg = _("immediate value cannot be register"); + else + { + long value; + + errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); + if (errmsg == NULL) + { + long x = value & 0xFFFF0000; + if (x != 0 && x != 0xFFFF0000) + errmsg = _("immediate value out of range"); + else + *valuep = (value & 0xFFFF); + } + } + return errmsg; +} + +/* Handle iq10 21-bit jmp offset. */ + +static const char * +parse_jtargq10 (cd, strp, opindex, reloc, type_addr, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + int reloc; + enum cgen_parse_operand_result *type_addr; + unsigned long *valuep; +{ + const char *errmsg; + bfd_vma value; + enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; + + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, + &result_type, &value); + if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* check value is within 23-bits (remembering that 2-bit shift right will occur) */ + if (value > 0x7fffff) + return _("21-bit offset out of range"); + } + *valuep = (value & 0x7FFFFF); + return errmsg; +} + +/* Handle high(). */ + +static const char * +parse_hi16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + unsigned long *valuep; +{ + if (strncasecmp (*strp, "%hi(", 4) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + /* if value has top-bit of %lo on, then it will + sign-propagate and so we compensate by adding + 1 to the resultant %hi value */ + if (value & 0x8000) + value += 0x10000; + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + /* we add %uhi in case a user just wants the high 16-bits or is using + an insn like ori for %lo which does not sign-propagate */ + if (strncasecmp (*strp, "%uhi(", 5) == 0) + { + enum cgen_parse_operand_result result_type; + bfd_vma value; + const char *errmsg; + + *strp += 5; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + { + value >>= 16; + } + *valuep = value; + + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_lo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value &= 0xffff; + *valuep = value; + return errmsg; + } + + return parse_imm (cd, strp, opindex, valuep); +} + +/* Handle %lo in a negated signed context. + The signedness of the value doesn't matter to %lo(), but this also + handles the case where %lo() isn't present. */ + +static const char * +parse_mlo16 (cd, strp, opindex, valuep) + CGEN_CPU_DESC cd; + const char **strp; + int opindex; + long *valuep; +{ + if (strncasecmp (*strp, "%lo(", 4) == 0) + { + const char *errmsg; + enum cgen_parse_operand_result result_type; + bfd_vma value; + + *strp += 4; + errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, + &result_type, &value); + if (**strp != ')') + return _("missing `)'"); + ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + value = (-value) & 0xffff; + *valuep = value; + return errmsg; + } + + return parse_mimm (cd, strp, opindex, valuep); +} + +/* -- */ + +const char * iq2000_cgen_parse_operand + PARAMS ((CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *)); + +/* Main entry point for operand parsing. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. */ + +const char * +iq2000_cgen_parse_operand (cd, opindex, strp, fields) + CGEN_CPU_DESC cd; + int opindex; + const char ** strp; + CGEN_FIELDS * fields; +{ + const char * errmsg = NULL; + /* Used by scalar operands that still need to be parsed. */ + long junk ATTRIBUTE_UNUSED; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value); + fields->f_imm = value; + } + break; + case IQ2000_OPERAND_BITNUM : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BITNUM, &fields->f_rt); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_BYTECOUNT, &fields->f_bytecount); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Y, &fields->f_cam_y); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CAM_Z, &fields->f_cam_z); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3FUNC, &fields->f_cm_3func); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_3Z, &fields->f_cm_3z); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4FUNC, &fields->f_cm_4func); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_CM_4Z, &fields->f_cm_4z); + break; + case IQ2000_OPERAND_COUNT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_COUNT, &fields->f_count); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_EXECODE, &fields->f_excode); + break; + case IQ2000_OPERAND_HI16 : + errmsg = parse_hi16 (cd, strp, IQ2000_OPERAND_HI16, &fields->f_imm); + break; + case IQ2000_OPERAND_IMM : + errmsg = parse_imm (cd, strp, IQ2000_OPERAND_IMM, &fields->f_imm); + break; + case IQ2000_OPERAND_INDEX : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_INDEX, &fields->f_index); + break; + case IQ2000_OPERAND_JMPTARG : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value); + fields->f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + bfd_vma value; + errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value); + fields->f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + errmsg = parse_lo16 (cd, strp, IQ2000_OPERAND_LO16, &fields->f_imm); + break; + case IQ2000_OPERAND_MASK : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASK, &fields->f_mask); + break; + case IQ2000_OPERAND_MASKL : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKL, &fields->f_maskl); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKQ10, &fields->f_maskq10); + break; + case IQ2000_OPERAND_MASKR : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_MASKR, &fields->f_rs); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = parse_mlo16 (cd, strp, IQ2000_OPERAND_MLO16, &fields->f_imm); + break; + case IQ2000_OPERAND_OFFSET : + { + bfd_vma value; + errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value); + fields->f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rs); + break; + case IQ2000_OPERAND_RD_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rd_rt); + break; + case IQ2000_OPERAND_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + errmsg = cgen_parse_keyword (cd, strp, & iq2000_cgen_opval_gr_names, & fields->f_rt_rs); + break; + case IQ2000_OPERAND_SHAMT : + errmsg = cgen_parse_unsigned_integer (cd, strp, IQ2000_OPERAND_SHAMT, &fields->f_shamt); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex); + abort (); + } + + return errmsg; +} + +cgen_parse_fn * const iq2000_cgen_parse_handlers[] = +{ + parse_insn_normal, +}; + +void +iq2000_cgen_init_asm (cd) + CGEN_CPU_DESC cd; +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->parse_handlers = & iq2000_cgen_parse_handlers[0]; + cd->parse_operand = iq2000_cgen_parse_operand; +#ifdef CGEN_ASM_INIT_HOOK +CGEN_ASM_INIT_HOOK +#endif +} + + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by iq2000_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +iq2000_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + + +/* Default insn parser. + + The syntax string is scanned and operands are parsed and stored in FIELDS. + Relocs are queued as we go via other callbacks. + + ??? Note that this is currently an all-or-nothing parser. If we fail to + parse the instruction, we return 0 and the caller will start over from + the beginning. Backtracking will be necessary in parsing subexpressions, + but that can be handled there. Not handling backtracking here may get + expensive in the case of the m68k. Deal with later. + + Returns NULL for success, an error message for failure. */ + +static const char * +parse_insn_normal (cd, insn, strp, fields) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + const char **strp; + CGEN_FIELDS *fields; +{ + /* ??? Runtime added insns not handled yet. */ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const char *str = *strp; + const char *errmsg; + const char *p; + const CGEN_SYNTAX_CHAR_TYPE * syn; +#ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ + int past_opcode_p; +#endif + + /* For now we assume the mnemonic is first (there are no leading operands). + We can parse it without needing to set up operand parsing. + GAS's input scrubber will ensure mnemonics are lowercase, but we may + not be called from GAS. */ + p = CGEN_INSN_MNEMONIC (insn); + while (*p && TOLOWER (*p) == TOLOWER (*str)) + ++p, ++str; + + if (* p) + return _("unrecognized instruction"); + +#ifndef CGEN_MNEMONIC_OPERANDS + if (* str && ! ISSPACE (* str)) + return _("unrecognized instruction"); +#endif + + CGEN_INIT_PARSE (cd); + cgen_init_parse_operand (cd); +#ifdef CGEN_MNEMONIC_OPERANDS + past_opcode_p = 0; +#endif + + /* We don't check for (*str != '\0') here because we want to parse + any trailing fake arguments in the syntax string. */ + syn = CGEN_SYNTAX_STRING (syntax); + + /* Mnemonics come first for now, ensure valid string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + abort (); + + ++syn; + + while (* syn != 0) + { + /* Non operand chars must match exactly. */ + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + /* FIXME: While we allow for non-GAS callers above, we assume the + first char after the mnemonic part is a space. */ + /* FIXME: We also take inappropriate advantage of the fact that + GAS's input scrubber will remove extraneous blanks. */ + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) + { +#ifdef CGEN_MNEMONIC_OPERANDS + if (CGEN_SYNTAX_CHAR(* syn) == ' ') + past_opcode_p = 1; +#endif + ++ syn; + ++ str; + } + else if (*str) + { + /* Syntax char didn't match. Can't be this insn. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found `%c')"), + CGEN_SYNTAX_CHAR(*syn), *str); + return msg; + } + else + { + /* Ran out of input. */ + static char msg [80]; + + /* xgettext:c-format */ + sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), + CGEN_SYNTAX_CHAR(*syn)); + return msg; + } + continue; + } + + /* We have an operand of some sort. */ + errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn), + &str, fields); + if (errmsg) + return errmsg; + + /* Done with this operand, continue with next one. */ + ++ syn; + } + + /* If we're at the end of the syntax string, we're done. */ + if (* syn == 0) + { + /* FIXME: For the moment we assume a valid `str' can only contain + blanks now. IE: We needn't try again with a longer version of + the insn and it is assumed that longer versions of insns appear + before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ + while (ISSPACE (* str)) + ++ str; + + if (* str != '\0') + return _("junk at end of line"); /* FIXME: would like to include `str' */ + + return NULL; + } + + /* We couldn't parse it. */ + return _("unrecognized instruction"); +} + +/* Main entry point. + This routine is called for each instruction to be assembled. + STR points to the insn to be assembled. + We assume all necessary tables have been initialized. + The assembled instruction, less any fixups, is stored in BUF. + Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value + still needs to be converted to target byte order, otherwise BUF is an array + of bytes in target byte order. + The result is a pointer to the insn's entry in the opcode table, + or NULL if an error occured (an error message will have already been + printed). + + Note that when processing (non-alias) macro-insns, + this function recurses. + + ??? It's possible to make this cpu-independent. + One would have to deal with a few minor things. + At this point in time doing so would be more of a curiosity than useful + [for example this file isn't _that_ big], but keeping the possibility in + mind helps keep the design clean. */ + +const CGEN_INSN * +iq2000_cgen_assemble_insn (cd, str, fields, buf, errmsg) + CGEN_CPU_DESC cd; + const char *str; + CGEN_FIELDS *fields; + CGEN_INSN_BYTES_PTR buf; + char **errmsg; +{ + const char *start; + CGEN_INSN_LIST *ilist; + const char *parse_errmsg = NULL; + const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; + + /* Skip leading white space. */ + while (ISSPACE (* str)) + ++ str; + + /* The instructions are stored in hashed lists. + Get the first in the list. */ + ilist = CGEN_ASM_LOOKUP_INSN (cd, str); + + /* Keep looking until we find a match. */ + start = str; + for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) + { + const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ + /* Is this insn supported by the selected cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + continue; +#endif + /* If the RELAX attribute is set, this is an insn that shouldn't be + chosen immediately. Instead, it is used during assembler/linker + relaxation if possible. */ + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + continue; + + str = start; + + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + + /* Allow parse/insert handlers to obtain length of insn. */ + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); + if (parse_errmsg != NULL) + continue; + + /* ??? 0 is passed for `pc'. */ + insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, + (bfd_vma) 0); + if (insert_errmsg != NULL) + continue; + + /* It is up to the caller to actually output the insn and any + queued relocs. */ + return insn; + } + + { + static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS + const char *tmp_errmsg; + + /* If requesting verbose error messages, use insert_errmsg. + Failing that, use parse_errmsg. */ + tmp_errmsg = (insert_errmsg ? insert_errmsg : + parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : + _("unrecognized instruction")); + + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start); + else + /* xgettext:c-format */ + sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start); +#else + if (strlen (start) > 50) + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s...'"), start); + else + /* xgettext:c-format */ + sprintf (errbuf, _("bad instruction `%.50s'"), start); +#endif + + *errmsg = errbuf; + return NULL; + } +} + +#if 0 /* This calls back to GAS which we can't do without care. */ + +/* Record each member of OPVALS in the assembler's symbol table. + This lets GAS parse registers for us. + ??? Interesting idea but not currently used. */ + +/* Record each member of OPVALS in the assembler's symbol table. + FIXME: Not currently used. */ + +void +iq2000_cgen_asm_hash_keywords (cd, opvals) + CGEN_CPU_DESC cd; + CGEN_KEYWORD *opvals; +{ + CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); + const CGEN_KEYWORD_ENTRY * ke; + + while ((ke = cgen_keyword_search_next (& search)) != NULL) + { +#if 0 /* Unnecessary, should be done in the search routine. */ + if (! iq2000_cgen_opval_supported (ke)) + continue; +#endif + cgen_asm_record_register (cd, ke->name, ke->value); + } +} + +#endif /* 0 */ diff --git a/opcodes/iq2000-desc.c b/opcodes/iq2000-desc.c new file mode 100644 index 0000000000..a30bf56b8b --- /dev/null +++ b/opcodes/iq2000-desc.c @@ -0,0 +1,2222 @@ +/* CPU data for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include +#include +#include +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "libiberty.h" + +/* Attributes. */ + +static const CGEN_ATTR_ENTRY bool_attr[] = +{ + { "#f", 0 }, + { "#t", 1 }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY MACH_attr[] = +{ + { "base", MACH_BASE }, + { "iq2000", MACH_IQ2000 }, + { "iq10", MACH_IQ10 }, + { "max", MACH_MAX }, + { 0, 0 } +}; + +static const CGEN_ATTR_ENTRY ISA_attr[] = +{ + { "iq2000", ISA_IQ2000 }, + { "max", ISA_MAX }, + { 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "RESERVED", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, + { "PC", &bool_attr[0], &bool_attr[0] }, + { "PROFILE", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, + { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, + { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, + { "SIGNED", &bool_attr[0], &bool_attr[0] }, + { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = +{ + { "MACH", & MACH_attr[0], & MACH_attr[0] }, + { "ALIAS", &bool_attr[0], &bool_attr[0] }, + { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, + { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, + { "COND-CTI", &bool_attr[0], &bool_attr[0] }, + { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, + { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, + { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, + { "RELAX", &bool_attr[0], &bool_attr[0] }, + { "NO-DIS", &bool_attr[0], &bool_attr[0] }, + { "PBB", &bool_attr[0], &bool_attr[0] }, + { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, + { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, + { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] }, + { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] }, + { "USES-RD", &bool_attr[0], &bool_attr[0] }, + { "USES-RS", &bool_attr[0], &bool_attr[0] }, + { "USES-RT", &bool_attr[0], &bool_attr[0] }, + { "USES-R31", &bool_attr[0], &bool_attr[0] }, + { 0, 0, 0 } +}; + +/* Instruction set variants. */ + +static const CGEN_ISA iq2000_cgen_isa_table[] = { + { "iq2000", 32, 32, 32, 32 }, + { 0, 0, 0, 0, 0 } +}; + +/* Machine variants. */ + +static const CGEN_MACH iq2000_cgen_mach_table[] = { + { "iq2000", "iq2000", MACH_IQ2000, 0 }, + { "iq10", "iq10", MACH_IQ10, 0 }, + { 0, 0, 0, 0 } +}; + +static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] = +{ + { "r0", 0, {0, {0}}, 0, 0 }, + { "%0", 0, {0, {0}}, 0, 0 }, + { "r1", 1, {0, {0}}, 0, 0 }, + { "%1", 1, {0, {0}}, 0, 0 }, + { "r2", 2, {0, {0}}, 0, 0 }, + { "%2", 2, {0, {0}}, 0, 0 }, + { "r3", 3, {0, {0}}, 0, 0 }, + { "%3", 3, {0, {0}}, 0, 0 }, + { "r4", 4, {0, {0}}, 0, 0 }, + { "%4", 4, {0, {0}}, 0, 0 }, + { "r5", 5, {0, {0}}, 0, 0 }, + { "%5", 5, {0, {0}}, 0, 0 }, + { "r6", 6, {0, {0}}, 0, 0 }, + { "%6", 6, {0, {0}}, 0, 0 }, + { "r7", 7, {0, {0}}, 0, 0 }, + { "%7", 7, {0, {0}}, 0, 0 }, + { "r8", 8, {0, {0}}, 0, 0 }, + { "%8", 8, {0, {0}}, 0, 0 }, + { "r9", 9, {0, {0}}, 0, 0 }, + { "%9", 9, {0, {0}}, 0, 0 }, + { "r10", 10, {0, {0}}, 0, 0 }, + { "%10", 10, {0, {0}}, 0, 0 }, + { "r11", 11, {0, {0}}, 0, 0 }, + { "%11", 11, {0, {0}}, 0, 0 }, + { "r12", 12, {0, {0}}, 0, 0 }, + { "%12", 12, {0, {0}}, 0, 0 }, + { "r13", 13, {0, {0}}, 0, 0 }, + { "%13", 13, {0, {0}}, 0, 0 }, + { "r14", 14, {0, {0}}, 0, 0 }, + { "%14", 14, {0, {0}}, 0, 0 }, + { "r15", 15, {0, {0}}, 0, 0 }, + { "%15", 15, {0, {0}}, 0, 0 }, + { "r16", 16, {0, {0}}, 0, 0 }, + { "%16", 16, {0, {0}}, 0, 0 }, + { "r17", 17, {0, {0}}, 0, 0 }, + { "%17", 17, {0, {0}}, 0, 0 }, + { "r18", 18, {0, {0}}, 0, 0 }, + { "%18", 18, {0, {0}}, 0, 0 }, + { "r19", 19, {0, {0}}, 0, 0 }, + { "%19", 19, {0, {0}}, 0, 0 }, + { "r20", 20, {0, {0}}, 0, 0 }, + { "%20", 20, {0, {0}}, 0, 0 }, + { "r21", 21, {0, {0}}, 0, 0 }, + { "%21", 21, {0, {0}}, 0, 0 }, + { "r22", 22, {0, {0}}, 0, 0 }, + { "%22", 22, {0, {0}}, 0, 0 }, + { "r23", 23, {0, {0}}, 0, 0 }, + { "%23", 23, {0, {0}}, 0, 0 }, + { "r24", 24, {0, {0}}, 0, 0 }, + { "%24", 24, {0, {0}}, 0, 0 }, + { "r25", 25, {0, {0}}, 0, 0 }, + { "%25", 25, {0, {0}}, 0, 0 }, + { "r26", 26, {0, {0}}, 0, 0 }, + { "%26", 26, {0, {0}}, 0, 0 }, + { "r27", 27, {0, {0}}, 0, 0 }, + { "%27", 27, {0, {0}}, 0, 0 }, + { "r28", 28, {0, {0}}, 0, 0 }, + { "%28", 28, {0, {0}}, 0, 0 }, + { "r29", 29, {0, {0}}, 0, 0 }, + { "%29", 29, {0, {0}}, 0, 0 }, + { "r30", 30, {0, {0}}, 0, 0 }, + { "%30", 30, {0, {0}}, 0, 0 }, + { "r31", 31, {0, {0}}, 0, 0 }, + { "%31", 31, {0, {0}}, 0, 0 } +}; + +CGEN_KEYWORD iq2000_cgen_opval_gr_names = +{ + & iq2000_cgen_opval_gr_names_entries[0], + 64, + 0, 0, 0, 0, "" +}; + + +/* The hardware table. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_HW_##a) +#else +#define A(a) (1 << CGEN_HW_/**/a) +#endif + +const CGEN_HW_ENTRY iq2000_cgen_hw_table[] = +{ + { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<name) + { + if (strcmp (name, table->bfd_name) == 0) + return table; + ++table; + } + abort (); +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_hw_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0]; + /* MAX_HW is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_HW_ENTRY **selected = + (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); + + cd->hw_table.init_entries = init; + cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); + memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); + /* ??? For now we just use machs to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->hw_table.entries = selected; + cd->hw_table.num_entries = MAX_HW; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_ifield_table (cd) + CGEN_CPU_TABLE *cd; +{ + cd->ifld_table = & iq2000_cgen_ifld_table[0]; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ + +static void +build_operand_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + int machs = cd->machs; + const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0]; + /* MAX_OPERANDS is only an upper bound on the number of selected entries. + However each entry is indexed by it's enum so there can be holes in + the table. */ + const CGEN_OPERAND **selected = + (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + + cd->operand_table.init_entries = init; + cd->operand_table.entry_size = sizeof (CGEN_OPERAND); + memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); + /* ??? For now we just use mach to determine which ones we want. */ + for (i = 0; init[i].name != NULL; ++i) + if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) + & machs) + selected[init[i].type] = &init[i]; + cd->operand_table.entries = selected; + cd->operand_table.num_entries = MAX_OPERANDS; +} + +/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. + ??? This could leave out insns not supported by the specified mach/isa, + but that would cause errors like "foo only supported by bar" to become + "unknown insn", so for now we include all insns and require the app to + do the checking later. + ??? On the other hand, parsing of such insns may require their hardware or + operand elements to be in the table [which they mightn't be]. */ + +static void +build_insn_table (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; + CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); + + memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); + for (i = 0; i < MAX_INSNS; ++i) + insns[i].base = &ib[i]; + cd->insn_table.init_entries = insns; + cd->insn_table.entry_size = sizeof (CGEN_IBASE); + cd->insn_table.num_init_entries = MAX_INSNS; +} + +/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ + +static void +iq2000_cgen_rebuild_tables (cd) + CGEN_CPU_TABLE *cd; +{ + int i; + unsigned int isas = cd->isas; + unsigned int machs = cd->machs; + + cd->int_insn_p = CGEN_INT_INSN_P; + + /* Data derived from the isa spec. */ +#define UNSET (CGEN_SIZE_UNKNOWN + 1) + cd->default_insn_bitsize = UNSET; + cd->base_insn_bitsize = UNSET; + cd->min_insn_bitsize = 65535; /* some ridiculously big number */ + cd->max_insn_bitsize = 0; + for (i = 0; i < MAX_ISAS; ++i) + if (((1 << i) & isas) != 0) + { + const CGEN_ISA *isa = & iq2000_cgen_isa_table[i]; + + /* Default insn sizes of all selected isas must be + equal or we set the result to 0, meaning "unknown". */ + if (cd->default_insn_bitsize == UNSET) + cd->default_insn_bitsize = isa->default_insn_bitsize; + else if (isa->default_insn_bitsize == cd->default_insn_bitsize) + ; /* this is ok */ + else + cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Base insn sizes of all selected isas must be equal + or we set the result to 0, meaning "unknown". */ + if (cd->base_insn_bitsize == UNSET) + cd->base_insn_bitsize = isa->base_insn_bitsize; + else if (isa->base_insn_bitsize == cd->base_insn_bitsize) + ; /* this is ok */ + else + cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; + + /* Set min,max insn sizes. */ + if (isa->min_insn_bitsize < cd->min_insn_bitsize) + cd->min_insn_bitsize = isa->min_insn_bitsize; + if (isa->max_insn_bitsize > cd->max_insn_bitsize) + cd->max_insn_bitsize = isa->max_insn_bitsize; + } + + /* Data derived from the mach spec. */ + for (i = 0; i < MAX_MACHS; ++i) + if (((1 << i) & machs) != 0) + { + const CGEN_MACH *mach = & iq2000_cgen_mach_table[i]; + + if (mach->insn_chunk_bitsize != 0) + { + if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) + { + fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n", + cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); + abort (); + } + + cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; + } + } + + /* Determine which hw elements are used by MACH. */ + build_hw_table (cd); + + /* Build the ifield table. */ + build_ifield_table (cd); + + /* Determine which operands are used by MACH/ISA. */ + build_operand_table (cd); + + /* Build the instruction table. */ + build_insn_table (cd); +} + +/* Initialize a cpu table and return a descriptor. + It's much like opening a file, and must be the first function called. + The arguments are a set of (type/value) pairs, terminated with + CGEN_CPU_OPEN_END. + + Currently supported values: + CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr + CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr + CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name + CGEN_CPU_OPEN_ENDIAN: specify endian choice + CGEN_CPU_OPEN_END: terminates arguments + + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. + + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) +{ + CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); + static int init_p; + unsigned int isas = 0; /* 0 = "unspecified" */ + unsigned int machs = 0; /* 0 = "unspecified" */ + enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; + va_list ap; + + if (! init_p) + { + init_tables (); + init_p = 1; + } + + memset (cd, 0, sizeof (*cd)); + + va_start (ap, arg_type); + while (arg_type != CGEN_CPU_OPEN_END) + { + switch (arg_type) + { + case CGEN_CPU_OPEN_ISAS : + isas = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_MACHS : + machs = va_arg (ap, unsigned int); + break; + case CGEN_CPU_OPEN_BFDMACH : + { + const char *name = va_arg (ap, const char *); + const CGEN_MACH *mach = + lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name); + + machs |= 1 << mach->num; + break; + } + case CGEN_CPU_OPEN_ENDIAN : + endian = va_arg (ap, enum cgen_endian); + break; + default : + fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n", + arg_type); + abort (); /* ??? return NULL? */ + } + arg_type = va_arg (ap, enum cgen_cpu_open_arg); + } + va_end (ap); + + /* mach unspecified means "all" */ + if (machs == 0) + machs = (1 << MAX_MACHS) - 1; + /* base mach is always selected */ + machs |= 1; + /* isa unspecified means "all" */ + if (isas == 0) + isas = (1 << MAX_ISAS) - 1; + if (endian == CGEN_ENDIAN_UNKNOWN) + { + /* ??? If target has only one, could have a default. */ + fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n"); + abort (); + } + + cd->isas = isas; + cd->machs = machs; + cd->endian = endian; + /* FIXME: for the sparc case we can determine insn-endianness statically. + The worry here is where both data and insn endian can be independently + chosen, in which case this function will need another argument. + Actually, will want to allow for more arguments in the future anyway. */ + cd->insn_endian = endian; + + /* Table (re)builder. */ + cd->rebuild_tables = iq2000_cgen_rebuild_tables; + iq2000_cgen_rebuild_tables (cd); + + /* Default to not allowing signed overflow. */ + cd->signed_overflow_ok_p = 0; + + return (CGEN_CPU_DESC) cd; +} + +/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. + MACH_NAME is the bfd name of the mach. */ + +CGEN_CPU_DESC +iq2000_cgen_cpu_open_1 (mach_name, endian) + const char *mach_name; + enum cgen_endian endian; +{ + return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, endian, + CGEN_CPU_OPEN_END); +} + +/* Close a cpu table. + ??? This can live in a machine independent file, but there's currently + no place to put this file (there's no libcgen). libopcodes is the wrong + place as some simulator ports use this but they don't use libopcodes. */ + +void +iq2000_cgen_cpu_close (cd) + CGEN_CPU_DESC cd; +{ + unsigned int i; + CGEN_INSN *insns; + + if (cd->macro_insn_table.init_entries) + { + insns = cd->macro_insn_table.init_entries; + for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX ((insns))) + regfree(CGEN_INSN_RX (insns)); + } + } + + if (cd->insn_table.init_entries) + { + insns = cd->insn_table.init_entries; + for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) + { + if (CGEN_INSN_RX (insns)) + regfree(CGEN_INSN_RX (insns)); + } + } + + + + if (cd->macro_insn_table.init_entries) + free ((CGEN_INSN *) cd->macro_insn_table.init_entries); + + if (cd->insn_table.init_entries) + free ((CGEN_INSN *) cd->insn_table.init_entries); + + if (cd->hw_table.entries) + free ((CGEN_HW_ENTRY *) cd->hw_table.entries); + + if (cd->operand_table.entries) + free ((CGEN_HW_ENTRY *) cd->operand_table.entries); + + free (cd); +} + diff --git a/opcodes/iq2000-desc.h b/opcodes/iq2000-desc.h new file mode 100644 index 0000000000..584c3ded75 --- /dev/null +++ b/opcodes/iq2000-desc.h @@ -0,0 +1,302 @@ +/* CPU data header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IQ2000_CPU_H +#define IQ2000_CPU_H + +#define CGEN_ARCH iq2000 + +/* Given symbol S, return iq2000_cgen_. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define CGEN_SYM(s) iq2000##_cgen_##s +#else +#define CGEN_SYM(s) iq2000/**/_cgen_/**/s +#endif + + +/* Selected cpu families. */ +#define HAVE_CPU_IQ2000BF +#define HAVE_CPU_IQ10BF + +#define CGEN_INSN_LSB0_P 1 + +/* Minimum size of any insn (in bytes). */ +#define CGEN_MIN_INSN_SIZE 4 + +/* Maximum size of any insn (in bytes). */ +#define CGEN_MAX_INSN_SIZE 4 + +#define CGEN_INT_INSN_P 1 + +/* Maximum number of syntax elements in an instruction. */ +#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 + +/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. + e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands + we can't hash on everything up to the space. */ +#define CGEN_MNEMONIC_OPERANDS + +/* Maximum number of fields in an instruction. */ +#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 + +/* Enums. */ + +/* Enum declaration for . */ +typedef enum gr_names { + H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1 + , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3 + , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5 + , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7 + , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9 + , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11 + , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13 + , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15 + , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17 + , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19 + , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21 + , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23 + , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25 + , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27 + , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29 + , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31 +} GR_NAMES; + +/* Enum declaration for primary opcodes. */ +typedef enum opcodes { + OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3 + , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7 + , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11 + , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15 + , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19 + , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23 + , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27 + , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31 + , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36 + , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41 + , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47 + , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63 +} OPCODES; + +/* Enum declaration for iq10-only primary opcodes. */ +typedef enum q10_opcodes { + OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47 + , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63 +} Q10_OPCODES; + +/* Enum declaration for branch sub-opcodes. */ +typedef enum regimm_functions { + FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3 + , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7 + , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16 + , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20 + , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23 +} REGIMM_FUNCTIONS; + +/* Enum declaration for function sub-opcodes. */ +typedef enum functions { + FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3 + , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7 + , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12 + , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33 + , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37 + , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42 + , FUNC_SLTU = 43, FUNC_MRGB = 45 +} FUNCTIONS; + +/* Enum declaration for iq10-only special function sub-opcodes. */ +typedef enum q10s_functions { + FUNC10_YIELD = 14, FUNC10_CNT1S = 46 +} Q10S_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_functions { + FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3 + , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7 + , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12 + , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18 + , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33 + , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37 + , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41 + , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0 + , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8 + , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20 + , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29 + , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35 + , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41 + , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48 + , FUNC10_CM32SA = 56 +} COP_FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_4functions { + FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6 +} COP_CM128_4FUNCTIONS; + +/* Enum declaration for iq10 function sub-opcodes. */ +typedef enum cop_cm128_3functions { + FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7 +} COP_CM128_3FUNCTIONS; + +/* Enum declaration for iq10 coprocessor sub-opcodes. */ +typedef enum cop2_functions { + FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3 + , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5 + , FUNC10_WBI = 6, FUNC10_WBIU = 7 +} COP2_FUNCTIONS; + +/* Enum declaration for iq10 coprocessor cam sub-opcodes. */ +typedef enum cop3_cam_functions { + FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19 +} COP3_CAM_FUNCTIONS; + +/* Attributes. */ + +/* Enum declaration for machine type selection. */ +typedef enum mach_attr { + MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX +} MACH_ATTR; + +/* Enum declaration for instruction set selection. */ +typedef enum isa_attr { + ISA_IQ2000, ISA_MAX +} ISA_ATTR; + +/* Number of architecture variants. */ +#define MAX_ISAS 1 +#define MAX_MACHS ((int) MACH_MAX) + +/* Ifield support. */ + +extern const struct cgen_ifld iq2000_cgen_ifld_table[]; + +/* Ifield attribute indices. */ + +/* Enum declaration for cgen_ifld attrs. */ +typedef enum cgen_ifld_attr { + CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED + , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 + , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS +} CGEN_IFLD_ATTR; + +/* Number of non-boolean elements in cgen_ifld_attr. */ +#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) + +/* Enum declaration for iq2000 ifield types. */ +typedef enum ifield_type { + IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS + , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP + , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM + , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG + , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT + , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL + , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19 + , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z + , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z + , IQ2000_F_CM_4Z, IQ2000_F_MAX +} IFIELD_TYPE; + +#define MAX_IFLD ((int) IQ2000_F_MAX) + +/* Hardware attribute indices. */ + +/* Enum declaration for cgen_hw attrs. */ +typedef enum cgen_hw_attr { + CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE + , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS +} CGEN_HW_ATTR; + +/* Number of non-boolean elements in cgen_hw_attr. */ +#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) + +/* Enum declaration for iq2000 hardware types. */ +typedef enum cgen_hw_type { + HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR + , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX +} CGEN_HW_TYPE; + +#define MAX_HW ((int) HW_MAX) + +/* Operand attribute indices. */ + +/* Enum declaration for cgen_operand attrs. */ +typedef enum cgen_operand_attr { + CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY + , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS +} CGEN_OPERAND_ATTR; + +/* Number of non-boolean elements in cgen_operand_attr. */ +#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) + +/* Enum declaration for iq2000 operand types. */ +typedef enum cgen_operand_type { + IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD + , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT + , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG + , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT + , IQ2000_OPERAND_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y + , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z + , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM + , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10 + , IQ2000_OPERAND_MAX +} CGEN_OPERAND_TYPE; + +/* Number of operands types. */ +#define MAX_OPERANDS 32 + +/* Maximum number of operands referenced by any insn. */ +#define MAX_OPERAND_INSTANCES 8 + +/* Insn attribute indices. */ + +/* Enum declaration for cgen_insn attrs. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY + , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS + , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS +} CGEN_INSN_ATTR; + +/* Number of non-boolean elements in cgen_insn_attr. */ +#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) + +/* cgen.h uses things we just defined. */ +#include "opcode/cgen.h" + +/* Attributes. */ +extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[]; +extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[]; + +/* Hardware decls. */ + +extern CGEN_KEYWORD iq2000_cgen_opval_gr_names; + + + + +#endif /* IQ2000_CPU_H */ diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c new file mode 100644 index 0000000000..49e01201dc --- /dev/null +++ b/opcodes/iq2000-dis.c @@ -0,0 +1,619 @@ +/* Disassembler interface for targets using CGEN. -*- C -*- + CGEN: Cpu tools GENerator + +THIS FILE IS MACHINE GENERATED WITH CGEN. +- the resultant file is machine generated, cgen-dis.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" + +/* Default text to print if an instruction isn't recognized. */ +#define UNKNOWN_INSN_MSG _("*unknown*") + +static void print_normal + PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); +static void print_address + PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); +static void print_keyword + PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); +static void print_insn_normal + PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, + bfd_vma, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); +static int default_print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); + +/* -- disassembler routines inserted here */ + + +void iq2000_cgen_print_operand + PARAMS ((CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, + void const *, bfd_vma, int)); + +/* Main entry point for printing operands. + XINFO is a `void *' and not a `disassemble_info *' to not put a requirement + of dis-asm.h on cgen.h. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +void +iq2000_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) + CGEN_CPU_DESC cd; + int opindex; + PTR xinfo; + CGEN_FIELDS *fields; + void const *attrs ATTRIBUTE_UNUSED; + bfd_vma pc; + int length; +{ + disassemble_info *info = (disassemble_info *) xinfo; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rs, 0); + break; + case IQ2000_OPERAND_BASEOFF : + print_address (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_BITNUM : + print_normal (cd, info, fields->f_rt, 0, pc, length); + break; + case IQ2000_OPERAND_BYTECOUNT : + print_normal (cd, info, fields->f_bytecount, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Y : + print_normal (cd, info, fields->f_cam_y, 0, pc, length); + break; + case IQ2000_OPERAND_CAM_Z : + print_normal (cd, info, fields->f_cam_z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3FUNC : + print_normal (cd, info, fields->f_cm_3func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_3Z : + print_normal (cd, info, fields->f_cm_3z, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4FUNC : + print_normal (cd, info, fields->f_cm_4func, 0, pc, length); + break; + case IQ2000_OPERAND_CM_4Z : + print_normal (cd, info, fields->f_cm_4z, 0, pc, length); + break; + case IQ2000_OPERAND_COUNT : + print_normal (cd, info, fields->f_count, 0, pc, length); + break; + case IQ2000_OPERAND_EXECODE : + print_normal (cd, info, fields->f_excode, 0, pc, length); + break; + case IQ2000_OPERAND_HI16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_IMM : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_INDEX : + print_normal (cd, info, fields->f_index, 0, pc, length); + break; + case IQ2000_OPERAND_JMPTARG : + print_address (cd, info, fields->f_jtarg, 0|(1<f_jtargq10, 0|(1<f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_MASK : + print_normal (cd, info, fields->f_mask, 0, pc, length); + break; + case IQ2000_OPERAND_MASKL : + print_normal (cd, info, fields->f_maskl, 0, pc, length); + break; + case IQ2000_OPERAND_MASKQ10 : + print_normal (cd, info, fields->f_maskq10, 0, pc, length); + break; + case IQ2000_OPERAND_MASKR : + print_normal (cd, info, fields->f_rs, 0, pc, length); + break; + case IQ2000_OPERAND_MLO16 : + print_normal (cd, info, fields->f_imm, 0, pc, length); + break; + case IQ2000_OPERAND_OFFSET : + print_address (cd, info, fields->f_offset, 0|(1<f_rd, 0); + break; + case IQ2000_OPERAND_RD_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rd_rs, 0|(1<f_rd_rt, 0|(1<f_rs, 0); + break; + case IQ2000_OPERAND_RT : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt, 0); + break; + case IQ2000_OPERAND_RT_RS : + print_keyword (cd, info, & iq2000_cgen_opval_gr_names, fields->f_rt_rs, 0|(1<f_shamt, 0, pc, length); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), + opindex); + abort (); + } +} + +cgen_print_fn * const iq2000_cgen_print_handlers[] = +{ + print_insn_normal, +}; + + +void +iq2000_cgen_init_dis (cd) + CGEN_CPU_DESC cd; +{ + iq2000_cgen_init_opcode_table (cd); + iq2000_cgen_init_ibld_table (cd); + cd->print_handlers = & iq2000_cgen_print_handlers[0]; + cd->print_operand = iq2000_cgen_print_operand; +} + + +/* Default print handler. */ + +static void +print_normal (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + long value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_NORMAL + CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", value); + else + (*info->fprintf_func) (info->stream, "0x%lx", value); +} + +/* Default address handler. */ + +static void +print_address (cd, dis_info, value, attrs, pc, length) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + bfd_vma value; + unsigned int attrs; + bfd_vma pc ATTRIBUTE_UNUSED; + int length ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + +#ifdef CGEN_PRINT_ADDRESS + CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); +#endif + + /* Print the operand as directed by the attributes. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) + ; /* nothing to do */ + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) + (*info->print_address_func) (value, info); + else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) + (*info->fprintf_func) (info->stream, "%ld", (long) value); + else + (*info->fprintf_func) (info->stream, "0x%lx", (long) value); +} + +/* Keyword print handler. */ + +static void +print_keyword (cd, dis_info, keyword_table, value, attrs) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + PTR dis_info; + CGEN_KEYWORD *keyword_table; + long value; + unsigned int attrs ATTRIBUTE_UNUSED; +{ + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_KEYWORD_ENTRY *ke; + + ke = cgen_keyword_lookup_value (keyword_table, value); + if (ke != NULL) + (*info->fprintf_func) (info->stream, "%s", ke->name); + else + (*info->fprintf_func) (info->stream, "???"); +} + +/* Default insn printer. + + DIS_INFO is defined as `PTR' so the disassembler needn't know anything + about disassemble_info. */ + +static void +print_insn_normal (cd, dis_info, insn, fields, pc, length) + CGEN_CPU_DESC cd; + PTR dis_info; + const CGEN_INSN *insn; + CGEN_FIELDS *fields; + bfd_vma pc; + int length; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + disassemble_info *info = (disassemble_info *) dis_info; + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_INIT_PRINT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + if (CGEN_SYNTAX_MNEMONIC_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); + continue; + } + if (CGEN_SYNTAX_CHAR_P (*syn)) + { + (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); + continue; + } + + /* We have an operand. */ + iq2000_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, + fields, CGEN_INSN_ATTRS (insn), pc, length); + } +} + +/* Subroutine of print_insn. Reads an insn into the given buffers and updates + the extract info. + Returns 0 if all is well, non-zero otherwise. */ + +static int +read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + bfd_vma pc; + disassemble_info *info; + char *buf; + int buflen; + CGEN_EXTRACT_INFO *ex_info; + unsigned long *insn_value; +{ + int status = (*info->read_memory_func) (pc, buf, buflen, info); + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + ex_info->dis_info = info; + ex_info->valid = (1 << buflen) - 1; + ex_info->insn_bytes = buf; + + *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); + return 0; +} + +/* Utility to print an insn. + BUF is the base part of the insn, target byte order, BUFLEN bytes long. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +print_insn (cd, pc, info, buf, buflen) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; + char *buf; + unsigned int buflen; +{ + CGEN_INSN_INT insn_value; + const CGEN_INSN_LIST *insn_list; + CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); + + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; + + /* The instructions are stored in hash lists. + Pick the first one and keep trying until we find the right one. */ + + insn_list = CGEN_DIS_LOOKUP_INSN (cd, buf, insn_value); + while (insn_list != NULL) + { + const CGEN_INSN *insn = insn_list->insn; + CGEN_FIELDS fields; + int length; + unsigned long insn_value_cropped; + +#ifdef CGEN_VALIDATE_INSN_SUPPORTED + /* Not needed as insn shouldn't be in hash lists if not supported. */ + /* Supported by this cpu? */ + if (! iq2000_cgen_insn_supported (cd, insn)) + { + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + continue; + } +#endif + + /* Basic bit mask must be correct. */ + /* ??? May wish to allow target to defer this check until the extract + handler. */ + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) + == CGEN_INSN_BASE_VALUE (insn)) + { + /* Printing is handled in two passes. The first pass parses the + machine insn and extracts the fields. The second pass prints + them. */ + + /* Make sure the entire insn is loaded into insn_value, if it + can fit. */ + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + { + unsigned long full_insn_value; + int rc = read_insn (cd, pc, info, buf, + CGEN_INSN_BITSIZE (insn) / 8, + & ex_info, & full_insn_value); + if (rc != 0) + return rc; + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, full_insn_value, &fields, pc); + } + else + length = CGEN_EXTRACT_FN (cd, insn) + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); + + /* length < 0 -> error */ + if (length < 0) + return length; + if (length > 0) + { + CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); + /* length is in bits, result is in bytes */ + return length / 8; + } + } + + insn_list = CGEN_DIS_NEXT_INSN (insn_list); + } + + return 0; +} + +/* Default value for CGEN_PRINT_INSN. + The result is the size of the insn in bytes or zero for an unknown insn + or -1 if an error occured fetching bytes. */ + +#ifndef CGEN_PRINT_INSN +#define CGEN_PRINT_INSN default_print_insn +#endif + +static int +default_print_insn (cd, pc, info) + CGEN_CPU_DESC cd; + bfd_vma pc; + disassemble_info *info; +{ + char buf[CGEN_MAX_INSN_SIZE]; + int buflen; + int status; + + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return -1; + } + + return print_insn (cd, pc, info, buf, buflen); +} + +/* Main entry point. + Print one instruction from PC on INFO->STREAM. + Return the size of the instruction (in bytes). */ + +typedef struct cpu_desc_list { + struct cpu_desc_list *next; + int isa; + int mach; + int endian; + CGEN_CPU_DESC cd; +} cpu_desc_list; + +int +print_insn_iq2000 (pc, info) + bfd_vma pc; + disassemble_info *info; +{ + static cpu_desc_list *cd_list = 0; + cpu_desc_list *cl = 0; + static CGEN_CPU_DESC cd = 0; + static int prev_isa; + static int prev_mach; + static int prev_endian; + int length; + int isa,mach; + int endian = (info->endian == BFD_ENDIAN_BIG + ? CGEN_ENDIAN_BIG + : CGEN_ENDIAN_LITTLE); + enum bfd_architecture arch; + + /* ??? gdb will set mach but leave the architecture as "unknown" */ +#ifndef CGEN_BFD_ARCH +#define CGEN_BFD_ARCH bfd_arch_iq2000 +#endif + arch = info->arch; + if (arch == bfd_arch_unknown) + arch = CGEN_BFD_ARCH; + + /* There's no standard way to compute the machine or isa number + so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + +#ifdef CGEN_COMPUTE_ISA + isa = CGEN_COMPUTE_ISA (info); +#else + isa = info->insn_sets; +#endif + + /* If we've switched cpu's, try to find a handle we've used before */ + if (cd + && (isa != prev_isa + || mach != prev_mach + || endian != prev_endian)) + { + cd = 0; + for (cl = cd_list; cl; cl = cl->next) + { + if (cl->isa == isa && + cl->mach == mach && + cl->endian == endian) + { + cd = cl->cd; + break; + } + } + } + + /* If we haven't initialized yet, initialize the opcode table. */ + if (! cd) + { + const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); + const char *mach_name; + + if (!arch_type) + abort (); + mach_name = arch_type->printable_name; + + prev_isa = isa; + prev_mach = mach; + prev_endian = endian; + cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, + CGEN_CPU_OPEN_BFDMACH, mach_name, + CGEN_CPU_OPEN_ENDIAN, prev_endian, + CGEN_CPU_OPEN_END); + if (!cd) + abort (); + + /* save this away for future reference */ + cl = xmalloc (sizeof (struct cpu_desc_list)); + cl->cd = cd; + cl->isa = isa; + cl->mach = mach; + cl->endian = endian; + cl->next = cd_list; + cd_list = cl; + + iq2000_cgen_init_dis (cd); + } + + /* We try to have as much common code as possible. + But at this point some targets need to take over. */ + /* ??? Some targets may need a hook elsewhere. Try to avoid this, + but if not possible try to move this hook elsewhere rather than + have two hooks. */ + length = CGEN_PRINT_INSN (cd, pc, info); + if (length > 0) + return length; + if (length < 0) + return -1; + + (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); + return cd->default_insn_bitsize / 8; +} diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c new file mode 100644 index 0000000000..5a29228c08 --- /dev/null +++ b/opcodes/iq2000-ibld.c @@ -0,0 +1,1394 @@ +/* Instruction building/extraction support for iq2000. -*- C -*- + +THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. +- the resultant file is machine generated, cgen-ibld.in isn't + +Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ??? Eventually more and more of this stuff can go to cpu-independent files. + Keep that in mind. */ + +#include "sysdep.h" +#include +#include "ansidecl.h" +#include "dis-asm.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "opintl.h" +#include "safe-ctype.h" + +#undef min +#define min(a,b) ((a) < (b) ? (a) : (b)) +#undef max +#define max(a,b) ((a) > (b) ? (a) : (b)) + +/* Used by the ifield rtx function. */ +#define FLD(f) (fields->f) + +static const char * insert_normal + PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); +static const char * insert_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); +static int extract_normal + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *)); +static int extract_insn_normal + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P +static void put_insn_int_value + PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif + +/* Operand insertion. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of insert_normal. */ + +static CGEN_INLINE void +insert_1 (cd, value, start, length, word_length, bufp) + CGEN_CPU_DESC cd; + unsigned long value; + int start,length,word_length; + unsigned char *bufp; +{ + unsigned long x,mask; + int shift; + + x = cgen_get_insn_value (cd, bufp, word_length); + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + x = (x & ~(mask << shift)) | ((value & mask) << shift); + + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default insertion routine. + + ATTRS is a mask of the boolean attributes. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + The result is an error message or NULL if success. */ + +/* ??? This duplicates functionality with bfd's howto table and + bfd_install_relocation. */ +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static const char * +insert_normal (cd, value, attrs, word_offset, start, length, word_length, + total_length, buffer) + CGEN_CPU_DESC cd; + long value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_BYTES_PTR buffer; +{ + static char errbuf[100]; + /* Written this way to avoid undefined behaviour. */ + unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the base-insn-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Ensure VALUE will fit. */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + { + unsigned long maxval = mask; + + if ((unsigned long) value > maxval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%lu not between 0 and %lu)"), + value, maxval); + return errbuf; + } + } + else + { + if (! cgen_signed_overflow_ok_p (cd)) + { + long minval = - (1L << (length - 1)); + long maxval = (1L << (length - 1)) - 1; + + if (value < minval || value > maxval) + { + sprintf + /* xgettext:c-format */ + (errbuf, _("operand out of range (%ld not between %ld and %ld)"), + value, minval, maxval); + return errbuf; + } + } + } + +#if CGEN_INT_INSN_P + + { + int shift; + + if (CGEN_INSN_LSB0_P) + shift = (word_offset + start + 1) - length; + else + shift = total_length - (word_offset + start + length); + *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); + } + +#else /* ! CGEN_INT_INSN_P */ + + { + unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; + + insert_1 (cd, value, start, length, word_length, bufp); + } + +#endif /* ! CGEN_INT_INSN_P */ + + return NULL; +} + +/* Default insn builder (insert handler). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). + The result is an error message or NULL if success. */ + +static const char * +insert_insn_normal (cd, insn, fields, buffer, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + unsigned long value; + const CGEN_SYNTAX_CHAR_TYPE * syn; + + CGEN_INIT_INSERT (cd); + value = CGEN_INSN_BASE_VALUE (insn); + + /* If we're recording insns as numbers (rather than a string of bytes), + target byte order handling is deferred until later. */ + +#if CGEN_INT_INSN_P + + put_insn_int_value (cd, buffer, cd->base_insn_bitsize, + CGEN_FIELDS_BITSIZE (fields), value); + +#else + + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value); + +#endif /* ! CGEN_INT_INSN_P */ + + /* ??? It would be better to scan the format's fields. + Still need to be able to insert a value based on the operand though; + e.g. storing a branch displacement that got resolved later. + Needs more thought first. */ + + for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) + { + const char *errmsg; + + if (CGEN_SYNTAX_CHAR_P (* syn)) + continue; + + errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + fields, buffer, pc); + if (errmsg) + return errmsg; + } + + return NULL; +} + +#if CGEN_INT_INSN_P +/* Cover function to store an insn value into an integral insn. Must go here + because it needs -desc.h for CGEN_INT_INSN_P. */ + +static void +put_insn_int_value (cd, buf, length, insn_length, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_INSN_BYTES_PTR buf; + int length; + int insn_length; + CGEN_INSN_INT value; +{ + /* For architectures with insns smaller than the base-insn-bitsize, + length may be too big. */ + if (length > insn_length) + *buf = value; + else + { + int shift = insn_length - length; + /* Written this way to avoid undefined behaviour. */ + CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1; + *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); + } +} +#endif + +/* Operand extraction. */ + +#if ! CGEN_INT_INSN_P + +/* Subroutine of extract_normal. + Ensure sufficient bytes are cached in EX_INFO. + OFFSET is the offset in bytes from the start of the insn of the value. + BYTES is the length of the needed value. + Returns 1 for success, 0 for failure. */ + +static CGEN_INLINE int +fill_cache (cd, ex_info, offset, bytes, pc) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info; + int offset, bytes; + bfd_vma pc; +{ + /* It's doubtful that the middle part has already been fetched so + we don't optimize that case. kiss. */ + unsigned int mask; + disassemble_info *info = (disassemble_info *) ex_info->dis_info; + + /* First do a quick check. */ + mask = (1 << bytes) - 1; + if (((ex_info->valid >> offset) & mask) == mask) + return 1; + + /* Search for the first byte we need to read. */ + for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) + if (! (mask & ex_info->valid)) + break; + + if (bytes) + { + int status; + + pc += offset; + status = (*info->read_memory_func) + (pc, ex_info->insn_bytes + offset, bytes, info); + + if (status != 0) + { + (*info->memory_error_func) (status, pc, info); + return 0; + } + + ex_info->valid |= ((1 << bytes) - 1) << offset; + } + + return 1; +} + +/* Subroutine of extract_normal. */ + +static CGEN_INLINE long +extract_1 (cd, ex_info, start, length, word_length, bufp, pc) + CGEN_CPU_DESC cd; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + int start,length,word_length; + unsigned char *bufp; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + unsigned long x; + int shift; +#if 0 + int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; +#endif + x = cgen_get_insn_value (cd, bufp, word_length); + + if (CGEN_INSN_LSB0_P) + shift = (start + 1) - length; + else + shift = (word_length - (start + length)); + return x >> shift; +} + +#endif /* ! CGEN_INT_INSN_P */ + +/* Default extraction routine. + + INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, + or sometimes less for cases like the m32r where the base insn size is 32 + but some insns are 16 bits. + ATTRS is a mask of the boolean attributes. We only need `SIGNED', + but for generality we take a bitmask of all of them. + WORD_OFFSET is the offset in bits from the start of the insn of the value. + WORD_LENGTH is the length of the word in bits in which the value resides. + START is the starting bit number in the word, architecture origin. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn in bits. + + Returns 1 for success, 0 for failure. */ + +/* ??? The return code isn't properly used. wip. */ + +/* ??? This doesn't handle bfd_vma's. Create another function when + necessary. */ + +static int +extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, + word_length, total_length, pc, valuep) + CGEN_CPU_DESC cd; +#if ! CGEN_INT_INSN_P + CGEN_EXTRACT_INFO *ex_info; +#else + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; +#endif + CGEN_INSN_INT insn_value; + unsigned int attrs; + unsigned int word_offset, start, length, word_length, total_length; +#if ! CGEN_INT_INSN_P + bfd_vma pc; +#else + bfd_vma pc ATTRIBUTE_UNUSED; +#endif + long *valuep; +{ + long value, mask; + + /* If LENGTH is zero, this operand doesn't contribute to the value + so give it a standard value of zero. */ + if (length == 0) + { + *valuep = 0; + return 1; + } + +#if 0 + if (CGEN_INT_INSN_P + && word_offset != 0) + abort (); +#endif + + if (word_length > 32) + abort (); + + /* For architectures with insns smaller than the insn-base-bitsize, + word_length may be too big. */ + if (cd->min_insn_bitsize < cd->base_insn_bitsize) + { + if (word_offset == 0 + && word_length > total_length) + word_length = total_length; + } + + /* Does the value reside in INSN_VALUE, and at the right alignment? */ + + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) + { + if (CGEN_INSN_LSB0_P) + value = insn_value >> ((word_offset + start + 1) - length); + else + value = insn_value >> (total_length - ( word_offset + start + length)); + } + +#if ! CGEN_INT_INSN_P + + else + { + unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; + + if (word_length > 32) + abort (); + + if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) + return 0; + + value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); + } + +#endif /* ! CGEN_INT_INSN_P */ + + /* Written this way to avoid undefined behaviour. */ + mask = (((1L << (length - 1)) - 1) << 1) | 1; + + value &= mask; + /* sign extend? */ + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) + && (value & (1L << (length - 1)))) + value |= ~mask; + + *valuep = value; + + return 1; +} + +/* Default insn extractor. + + INSN_VALUE is the first base_insn_bitsize bits, translated to host order. + The extracted fields are stored in FIELDS. + EX_INFO is used to handle reading variable length insns. + Return the length of the insn in bits, or 0 if no match, + or -1 if an error occurs fetching data (memory_error_func will have + been called). */ + +static int +extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + const CGEN_INSN *insn; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS *fields; + bfd_vma pc; +{ + const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); + const CGEN_SYNTAX_CHAR_TYPE *syn; + + CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); + + CGEN_INIT_EXTRACT (cd); + + for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) + { + int length; + + if (CGEN_SYNTAX_CHAR_P (*syn)) + continue; + + length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), + ex_info, insn_value, fields, pc); + if (length <= 0) + return length; + } + + /* We recognized and successfully extracted this insn. */ + return CGEN_INSN_BITSIZE (insn); +} + +/* machine generated code added here */ + +const char * iq2000_cgen_insert_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + +/* Main entry point for operand insertion. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `parse_insn_normal', but keeping it + separate makes clear the interface between `parse_insn_normal' and each of + the handlers. It's also needed by GAS to insert operands that couldn't be + resolved during parsing. */ + +const char * +iq2000_cgen_insert_operand (cd, opindex, fields, buffer, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_FIELDS * fields; + CGEN_INSN_BYTES_PTR buffer; + bfd_vma pc ATTRIBUTE_UNUSED; +{ + const char * errmsg = NULL; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BASEOFF : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BITNUM : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_BYTECOUNT : + errmsg = insert_normal (cd, fields->f_bytecount, 0, 0, 7, 8, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Y : + errmsg = insert_normal (cd, fields->f_cam_y, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CAM_Z : + errmsg = insert_normal (cd, fields->f_cam_z, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3FUNC : + errmsg = insert_normal (cd, fields->f_cm_3func, 0, 0, 5, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_3Z : + errmsg = insert_normal (cd, fields->f_cm_3z, 0, 0, 1, 2, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4FUNC : + errmsg = insert_normal (cd, fields->f_cm_4func, 0, 0, 5, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_CM_4Z : + errmsg = insert_normal (cd, fields->f_cm_4z, 0, 0, 2, 3, 32, total_length, buffer); + break; + case IQ2000_OPERAND_COUNT : + errmsg = insert_normal (cd, fields->f_count, 0, 0, 15, 7, 32, total_length, buffer); + break; + case IQ2000_OPERAND_EXECODE : + errmsg = insert_normal (cd, fields->f_excode, 0, 0, 25, 20, 32, total_length, buffer); + break; + case IQ2000_OPERAND_HI16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_IMM : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_INDEX : + errmsg = insert_normal (cd, fields->f_index, 0, 0, 8, 9, 32, total_length, buffer); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value = fields->f_jtarg; + value = ((unsigned int) (((value) & (262143))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_jtargq10; + value = ((unsigned int) (((value) & (8388607))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASK : + errmsg = insert_normal (cd, fields->f_mask, 0, 0, 9, 4, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKL : + errmsg = insert_normal (cd, fields->f_maskl, 0, 0, 4, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKQ10 : + errmsg = insert_normal (cd, fields->f_maskq10, 0, 0, 10, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MASKR : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_MLO16 : + errmsg = insert_normal (cd, fields->f_imm, 0, 0, 15, 16, 32, total_length, buffer); + break; + case IQ2000_OPERAND_OFFSET : + { + long value = fields->f_offset; + value = ((int) (((value) - (pc))) >> (2)); + errmsg = insert_normal (cd, value, 0|(1<f_rd, 0, 0, 15, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RD_RS : + { +{ + FLD (f_rd) = FLD (f_rd_rs); + FLD (f_rs) = FLD (f_rd_rs); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RD_RT : + { +{ + FLD (f_rd) = FLD (f_rd_rt); + FLD (f_rt) = FLD (f_rd_rt); +} + errmsg = insert_normal (cd, fields->f_rd, 0, 0, 15, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_RS : + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT : + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + break; + case IQ2000_OPERAND_RT_RS : + { +{ + FLD (f_rt) = FLD (f_rt_rs); + FLD (f_rs) = FLD (f_rt_rs); +} + errmsg = insert_normal (cd, fields->f_rt, 0, 0, 20, 5, 32, total_length, buffer); + if (errmsg) + break; + errmsg = insert_normal (cd, fields->f_rs, 0, 0, 25, 5, 32, total_length, buffer); + if (errmsg) + break; + } + break; + case IQ2000_OPERAND_SHAMT : + errmsg = insert_normal (cd, fields->f_shamt, 0, 0, 10, 5, 32, total_length, buffer); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while building insn.\n"), + opindex); + abort (); + } + + return errmsg; +} + +int iq2000_cgen_extract_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *, bfd_vma)); + +/* Main entry point for operand extraction. + The result is <= 0 for error, >0 for success. + ??? Actual values aren't well defined right now. + + This function is basically just a big switch statement. Earlier versions + used tables to look up the function to use, but + - if the table contains both assembler and disassembler functions then + the disassembler contains much of the assembler and vice-versa, + - there's a lot of inlining possibilities as things grow, + - using a switch statement avoids the function call overhead. + + This function could be moved into `print_insn_normal', but keeping it + separate makes clear the interface between `print_insn_normal' and each of + the handlers. */ + +int +iq2000_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) + CGEN_CPU_DESC cd; + int opindex; + CGEN_EXTRACT_INFO *ex_info; + CGEN_INSN_INT insn_value; + CGEN_FIELDS * fields; + bfd_vma pc; +{ + /* Assume success (for those operands that are nops). */ + int length = 1; + unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_BASEOFF : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_BITNUM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_BYTECOUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 8, 32, total_length, pc, & fields->f_bytecount); + break; + case IQ2000_OPERAND_CAM_Y : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cam_y); + break; + case IQ2000_OPERAND_CAM_Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cam_z); + break; + case IQ2000_OPERAND_CM_3FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_cm_3func); + break; + case IQ2000_OPERAND_CM_3Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 1, 2, 32, total_length, pc, & fields->f_cm_3z); + break; + case IQ2000_OPERAND_CM_4FUNC : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 4, 32, total_length, pc, & fields->f_cm_4func); + break; + case IQ2000_OPERAND_CM_4Z : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 2, 3, 32, total_length, pc, & fields->f_cm_4z); + break; + case IQ2000_OPERAND_COUNT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 7, 32, total_length, pc, & fields->f_count); + break; + case IQ2000_OPERAND_EXECODE : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 20, 32, total_length, pc, & fields->f_excode); + break; + case IQ2000_OPERAND_HI16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_IMM : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_INDEX : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 9, 32, total_length, pc, & fields->f_index); + break; + case IQ2000_OPERAND_JMPTARG : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtarg = value; + } + break; + case IQ2000_OPERAND_JMPTARGQ10 : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_jtargq10 = value; + } + break; + case IQ2000_OPERAND_LO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_MASK : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 4, 32, total_length, pc, & fields->f_mask); + break; + case IQ2000_OPERAND_MASKL : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 5, 32, total_length, pc, & fields->f_maskl); + break; + case IQ2000_OPERAND_MASKQ10 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_maskq10); + break; + case IQ2000_OPERAND_MASKR : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_MLO16 : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_imm); + break; + case IQ2000_OPERAND_OFFSET : + { + long value; + length = extract_normal (cd, ex_info, insn_value, 0|(1<f_offset = value; + } + break; + case IQ2000_OPERAND_RD : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + break; + case IQ2000_OPERAND_RD_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_RD_RT : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_rd); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; +{ + FLD (f_rd_rt) = FLD (f_rt); +} + } + break; + case IQ2000_OPERAND_RS : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + break; + case IQ2000_OPERAND_RT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + break; + case IQ2000_OPERAND_RT_RS : + { + length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_rt); + if (length <= 0) break; + length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_rs); + if (length <= 0) break; +{ + FLD (f_rd_rs) = FLD (f_rs); +} + } + break; + case IQ2000_OPERAND_SHAMT : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 5, 32, total_length, pc, & fields->f_shamt); + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"), + opindex); + abort (); + } + + return length; +} + +cgen_insert_fn * const iq2000_cgen_insert_handlers[] = +{ + insert_insn_normal, +}; + +cgen_extract_fn * const iq2000_cgen_extract_handlers[] = +{ + extract_insn_normal, +}; + +int iq2000_cgen_get_int_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); +bfd_vma iq2000_cgen_get_vma_operand + PARAMS ((CGEN_CPU_DESC, int, const CGEN_FIELDS *)); + +/* Getting values from cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they return. + TODO: floating point, inlining support, remove cases where result type + not appropriate. */ + +int +iq2000_cgen_get_int_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + int value; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), + opindex); + abort (); + } + + return value; +} + +bfd_vma +iq2000_cgen_get_vma_operand (cd, opindex, fields) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + const CGEN_FIELDS * fields; +{ + bfd_vma value; + + switch (opindex) + { + case IQ2000_OPERAND_BASE : + value = fields->f_rs; + break; + case IQ2000_OPERAND_BASEOFF : + value = fields->f_imm; + break; + case IQ2000_OPERAND_BITNUM : + value = fields->f_rt; + break; + case IQ2000_OPERAND_BYTECOUNT : + value = fields->f_bytecount; + break; + case IQ2000_OPERAND_CAM_Y : + value = fields->f_cam_y; + break; + case IQ2000_OPERAND_CAM_Z : + value = fields->f_cam_z; + break; + case IQ2000_OPERAND_CM_3FUNC : + value = fields->f_cm_3func; + break; + case IQ2000_OPERAND_CM_3Z : + value = fields->f_cm_3z; + break; + case IQ2000_OPERAND_CM_4FUNC : + value = fields->f_cm_4func; + break; + case IQ2000_OPERAND_CM_4Z : + value = fields->f_cm_4z; + break; + case IQ2000_OPERAND_COUNT : + value = fields->f_count; + break; + case IQ2000_OPERAND_EXECODE : + value = fields->f_excode; + break; + case IQ2000_OPERAND_HI16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_IMM : + value = fields->f_imm; + break; + case IQ2000_OPERAND_INDEX : + value = fields->f_index; + break; + case IQ2000_OPERAND_JMPTARG : + value = fields->f_jtarg; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + value = fields->f_jtargq10; + break; + case IQ2000_OPERAND_LO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_MASK : + value = fields->f_mask; + break; + case IQ2000_OPERAND_MASKL : + value = fields->f_maskl; + break; + case IQ2000_OPERAND_MASKQ10 : + value = fields->f_maskq10; + break; + case IQ2000_OPERAND_MASKR : + value = fields->f_rs; + break; + case IQ2000_OPERAND_MLO16 : + value = fields->f_imm; + break; + case IQ2000_OPERAND_OFFSET : + value = fields->f_offset; + break; + case IQ2000_OPERAND_RD : + value = fields->f_rd; + break; + case IQ2000_OPERAND_RD_RS : + value = fields->f_rd_rs; + break; + case IQ2000_OPERAND_RD_RT : + value = fields->f_rd_rt; + break; + case IQ2000_OPERAND_RS : + value = fields->f_rs; + break; + case IQ2000_OPERAND_RT : + value = fields->f_rt; + break; + case IQ2000_OPERAND_RT_RS : + value = fields->f_rt_rs; + break; + case IQ2000_OPERAND_SHAMT : + value = fields->f_shamt; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), + opindex); + abort (); + } + + return value; +} + +void iq2000_cgen_set_int_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, int)); +void iq2000_cgen_set_vma_operand + PARAMS ((CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma)); + +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +iq2000_cgen_set_int_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +iq2000_cgen_set_vma_operand (cd, opindex, fields, value) + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case IQ2000_OPERAND_BASE : + fields->f_rs = value; + break; + case IQ2000_OPERAND_BASEOFF : + fields->f_imm = value; + break; + case IQ2000_OPERAND_BITNUM : + fields->f_rt = value; + break; + case IQ2000_OPERAND_BYTECOUNT : + fields->f_bytecount = value; + break; + case IQ2000_OPERAND_CAM_Y : + fields->f_cam_y = value; + break; + case IQ2000_OPERAND_CAM_Z : + fields->f_cam_z = value; + break; + case IQ2000_OPERAND_CM_3FUNC : + fields->f_cm_3func = value; + break; + case IQ2000_OPERAND_CM_3Z : + fields->f_cm_3z = value; + break; + case IQ2000_OPERAND_CM_4FUNC : + fields->f_cm_4func = value; + break; + case IQ2000_OPERAND_CM_4Z : + fields->f_cm_4z = value; + break; + case IQ2000_OPERAND_COUNT : + fields->f_count = value; + break; + case IQ2000_OPERAND_EXECODE : + fields->f_excode = value; + break; + case IQ2000_OPERAND_HI16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_IMM : + fields->f_imm = value; + break; + case IQ2000_OPERAND_INDEX : + fields->f_index = value; + break; + case IQ2000_OPERAND_JMPTARG : + fields->f_jtarg = value; + break; + case IQ2000_OPERAND_JMPTARGQ10 : + fields->f_jtargq10 = value; + break; + case IQ2000_OPERAND_LO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_MASK : + fields->f_mask = value; + break; + case IQ2000_OPERAND_MASKL : + fields->f_maskl = value; + break; + case IQ2000_OPERAND_MASKQ10 : + fields->f_maskq10 = value; + break; + case IQ2000_OPERAND_MASKR : + fields->f_rs = value; + break; + case IQ2000_OPERAND_MLO16 : + fields->f_imm = value; + break; + case IQ2000_OPERAND_OFFSET : + fields->f_offset = value; + break; + case IQ2000_OPERAND_RD : + fields->f_rd = value; + break; + case IQ2000_OPERAND_RD_RS : + fields->f_rd_rs = value; + break; + case IQ2000_OPERAND_RD_RT : + fields->f_rd_rt = value; + break; + case IQ2000_OPERAND_RS : + fields->f_rs = value; + break; + case IQ2000_OPERAND_RT : + fields->f_rt = value; + break; + case IQ2000_OPERAND_RT_RS : + fields->f_rt_rs = value; + break; + case IQ2000_OPERAND_SHAMT : + fields->f_shamt = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + +/* Function to call before using the instruction builder tables. */ + +void +iq2000_cgen_init_ibld_table (cd) + CGEN_CPU_DESC cd; +{ + cd->insert_handlers = & iq2000_cgen_insert_handlers[0]; + cd->extract_handlers = & iq2000_cgen_extract_handlers[0]; + + cd->insert_operand = iq2000_cgen_insert_operand; + cd->extract_operand = iq2000_cgen_extract_operand; + + cd->get_int_operand = iq2000_cgen_get_int_operand; + cd->set_int_operand = iq2000_cgen_set_int_operand; + cd->get_vma_operand = iq2000_cgen_get_vma_operand; + cd->set_vma_operand = iq2000_cgen_set_vma_operand; +} diff --git a/opcodes/iq2000-opc.c b/opcodes/iq2000-opc.c new file mode 100644 index 0000000000..fe8cf64150 --- /dev/null +++ b/opcodes/iq2000-opc.c @@ -0,0 +1,3482 @@ +/* Instruction opcode table for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#include "sysdep.h" +#include "ansidecl.h" +#include "bfd.h" +#include "symcat.h" +#include "iq2000-desc.h" +#include "iq2000-opc.h" +#include "libiberty.h" + +/* The hash functions are recorded here to help keep assembler code out of + the disassembler and vice versa. */ + +static int asm_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int asm_hash_insn PARAMS ((const char *)); +static int dis_hash_insn_p PARAMS ((const CGEN_INSN *)); +static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT)); + +/* Instruction formats. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +#else +#define F(f) & iq2000_cgen_ifld_table[IQ2000_/**/f] +#endif +static const CGEN_IFMT ifmt_empty = { + 0, 0, 0x0, { { 0 } } +}; + +static const CGEN_IFMT ifmt_add2 = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_add = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_addi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ram = { + 32, 32, 0xfc000020, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_5) }, { F (F_MASKL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sll = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sllv2 = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv2 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slmv = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_slti = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sra2 = { + 32, 32, 0xffe0003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RD_RT) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bbv = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bgez = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalr = { + 32, 32, 0xfc1f07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jr = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lui = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_break = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_syscall = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_EXCODE) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_andoui2 = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RT_RS) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgb2 = { + 32, 32, 0xfc00043f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_10) }, { F (F_MASK) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_bc0f = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_OFFSET) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cfc0 = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_10_11) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_chkhdr = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lulck = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_pkrlr1 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_COUNT) }, { F (F_INDEX) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rfe = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_25) }, { F (F_24_19) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_j = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RSRVD) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq10 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mrgbq102 = { + 32, 32, 0xfc00003f, { { F (F_OPCODE) }, { F (F_RT) }, { F (F_RD_RS) }, { F (F_MASKQ10) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jq10 = { + 32, 32, 0xffff0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_jalq10 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_JTARG) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_avail = { + 32, 32, 0xffff07ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_rbi = { + 32, 32, 0xfc000700, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cam36 = { + 32, 32, 0xffe007c0, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32and = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm32rd = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria3 = { + 32, 32, 0xfc0007fc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cm128ria4 = { + 32, 32, 0xfc0007f8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ctc = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +#undef F + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IQ2000_OPERAND_##op +#else +#define OPERAND(op) IQ2000_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The instruction table. */ + +static const CGEN_OPCODE iq2000_cgen_insn_opcode_table[MAX_INSNS] = +{ + /* Special null first entry. + A `num' value of zero is thus invalid. + Also, the special `invalid' insn resides here. */ + { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, +/* add ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x20 } + }, +/* add $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x20 } + }, +/* addi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x20000000 } + }, +/* addi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x20000000 } + }, +/* addiu ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x24000000 } + }, +/* addiu $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x24000000 } + }, +/* addu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x21 } + }, +/* addu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x21 } + }, +/* ado16 ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x29 } + }, +/* ado16 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x29 } + }, +/* and ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x24 } + }, +/* and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x24 } + }, +/* andi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x30000000 } + }, +/* andi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x30000000 } + }, +/* andoi ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0xb0000000 } + }, +/* andoi $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0xb0000000 } + }, +/* nor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x27 } + }, +/* nor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x27 } + }, +/* or ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x25 } + }, +/* or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x25 } + }, +/* ori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x34000000 } + }, +/* ori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x34000000 } + }, +/* ram $rd,$rt,$shamt,$maskl,$maskr */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), ',', OP (MASKL), ',', OP (MASKR), 0 } }, + & ifmt_ram, { 0x9c000000 } + }, +/* sll $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x0 } + }, +/* sllv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x4 } + }, +/* sllv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x4 } + }, +/* slmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x1 } + }, +/* slmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x1 } + }, +/* slt ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2a } + }, +/* slt $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2a } + }, +/* slti ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x28000000 } + }, +/* slti $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x28000000 } + }, +/* sltiu ${rt-rs},$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (IMM), 0 } }, + & ifmt_slti2, { 0x2c000000 } + }, +/* sltiu $rt,$rs,$imm */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (IMM), 0 } }, + & ifmt_slti, { 0x2c000000 } + }, +/* sltu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x2b } + }, +/* sltu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x2b } + }, +/* sra ${rd-rt},$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (SHAMT), 0 } }, + & ifmt_sra2, { 0x3 } + }, +/* sra $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x3 } + }, +/* srav ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x7 } + }, +/* srav $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x7 } + }, +/* srl $rd,$rt,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (SHAMT), 0 } }, + & ifmt_sll, { 0x2 } + }, +/* srlv ${rd-rt},$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), 0 } }, + & ifmt_sllv2, { 0x6 } + }, +/* srlv $rd,$rt,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), 0 } }, + & ifmt_add, { 0x6 } + }, +/* srmv ${rd-rt},$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv2, { 0x5 } + }, +/* srmv $rd,$rt,$rs,$shamt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (RS), ',', OP (SHAMT), 0 } }, + & ifmt_slmv, { 0x5 } + }, +/* sub ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x22 } + }, +/* sub $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x22 } + }, +/* subu ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x23 } + }, +/* subu $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x23 } + }, +/* xor ${rd-rs},$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), 0 } }, + & ifmt_add2, { 0x26 } + }, +/* xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x26 } + }, +/* xori ${rt-rs},$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (LO16), 0 } }, + & ifmt_addi2, { 0x38000000 } + }, +/* xori $rt,$rs,$lo16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } }, + & ifmt_addi, { 0x38000000 } + }, +/* bbi $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x70000000 } + }, +/* bbin $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0x78000000 } + }, +/* bbv $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x74000000 } + }, +/* bbvn $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x7c000000 } + }, +/* beq $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x10000000 } + }, +/* beql $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x50000000 } + }, +/* bgez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4010000 } + }, +/* bgezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4110000 } + }, +/* bgezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4130000 } + }, +/* bgezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4030000 } + }, +/* bltz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4000000 } + }, +/* bltzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4020000 } + }, +/* bltzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4100000 } + }, +/* bltzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4120000 } + }, +/* bmb0 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x60000000 } + }, +/* bmb1 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x64000000 } + }, +/* bmb2 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x68000000 } + }, +/* bmb3 $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x6c000000 } + }, +/* bne $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x14000000 } + }, +/* bnel $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x54000000 } + }, +/* jalr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x9 } + }, +/* jr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0x8 } + }, +/* lb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x80000000 } + }, +/* lbu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x90000000 } + }, +/* lh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x84000000 } + }, +/* lhu $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x94000000 } + }, +/* lui $rt,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (HI16), 0 } }, + & ifmt_lui, { 0x3c000000 } + }, +/* lw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0x8c000000 } + }, +/* sb $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa0000000 } + }, +/* sh $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xa4000000 } + }, +/* sw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xac000000 } + }, +/* break */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xd } + }, +/* syscall */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xc } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xfc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xfc000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x1c000000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x5c000000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x18000000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x58000000 } + }, +/* mrgb $rd,$rs,$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$mask */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASK), 0 } }, + & ifmt_mrgb2, { 0x2d } + }, +/* bctxt $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bc0f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41000000 } + }, +/* bc0fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41020000 } + }, +/* bc3f $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d000000 } + }, +/* bc3fl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d020000 } + }, +/* bc0t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41010000 } + }, +/* bc0tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x41030000 } + }, +/* bc3t $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d010000 } + }, +/* bc3tl $offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (OFFSET), 0 } }, + & ifmt_bc0f, { 0x4d030000 } + }, +/* cfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40400000 } + }, +/* cfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44400000 } + }, +/* cfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48400000 } + }, +/* cfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c400000 } + }, +/* chkhdr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4d200000 } + }, +/* ctc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40c00000 } + }, +/* ctc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44c00000 } + }, +/* ctc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48c00000 } + }, +/* ctc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4cc00000 } + }, +/* jcr $rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), 0 } }, + & ifmt_jr, { 0xa } + }, +/* luc32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200003 } + }, +/* luc32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200007 } + }, +/* luc64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000b } + }, +/* luc64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000f } + }, +/* luk $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200008 } + }, +/* lulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200004 } + }, +/* lum32 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200002 } + }, +/* lum32l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200006 } + }, +/* lum64 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000a } + }, +/* lum64l $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x4820000e } + }, +/* lur $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200001 } + }, +/* lurl $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200005 } + }, +/* luulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200000 } + }, +/* mfc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40000000 } + }, +/* mfc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44000000 } + }, +/* mfc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48000000 } + }, +/* mfc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c000000 } + }, +/* mtc0 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x40800000 } + }, +/* mtc1 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x44800000 } + }, +/* mtc2 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x48800000 } + }, +/* mtc3 $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_cfc0, { 0x4c800000 } + }, +/* pkrl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200007 } + }, +/* pkrlr1 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fa00000 } + }, +/* pkrlr30 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fe00000 } + }, +/* rb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200004 } + }, +/* rbr1 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f000000 } + }, +/* rbr30 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f400000 } + }, +/* rfe */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_rfe, { 0x42000010 } + }, +/* rx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200006 } + }, +/* rxr1 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4f800000 } + }, +/* rxr30 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4fc00000 } + }, +/* sleep */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_syscall, { 0xe } + }, +/* srrd $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200010 } + }, +/* srrdl $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200014 } + }, +/* srulck $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x48200016 } + }, +/* srwr $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200011 } + }, +/* srwru $rt,$rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RD), 0 } }, + & ifmt_chkhdr, { 0x48200015 } + }, +/* trapqfl */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200008 } + }, +/* trapqne */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0x4c200009 } + }, +/* traprel $rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), 0 } }, + & ifmt_lulck, { 0x4c20000a } + }, +/* wb $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200000 } + }, +/* wbu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200001 } + }, +/* wbr1 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e000000 } + }, +/* wbr1u $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e200000 } + }, +/* wbr30 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e400000 } + }, +/* wbr30u $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e600000 } + }, +/* wx $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200002 } + }, +/* wxu $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c200003 } + }, +/* wxr1 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4e800000 } + }, +/* wxr1u $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ea00000 } + }, +/* wxr30 $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ec00000 } + }, +/* wxr30u $rt,$index,$count */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (INDEX), ',', OP (COUNT), 0 } }, + & ifmt_pkrlr1, { 0x4ee00000 } + }, +/* ldw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xc0000000 } + }, +/* sdw $rt,$lo16($base) */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (LO16), '(', OP (BASE), ')', 0 } }, + & ifmt_lb, { 0xe0000000 } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0x8000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_j, { 0xc000000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xb4000000 } + }, +/* andoui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0xbc000000 } + }, +/* andoui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0xbc000000 } + }, +/* orui $rt,$rs,$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (HI16), 0 } }, + & ifmt_andoui, { 0x3c000000 } + }, +/* orui ${rt-rs},$hi16 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT_RS), ',', OP (HI16), 0 } }, + & ifmt_andoui2, { 0x3c000000 } + }, +/* mrgb $rd,$rs,$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq10, { 0x2d } + }, +/* mrgb ${rd-rs},$rt,$maskq10 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD_RS), ',', OP (RT), ',', OP (MASKQ10), 0 } }, + & ifmt_mrgbq102, { 0x2d } + }, +/* j $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0x8000000 } + }, +/* jal $rt,$jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RT), ',', OP (JMPTARG), 0 } }, + & ifmt_jalq10, { 0xc000000 } + }, +/* jal $jmptarg */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (JMPTARG), 0 } }, + & ifmt_jq10, { 0xc1f0000 } + }, +/* bbil $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf0000000 } + }, +/* bbinl $rs($bitnum),$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), '(', OP (BITNUM), ')', ',', OP (OFFSET), 0 } }, + & ifmt_bbi, { 0xf8000000 } + }, +/* bbvl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xf4000000 } + }, +/* bbvnl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0xfc000000 } + }, +/* bgtzal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4150000 } + }, +/* bgtzall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4170000 } + }, +/* blezal $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4140000 } + }, +/* blezall $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4160000 } + }, +/* bgtz $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4050000 } + }, +/* bgtzl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4070000 } + }, +/* blez $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4040000 } + }, +/* blezl $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4060000 } + }, +/* bmb $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x18000000 } + }, +/* bmbl $rs,$rt,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), ',', OP (OFFSET), 0 } }, + & ifmt_bbv, { 0x58000000 } + }, +/* bri $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4080000 } + }, +/* brv $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x4090000 } + }, +/* bctx $rs,$offset */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (OFFSET), 0 } }, + & ifmt_bgez, { 0x40c0000 } + }, +/* yield */ + { + { 0, 0, 0, 0 }, + { { MNEM, 0 } }, + & ifmt_break, { 0xe } + }, +/* crc32 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000014 } + }, +/* crc32b $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000015 } + }, +/* cnt1s $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_add, { 0x2e } + }, +/* avail $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000024 } + }, +/* free $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000025 } + }, +/* tstod $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000027 } + }, +/* cmphdr $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c00002c } + }, +/* mcid $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000020 } + }, +/* dba $rd */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), 0 } }, + & ifmt_avail, { 0x4c000022 } + }, +/* dbd $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000021 } + }, +/* dpwt $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000023 } + }, +/* chkhdr $rd,$rs */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), 0 } }, + & ifmt_jalr, { 0x4c000026 } + }, +/* rba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000008 } + }, +/* rbal $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000009 } + }, +/* rbar $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00000a } + }, +/* wba $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000010 } + }, +/* wbau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000011 } + }, +/* wbac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000012 } + }, +/* rbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000200 } + }, +/* rbil $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000300 } + }, +/* rbir $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000100 } + }, +/* wbi $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000600 } + }, +/* wbic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000500 } + }, +/* wbiu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x4c000700 } + }, +/* pkrli $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000000 } + }, +/* pkrlih $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000200 } + }, +/* pkrliu $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000100 } + }, +/* pkrlic $rd,$rs,$rt,$bytecount */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (BYTECOUNT), 0 } }, + & ifmt_rbi, { 0x48000300 } + }, +/* pkrla $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000028 } + }, +/* pkrlau $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000029 } + }, +/* pkrlah $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002a } + }, +/* pkrlac $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c00002b } + }, +/* lock $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000001 } + }, +/* unlk $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000003 } + }, +/* swrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000004 } + }, +/* swrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000005 } + }, +/* swwr $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000006 } + }, +/* swwru $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c000007 } + }, +/* dwrd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000c } + }, +/* dwrdl $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c00000d } + }, +/* cam36 $rd,$rt,${cam-z},${cam-y} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Z), ',', OP (CAM_Y), 0 } }, + & ifmt_cam36, { 0x4c000400 } + }, +/* cam72 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000440 } + }, +/* cam144 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c000480 } + }, +/* cam288 $rd,$rt,${cam-y},${cam-z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), ',', OP (CAM_Y), ',', OP (CAM_Z), 0 } }, + & ifmt_cam36, { 0x4c0004c0 } + }, +/* cm32and $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000ab } + }, +/* cm32andn $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a3 } + }, +/* cm32or $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000aa } + }, +/* cm32ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000b0 } + }, +/* cm32rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a1 } + }, +/* cm32ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a4 } + }, +/* cm32rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_add, { 0x4c0000a0 } + }, +/* cm32sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000b8 } + }, +/* cm32sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000a9 } + }, +/* cm32si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c0000ac } + }, +/* cm32ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a8 } + }, +/* cm32xor $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a2 } + }, +/* cm64clr $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000085 } + }, +/* cm64ra $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000090 } + }, +/* cm64rd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000081 } + }, +/* cm64ri $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000084 } + }, +/* cm64ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000094 } + }, +/* cm64rs $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000080 } + }, +/* cm64sa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000098 } + }, +/* cm64sd $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c000089 } + }, +/* cm64si $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_cm32rd, { 0x4c00008c } + }, +/* cm64sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009c } + }, +/* cm64ss $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000088 } + }, +/* cm128ria2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c000095 } + }, +/* cm128ria3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000090 } + }, +/* cm128ria4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b0 } + }, +/* cm128sia2 $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c00009d } + }, +/* cm128sia3 $rd,$rs,$rt,${cm-3z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_3Z), 0 } }, + & ifmt_cm128ria3, { 0x4c000098 } + }, +/* cm128sia4 $rd,$rs,$rt,${cm-4z} */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), ',', OP (CM_4Z), 0 } }, + & ifmt_cm128ria4, { 0x4c0000b8 } + }, +/* cm128vsa $rd,$rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } }, + & ifmt_cm32and, { 0x4c0000a6 } + }, +/* cfc $rd,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RD), ',', OP (RT), 0 } }, + & ifmt_chkhdr, { 0x4c000000 } + }, +/* ctc $rs,$rt */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RS), ',', OP (RT), 0 } }, + & ifmt_ctc, { 0x4c000002 } + }, +}; + +#undef A +#undef OPERAND +#undef MNEM +#undef OP + +/* Formats for ALIAS macro-insns. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define F(f) & iq2000_cgen_ifld_table[IQ2000_##f] +#else +#define F(f) & iq2000_cgen_ifld_table[IQ2000_/**/f] +#endif +static const CGEN_IFMT ifmt_nop = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_li = { + 32, 32, 0xfc1f0000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_move = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lb_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lbu_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lh_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_lw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_add = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_addu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_and = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_j = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_or = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sll = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_slt = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sltu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sra = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_srl = { + 32, 32, 0xfc0007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_not = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_subi = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_sub = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_subu = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sb_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sh_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_xor = { + 32, 32, 0xfc000000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_ldw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_sdw_base_0 = { + 32, 32, 0xffe00000, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_IMM) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_avail = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam36 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam72 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam144 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cam288 = { + 32, 32, 0xffe007c7, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP_10) }, { F (F_CAM_Z) }, { F (F_CAM_Y) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32read = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64read = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32mlog = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32and = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32andn = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32or = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ra = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ri = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32rs = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sa = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32sd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32si = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32ss = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm32xor = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64clr = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ra = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ri = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ria2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64rs = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sa = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64si = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64sia2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm64ss = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria3 = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128ria4 = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia2 = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia3 = { + 32, 32, 0xfc00fffc, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_4FUNC) }, { F (F_CM_3Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cm128sia4 = { + 32, 32, 0xfc00fff8, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_CP_GRP) }, { F (F_CM_3FUNC) }, { F (F_CM_4Z) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_cmphdr = { + 32, 32, 0xffffffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dbd = { + 32, 32, 0xffe007ff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m2_dbd = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_dpwt = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_free = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_lock = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrla = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlac = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlah = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlau = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrli = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlic = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrlih = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_pkrliu = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rba = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbal = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbar = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbi = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbil = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_rbir = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwr = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_swwru = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_tstod = { + 32, 32, 0xfc1fffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_unlk = { + 32, 32, 0xffe0ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wba = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbac = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbau = { + 32, 32, 0xfc00ffff, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_SHAMT) }, { F (F_FUNC) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbi = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbic = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_m_wbiu = { + 32, 32, 0xfc00ff00, { { F (F_OPCODE) }, { F (F_RS) }, { F (F_RT) }, { F (F_RD) }, { F (F_CP_OP) }, { F (F_BYTECOUNT) }, { 0 } } +}; + +#undef F + +/* Each non-simple macro entry points to an array of expansion possibilities. */ + +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define A(a) (1 << CGEN_INSN_##a) +#else +#define A(a) (1 << CGEN_INSN_/**/a) +#endif +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#define OPERAND(op) IQ2000_OPERAND_##op +#else +#define OPERAND(op) IQ2000_OPERAND_/**/op +#endif +#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ +#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) + +/* The macro instruction table. */ + +static const CGEN_IBASE iq2000_cgen_macro_insn_table[] = +{ +/* nop */ + { + -1, "nop", "nop", 32, + { 0|A(ALIAS), { (1<macro_insn_table.init_entries = insns; + cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); + cd->macro_insn_table.num_init_entries = num_macros; + + oc = & iq2000_cgen_insn_opcode_table[0]; + insns = (CGEN_INSN *) cd->insn_table.init_entries; + for (i = 0; i < MAX_INSNS; ++i) + { + insns[i].opcode = &oc[i]; + iq2000_cgen_build_insn_regex (& insns[i]); + } + + cd->sizeof_fields = sizeof (CGEN_FIELDS); + cd->set_fields_bitsize = set_fields_bitsize; + + cd->asm_hash_p = asm_hash_insn_p; + cd->asm_hash = asm_hash_insn; + cd->asm_hash_size = CGEN_ASM_HASH_SIZE; + + cd->dis_hash_p = dis_hash_insn_p; + cd->dis_hash = dis_hash_insn; + cd->dis_hash_size = CGEN_DIS_HASH_SIZE; +} diff --git a/opcodes/iq2000-opc.h b/opcodes/iq2000-opc.h new file mode 100644 index 0000000000..4dca525ffe --- /dev/null +++ b/opcodes/iq2000-opc.h @@ -0,0 +1,181 @@ +/* Instruction opcode header for iq2000. + +THIS FILE IS MACHINE GENERATED WITH CGEN. + +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + +This file is part of the GNU Binutils and/or GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +*/ + +#ifndef IQ2000_OPC_H +#define IQ2000_OPC_H + +/* -- opc.h */ + +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + +/* Override disassembly hashing - there are variable bits in the top + byte of these instructions. */ +#define CGEN_DIS_HASH_SIZE 8 +#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) + +/* following activates check beyond hashing since some iq2000 and iq10 + instructions have same mnemonics but different functionality. */ +#define CGEN_VALIDATE_INSN_SUPPORTED + +extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, CGEN_INSN *insn); + +/* -- asm.c */ +/* Enum declaration for iq2000 instruction types. */ +typedef enum cgen_insn_type { + IQ2000_INSN_INVALID, IQ2000_INSN_ADD2, IQ2000_INSN_ADD, IQ2000_INSN_ADDI2 + , IQ2000_INSN_ADDI, IQ2000_INSN_ADDIU2, IQ2000_INSN_ADDIU, IQ2000_INSN_ADDU2 + , IQ2000_INSN_ADDU, IQ2000_INSN_ADO162, IQ2000_INSN_ADO16, IQ2000_INSN_AND2 + , IQ2000_INSN_AND, IQ2000_INSN_ANDI2, IQ2000_INSN_ANDI, IQ2000_INSN_ANDOI2 + , IQ2000_INSN_ANDOI, IQ2000_INSN_NOR2, IQ2000_INSN_NOR, IQ2000_INSN_OR2 + , IQ2000_INSN_OR, IQ2000_INSN_ORI2, IQ2000_INSN_ORI, IQ2000_INSN_RAM + , IQ2000_INSN_SLL, IQ2000_INSN_SLLV2, IQ2000_INSN_SLLV, IQ2000_INSN_SLMV2 + , IQ2000_INSN_SLMV, IQ2000_INSN_SLT2, IQ2000_INSN_SLT, IQ2000_INSN_SLTI2 + , IQ2000_INSN_SLTI, IQ2000_INSN_SLTIU2, IQ2000_INSN_SLTIU, IQ2000_INSN_SLTU2 + , IQ2000_INSN_SLTU, IQ2000_INSN_SRA2, IQ2000_INSN_SRA, IQ2000_INSN_SRAV2 + , IQ2000_INSN_SRAV, IQ2000_INSN_SRL, IQ2000_INSN_SRLV2, IQ2000_INSN_SRLV + , IQ2000_INSN_SRMV2, IQ2000_INSN_SRMV, IQ2000_INSN_SUB2, IQ2000_INSN_SUB + , IQ2000_INSN_SUBU2, IQ2000_INSN_SUBU, IQ2000_INSN_XOR2, IQ2000_INSN_XOR + , IQ2000_INSN_XORI2, IQ2000_INSN_XORI, IQ2000_INSN_BBI, IQ2000_INSN_BBIN + , IQ2000_INSN_BBV, IQ2000_INSN_BBVN, IQ2000_INSN_BEQ, IQ2000_INSN_BEQL + , IQ2000_INSN_BGEZ, IQ2000_INSN_BGEZAL, IQ2000_INSN_BGEZALL, IQ2000_INSN_BGEZL + , IQ2000_INSN_BLTZ, IQ2000_INSN_BLTZL, IQ2000_INSN_BLTZAL, IQ2000_INSN_BLTZALL + , IQ2000_INSN_BMB0, IQ2000_INSN_BMB1, IQ2000_INSN_BMB2, IQ2000_INSN_BMB3 + , IQ2000_INSN_BNE, IQ2000_INSN_BNEL, IQ2000_INSN_JALR, IQ2000_INSN_JR + , IQ2000_INSN_LB, IQ2000_INSN_LBU, IQ2000_INSN_LH, IQ2000_INSN_LHU + , IQ2000_INSN_LUI, IQ2000_INSN_LW, IQ2000_INSN_SB, IQ2000_INSN_SH + , IQ2000_INSN_SW, IQ2000_INSN_BREAK, IQ2000_INSN_SYSCALL, IQ2000_INSN_ANDOUI + , IQ2000_INSN_ANDOUI2, IQ2000_INSN_ORUI2, IQ2000_INSN_ORUI, IQ2000_INSN_BGTZ + , IQ2000_INSN_BGTZL, IQ2000_INSN_BLEZ, IQ2000_INSN_BLEZL, IQ2000_INSN_MRGB + , IQ2000_INSN_MRGB2, IQ2000_INSN_BCTXT, IQ2000_INSN_BC0F, IQ2000_INSN_BC0FL + , IQ2000_INSN_BC3F, IQ2000_INSN_BC3FL, IQ2000_INSN_BC0T, IQ2000_INSN_BC0TL + , IQ2000_INSN_BC3T, IQ2000_INSN_BC3TL, IQ2000_INSN_CFC0, IQ2000_INSN_CFC1 + , IQ2000_INSN_CFC2, IQ2000_INSN_CFC3, IQ2000_INSN_CHKHDR, IQ2000_INSN_CTC0 + , IQ2000_INSN_CTC1, IQ2000_INSN_CTC2, IQ2000_INSN_CTC3, IQ2000_INSN_JCR + , IQ2000_INSN_LUC32, IQ2000_INSN_LUC32L, IQ2000_INSN_LUC64, IQ2000_INSN_LUC64L + , IQ2000_INSN_LUK, IQ2000_INSN_LULCK, IQ2000_INSN_LUM32, IQ2000_INSN_LUM32L + , IQ2000_INSN_LUM64, IQ2000_INSN_LUM64L, IQ2000_INSN_LUR, IQ2000_INSN_LURL + , IQ2000_INSN_LUULCK, IQ2000_INSN_MFC0, IQ2000_INSN_MFC1, IQ2000_INSN_MFC2 + , IQ2000_INSN_MFC3, IQ2000_INSN_MTC0, IQ2000_INSN_MTC1, IQ2000_INSN_MTC2 + , IQ2000_INSN_MTC3, IQ2000_INSN_PKRL, IQ2000_INSN_PKRLR1, IQ2000_INSN_PKRLR30 + , IQ2000_INSN_RB, IQ2000_INSN_RBR1, IQ2000_INSN_RBR30, IQ2000_INSN_RFE + , IQ2000_INSN_RX, IQ2000_INSN_RXR1, IQ2000_INSN_RXR30, IQ2000_INSN_SLEEP + , IQ2000_INSN_SRRD, IQ2000_INSN_SRRDL, IQ2000_INSN_SRULCK, IQ2000_INSN_SRWR + , IQ2000_INSN_SRWRU, IQ2000_INSN_TRAPQFL, IQ2000_INSN_TRAPQNE, IQ2000_INSN_TRAPREL + , IQ2000_INSN_WB, IQ2000_INSN_WBU, IQ2000_INSN_WBR1, IQ2000_INSN_WBR1U + , IQ2000_INSN_WBR30, IQ2000_INSN_WBR30U, IQ2000_INSN_WX, IQ2000_INSN_WXU + , IQ2000_INSN_WXR1, IQ2000_INSN_WXR1U, IQ2000_INSN_WXR30, IQ2000_INSN_WXR30U + , IQ2000_INSN_LDW, IQ2000_INSN_SDW, IQ2000_INSN_J, IQ2000_INSN_JAL + , IQ2000_INSN_BMB, IQ2000_INSN_ANDOUI_Q10, IQ2000_INSN_ANDOUI2_Q10, IQ2000_INSN_ORUI_Q10 + , IQ2000_INSN_ORUI2_Q10, IQ2000_INSN_MRGBQ10, IQ2000_INSN_MRGBQ102, IQ2000_INSN_JQ10 + , IQ2000_INSN_JALQ10, IQ2000_INSN_JALQ10_2, IQ2000_INSN_BBIL, IQ2000_INSN_BBINL + , IQ2000_INSN_BBVL, IQ2000_INSN_BBVNL, IQ2000_INSN_BGTZAL, IQ2000_INSN_BGTZALL + , IQ2000_INSN_BLEZAL, IQ2000_INSN_BLEZALL, IQ2000_INSN_BGTZ_Q10, IQ2000_INSN_BGTZL_Q10 + , IQ2000_INSN_BLEZ_Q10, IQ2000_INSN_BLEZL_Q10, IQ2000_INSN_BMB_Q10, IQ2000_INSN_BMBL + , IQ2000_INSN_BRI, IQ2000_INSN_BRV, IQ2000_INSN_BCTX, IQ2000_INSN_YIELD + , IQ2000_INSN_CRC32, IQ2000_INSN_CRC32B, IQ2000_INSN_CNT1S, IQ2000_INSN_AVAIL + , IQ2000_INSN_FREE, IQ2000_INSN_TSTOD, IQ2000_INSN_CMPHDR, IQ2000_INSN_MCID + , IQ2000_INSN_DBA, IQ2000_INSN_DBD, IQ2000_INSN_DPWT, IQ2000_INSN_CHKHDRQ10 + , IQ2000_INSN_RBA, IQ2000_INSN_RBAL, IQ2000_INSN_RBAR, IQ2000_INSN_WBA + , IQ2000_INSN_WBAU, IQ2000_INSN_WBAC, IQ2000_INSN_RBI, IQ2000_INSN_RBIL + , IQ2000_INSN_RBIR, IQ2000_INSN_WBI, IQ2000_INSN_WBIC, IQ2000_INSN_WBIU + , IQ2000_INSN_PKRLI, IQ2000_INSN_PKRLIH, IQ2000_INSN_PKRLIU, IQ2000_INSN_PKRLIC + , IQ2000_INSN_PKRLA, IQ2000_INSN_PKRLAU, IQ2000_INSN_PKRLAH, IQ2000_INSN_PKRLAC + , IQ2000_INSN_LOCK, IQ2000_INSN_UNLK, IQ2000_INSN_SWRD, IQ2000_INSN_SWRDL + , IQ2000_INSN_SWWR, IQ2000_INSN_SWWRU, IQ2000_INSN_DWRD, IQ2000_INSN_DWRDL + , IQ2000_INSN_CAM36, IQ2000_INSN_CAM72, IQ2000_INSN_CAM144, IQ2000_INSN_CAM288 + , IQ2000_INSN_CM32AND, IQ2000_INSN_CM32ANDN, IQ2000_INSN_CM32OR, IQ2000_INSN_CM32RA + , IQ2000_INSN_CM32RD, IQ2000_INSN_CM32RI, IQ2000_INSN_CM32RS, IQ2000_INSN_CM32SA + , IQ2000_INSN_CM32SD, IQ2000_INSN_CM32SI, IQ2000_INSN_CM32SS, IQ2000_INSN_CM32XOR + , IQ2000_INSN_CM64CLR, IQ2000_INSN_CM64RA, IQ2000_INSN_CM64RD, IQ2000_INSN_CM64RI + , IQ2000_INSN_CM64RIA2, IQ2000_INSN_CM64RS, IQ2000_INSN_CM64SA, IQ2000_INSN_CM64SD + , IQ2000_INSN_CM64SI, IQ2000_INSN_CM64SIA2, IQ2000_INSN_CM64SS, IQ2000_INSN_CM128RIA2 + , IQ2000_INSN_CM128RIA3, IQ2000_INSN_CM128RIA4, IQ2000_INSN_CM128SIA2, IQ2000_INSN_CM128SIA3 + , IQ2000_INSN_CM128SIA4, IQ2000_INSN_CM128VSA, IQ2000_INSN_CFC, IQ2000_INSN_CTC +} CGEN_INSN_TYPE; + +/* Index of `invalid' insn place holder. */ +#define CGEN_INSN_INVALID IQ2000_INSN_INVALID + +/* Total number of insns in table. */ +#define MAX_INSNS ((int) IQ2000_INSN_CTC + 1) + +/* This struct records data prior to insertion or after extraction. */ +struct cgen_fields +{ + int length; + long f_nil; + long f_anyof; + long f_opcode; + long f_rs; + long f_rt; + long f_rd; + long f_shamt; + long f_cp_op; + long f_cp_op_10; + long f_cp_grp; + long f_func; + long f_imm; + long f_rd_rs; + long f_rd_rt; + long f_rt_rs; + long f_jtarg; + long f_jtargq10; + long f_offset; + long f_count; + long f_bytecount; + long f_index; + long f_mask; + long f_maskq10; + long f_maskl; + long f_excode; + long f_rsrvd; + long f_10_11; + long f_24_19; + long f_5; + long f_10; + long f_25; + long f_cam_z; + long f_cam_y; + long f_cm_3func; + long f_cm_4func; + long f_cm_3z; + long f_cm_4z; +}; + +#define CGEN_INIT_PARSE(od) \ +{\ +} +#define CGEN_INIT_INSERT(od) \ +{\ +} +#define CGEN_INIT_EXTRACT(od) \ +{\ +} +#define CGEN_INIT_PRINT(od) \ +{\ +} + + +#endif /* IQ2000_OPC_H */ -- 2.34.1