From f91d48deb29d9e6f4b530f586db0140943ed0d83 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Wed, 5 Apr 2017 20:58:28 +0800 Subject: [PATCH] RISC-V: Fix disassemble for c.li, c.andi and c.addiw ChangeLog 2017-05-03 Kito Cheng * riscv-dis.c (print_insn_args): Handle 'Co' operands. --- opcodes/ChangeLog | 4 ++++ opcodes/riscv-dis.c | 1 + 2 files changed, 5 insertions(+) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 355a162b0e..ea0902fc1d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2017-05-03 Kito Cheng + + * riscv-dis.c (print_insn_args): Handle 'Co' operands. + 2017-05-01 Michael Clark * riscv-opc.c (riscv_opcodes) : Use RA not T1 as a temporary diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d760d701d4..bb53463310 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) case 'i': print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); break; + case 'o': case 'j': print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); break; -- 2.34.1