From 1d899fd652fac98bcbad1f1573f5a6a0224ea2dd Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 15 Aug 2013 14:08:05 +0800 Subject: [PATCH] blackfin: Add STMMAC platform data to enable dwmac1000 driver on BF60x. - Enable GMAC - Set propler DMA PBL - Disable DMA store and forward mode - Select PTP input clock from MII clock. Signed-off-by: Sonic Zhang Signed-off-by: Steven Miao --- arch/blackfin/mach-bf609/boards/ezkit.c | 16 ++++++++++++++++ .../mach-bf609/include/mach/defBF60x_base.h | 10 ++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c index d4dcbab70bb7..d56a55ad83a7 100644 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ b/arch/blackfin/mach-bf609/boards/ezkit.c @@ -104,6 +104,7 @@ static struct platform_device bfin_rotary_device = { #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE) #include +#include static unsigned short pins[] = P_RMII0; @@ -111,11 +112,26 @@ static struct stmmac_mdio_bus_data phy_private_data = { .phy_mask = 1, }; +static struct stmmac_dma_cfg eth_dma_cfg = { + .pbl = 2, +}; + +int stmmac_ptp_clk_init(struct platform_device *pdev) +{ + bfin_write32(PADS0_EMAC_PTP_CLKSEL, 0); + return 0; +} + static struct plat_stmmacenet_data eth_private_data = { + .has_gmac = 1, .bus_id = 0, .enh_desc = 1, .phy_addr = 1, .mdio_bus_data = &phy_private_data, + .dma_cfg = ð_dma_cfg, + .force_thresh_dma_mode = 1, + .interface = PHY_INTERFACE_MODE_RMII, + .init = stmmac_ptp_clk_init, }; static struct platform_device bfin_eth_device = { diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h index f1a6afae1a71..35caa7bc192c 100644 --- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h +++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h @@ -839,6 +839,16 @@ #define PORTG_LOCK 0xFFC03344 /* PORTG Port x GPIO Lock Register */ #define PORTG_REVID 0xFFC0337C /* PORTG Port x GPIO Revision ID */ +/* ================================================== + Pads Controller Registers + ================================================== */ + +/* ========================= + PADS0 + ========================= */ +#define PADS0_EMAC_PTP_CLKSEL 0xFFC03404 /* PADS0 Clock Selection for EMAC and PTP */ +#define PADS0_TWI_VSEL 0xFFC03408 /* PADS0 TWI Voltage Selection */ +#define PADS0_PORTS_HYST 0xFFC03440 /* PADS0 Hysteresis Enable Register */ /* ========================= PINT Registers -- 2.34.1