From 2d78f95bb639209254eb7252f9c48c520bd90d56 Mon Sep 17 00:00:00 2001 From: Andre Vieira Date: Thu, 16 May 2019 11:49:02 +0100 Subject: [PATCH] [PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh gas/ChangeLog: 2019-05-16 Andre Vieira * config/tc-arm.c (do_mve_vmlas): New encoding function. (do_mve_vmulh): Likewise. (insns): Add entries for MVE mnemonics. * testsuite/gas/arm/mve-vmlas-bad.d: New test. * testsuite/gas/arm/mve-vmlas-bad.l: New test. * testsuite/gas/arm/mve-vmlas-bad.s: New test. * testsuite/gas/arm/mve-vmulh-bad.d: New test. * testsuite/gas/arm/mve-vmulh-bad.l: New test. * testsuite/gas/arm/mve-vmulh-bad.s: New test. --- gas/ChangeLog | 12 +++++++ gas/config/tc-arm.c | 46 +++++++++++++++++++++++++++ gas/testsuite/gas/arm/mve-vmlas-bad.d | 5 +++ gas/testsuite/gas/arm/mve-vmlas-bad.l | 16 ++++++++++ gas/testsuite/gas/arm/mve-vmlas-bad.s | 22 +++++++++++++ gas/testsuite/gas/arm/mve-vmulh-bad.d | 5 +++ gas/testsuite/gas/arm/mve-vmulh-bad.l | 29 +++++++++++++++++ gas/testsuite/gas/arm/mve-vmulh-bad.s | 33 +++++++++++++++++++ 8 files changed, 168 insertions(+) create mode 100644 gas/testsuite/gas/arm/mve-vmlas-bad.d create mode 100644 gas/testsuite/gas/arm/mve-vmlas-bad.l create mode 100644 gas/testsuite/gas/arm/mve-vmlas-bad.s create mode 100644 gas/testsuite/gas/arm/mve-vmulh-bad.d create mode 100644 gas/testsuite/gas/arm/mve-vmulh-bad.l create mode 100644 gas/testsuite/gas/arm/mve-vmulh-bad.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 931126eb31..890af8630c 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,15 @@ +2019-05-16 Andre Vieira + + * config/tc-arm.c (do_mve_vmlas): New encoding function. + (do_mve_vmulh): Likewise. + (insns): Add entries for MVE mnemonics. + * testsuite/gas/arm/mve-vmlas-bad.d: New test. + * testsuite/gas/arm/mve-vmlas-bad.l: New test. + * testsuite/gas/arm/mve-vmlas-bad.s: New test. + * testsuite/gas/arm/mve-vmulh-bad.d: New test. + * testsuite/gas/arm/mve-vmulh-bad.l: New test. + * testsuite/gas/arm/mve-vmulh-bad.s: New test. + 2019-05-16 Andre Vieira * config/tc-arm.c (enum operand_parse_code): New operand. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 63d5af175c..1b65a26bcd 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -15704,6 +15704,33 @@ do_mve_viddup (void) inst.is_neon = 1; } +static void +do_mve_vmlas (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + + if (inst.operands[2].reg == REG_PC) + as_tsktsk (MVE_BAD_PC); + else if (inst.operands[2].reg == REG_SP) + as_tsktsk (MVE_BAD_SP); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + inst.instruction |= (et.type == NT_unsigned) << 28; + inst.instruction |= HI1 (inst.operands[0].reg) << 22; + inst.instruction |= neon_logbits (et.size) << 20; + inst.instruction |= LOW4 (inst.operands[1].reg) << 16; + inst.instruction |= LOW4 (inst.operands[0].reg) << 12; + inst.instruction |= HI1 (inst.operands[1].reg) << 7; + inst.instruction |= inst.operands[2].reg; + inst.is_neon = 1; +} + static void do_mve_vmaxnma_vminnma (void) { @@ -17235,6 +17262,21 @@ do_mve_vsbc (void) mve_encode_qqq (1, 64); } +static void +do_mve_vmulh (void) +{ + enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL); + struct neon_type_el et + = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY); + + if (inst.cond > COND_ALWAYS) + inst.pred_insn_type = INSIDE_VPT_INSN; + else + inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN; + + mve_encode_qqq (et.type == NT_unsigned, et.size); +} + static void do_mve_vmull (void) { @@ -24649,6 +24691,10 @@ static const struct asm_opcode insns[] = mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh), + mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas), + mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), + mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh), + #undef THUMB_VARIANT #define THUMB_VARIANT & mve_fp_ext mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul), diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.d b/gas/testsuite/gas/arm/mve-vmlas-bad.d new file mode 100644 index 0000000000..d33b185362 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.d @@ -0,0 +1,5 @@ +#name: Bad MVE VMLAS instructions +#as: -march=armv8.1-m.main+mve +#error_output: mve-vmlas-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.l b/gas/testsuite/gas/arm/mve-vmlas-bad.l new file mode 100644 index 0000000000..3a06f32f63 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.l @@ -0,0 +1,16 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmlas.s64 q0,q1,r2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmlas.f32 q0,q1,r2' +[^:]*:12: Warning: instruction is UNPREDICTABLE with SP operand +[^:]*:13: Warning: instruction is UNPREDICTABLE with PC operand +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:14: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:17: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:19: Error: syntax error -- `vmlaseq.s16 q0,q1,r2' +[^:]*:20: Error: vector predicated instruction should be in VPT/VPST block -- `vmlast.s16 q0,q1,r2' +[^:]*:22: Error: instruction missing MVE vector predication code -- `vmlas.s16 q0,q1,r2' diff --git a/gas/testsuite/gas/arm/mve-vmlas-bad.s b/gas/testsuite/gas/arm/mve-vmlas-bad.s new file mode 100644 index 0000000000..5eff30e4f3 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmlas-bad.s @@ -0,0 +1,22 @@ +.macro cond +.irp cond, eq, ne, gt, ge, lt, le +it \cond +vmlas.s16 q0, q1, r2 +.endr +.endm + +.syntax unified +.thumb +vmlas.s64 q0, q1, r2 +vmlas.f32 q0, q1, r2 +vmlas.u32 q0, q1, sp +vmlas.u32 q0, q1, pc +cond +it eq +vmlaseq.s16 q0, q1, r2 +vmlaseq.s16 q0, q1, r2 +vpst +vmlaseq.s16 q0, q1, r2 +vmlast.s16 q0, q1, r2 +vpst +vmlas.s16 q0, q1, r2 diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.d b/gas/testsuite/gas/arm/mve-vmulh-bad.d new file mode 100644 index 0000000000..febf281254 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.d @@ -0,0 +1,5 @@ +#name: bad MVE VMULH and VRMULH instructions +#as: -march=armv8.1-m.main+mve.fp +#error_output: mve-vmulh-bad.l + +.*: +file format .*arm.* diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.l b/gas/testsuite/gas/arm/mve-vmulh-bad.l new file mode 100644 index 0000000000..7e3c01b38f --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: bad type in SIMD instruction -- `vmulh.f16 q0,q1,q2' +[^:]*:11: Error: bad type in SIMD instruction -- `vmulh.i32 q0,q1,q2' +[^:]*:12: Error: bad type in SIMD instruction -- `vmulh.s64 q0,q1,q2' +[^:]*:13: Error: bad type in SIMD instruction -- `vrmulh.f16 q0,q1,q2' +[^:]*:14: Error: bad type in SIMD instruction -- `vrmulh.i32 q0,q1,q2' +[^:]*:15: Error: bad type in SIMD instruction -- `vrmulh.s64 q0,q1,q2' +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:16: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block +[^:]*:19: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:20: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:22: Error: syntax error -- `vmulheq.s16 q0,q1,q2' +[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vmulht.s16 q0,q1,q2' +[^:]*:25: Error: instruction missing MVE vector predication code -- `vmulh.s16 q0,q1,q2' +[^:]*:27: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:28: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:30: Error: syntax error -- `vrmulheq.s16 q0,q1,q2' +[^:]*:31: Error: vector predicated instruction should be in VPT/VPST block -- `vrmulht.s16 q0,q1,q2' +[^:]*:33: Error: instruction missing MVE vector predication code -- `vrmulh.s16 q0,q1,q2' diff --git a/gas/testsuite/gas/arm/mve-vmulh-bad.s b/gas/testsuite/gas/arm/mve-vmulh-bad.s new file mode 100644 index 0000000000..84d3cceb87 --- /dev/null +++ b/gas/testsuite/gas/arm/mve-vmulh-bad.s @@ -0,0 +1,33 @@ +.macro cond op +.irp cond, eq, ne, gt, ge, lt, le +it \cond +\op\().u16 q0, q1, q2 +.endr +.endm + +.syntax unified +.thumb +vmulh.f16 q0, q1, q2 +vmulh.i32 q0, q1, q2 +vmulh.s64 q0, q1, q2 +vrmulh.f16 q0, q1, q2 +vrmulh.i32 q0, q1, q2 +vrmulh.s64 q0, q1, q2 +cond vmulh +cond vrmulh +it eq +vmulheq.s16 q0, q1, q2 +vmulheq.s16 q0, q1, q2 +vpst +vmulheq.s16 q0, q1, q2 +vmulht.s16 q0, q1, q2 +vpst +vmulh.s16 q0, q1, q2 +it eq +vrmulheq.s16 q0, q1, q2 +vrmulheq.s16 q0, q1, q2 +vpst +vrmulheq.s16 q0, q1, q2 +vrmulht.s16 q0, q1, q2 +vpst +vrmulh.s16 q0, q1, q2 -- 2.34.1