From 4de6b5d3610276befcc3af6aad5975638d836c77 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Tue, 2 Sep 1997 03:49:55 +0000 Subject: [PATCH] Merge SH4 branch simulator in to devo. --- sim/sh/.Sanitize | 30 + sim/sh/ChangeLog | 115 ++++ sim/sh/gencode.c | 1609 +++++++++++++++++++++++++++++++++++++++------- sim/sh/interp.c | 572 ++++++++++++---- 4 files changed, 1964 insertions(+), 362 deletions(-) diff --git a/sim/sh/.Sanitize b/sim/sh/.Sanitize index 0c6c23f180..6b3a315985 100644 --- a/sim/sh/.Sanitize +++ b/sim/sh/.Sanitize @@ -40,4 +40,34 @@ Things-to-lose: Do-last: +sh4_files="ChangeLog interp.c gencode.c" + +if ( echo $* | grep keep\-sh4 > /dev/null ) ; then + for i in $sh4_files ; do + if test ! -d $i && (grep sanitize-sh4 $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Keeping sh4 stuff in $i + fi + fi + done +else + for i in * ; do + if test ! -d $i && (grep sanitize-sh4 $i > /dev/null) ; then + if [ -n "${verbose}" ] ; then + echo Removing traces of \"sh4\" from $i... + fi + cp $i new + sed '/start\-sanitize\-sh4/,/end-\sanitize\-sh4/d' < $i > new + if [ -n "${safe}" -a ! -f .Recover/$i ] ; then + if [ -n "${verbose}" ] ; then + echo Caching $i in .Recover... + fi + mv $i .Recover + fi + mv new $i + fi + done +fi + + # End of file. diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog index c3eecc745e..f11b4d79a7 100644 --- a/sim/sh/ChangeLog +++ b/sim/sh/ChangeLog @@ -1,3 +1,7 @@ +Tue Sep 2 13:15:27 1997 Andrew Cagney + + * gencode.c (tab): Order instructions according to SH3 document. + Wed Aug 27 18:13:22 1997 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. @@ -19,6 +23,117 @@ Mon Aug 25 16:17:51 1997 Andrew Cagney * interp.c (sim_open): Add ABFD argument. +Mon Jun 23 15:49:14 1997 Andrew Cagney + + * interp.c (get_dr): Avoid SIGFPE by moving integers instead of + FP's around. + (set_dr): Ditto. + +start-sanitize-sh4 +Mon Jun 23 15:02:40 1997 Andrew Cagney + + * interp.c (XD, SET_XD): Delete. + (XF, SET_XF, XD_TO_XF): Define, move around registers in either + FP bank. + + * gencode.c (fmov): Update. + +end-sanitize-sh4 +Sun Jun 22 19:33:33 1997 Andrew Cagney + + * interp.c (set_fpscr1): From J"orn Rennecke + , Fix typo. Ditto for comment. + +start-sanitize-sh4 +Tue Aug 12 00:19:11 1997 J"orn Rennecke + + * interp.c (special_address): New function. + (BUSERROR): Call it. Added parameters bits_written and data. + Changed all callers. + * gencode.c (tab): Fixed ocbwb and pref. + +end-sanitize-sh4 +start-sanitize-sh4 +Fri Jun 20 22:03:18 1997 J"orn Rennecke + + * interp.c (do_wdat, do_wdat): Fix bug in register number calculation. + +end-sanitize-sh4 +Thu Jun 19 00:28:08 1997 Andrew Cagney + + * interp.c (sim_create_inferior): Clear registers each time an + inferior is started. + +start-sanitize-sh4 +Mon Jun 16 14:01:55 1997 Andrew Cagney + + * interp.c (*FP, FP_OP, FP_CMP, FP_UNARY): Provide a hook for + when a host doesn't support IEEE FP. + (*DP): Provide alternative definition that supports 64bit floating + point. + (target_little_endian): Combine little_endian and little_endian_p. + (saved_state_type): Make fpscr and sr simple integers. + (SET_FPSCR, GET_FPSCR): Use macros to update fpscr register. + (set_fpscr1): New function. Handle swapping when PR / FR bits + changed. Call via *_FPSCR macro. + (SET_SR*, GET_SR*): Use macro's to access the SR bits - avoids + endian problems. + + * gencode.c (tab): Update. + +end-sanitize-sh4 +Sun Jun 15 15:22:52 1997 Andrew Cagney + + * gencode.c (main): Perform basic checks on tab entries. + + * Makefile.in (gencode): Always compile with -g. + +Sat Jun 14 13:45:09 1997 Andrew Cagney + + * gencode.c (gensim): Move ref checking code to before `stuff'. + For branches with delay slots refs were not being checked. + + * interp.c (sim_resume): Use nia to specify the next instruction + address instead of overloading pc. + (C): Delete definiton - refer to cycles directly. + (SEXT12): New macro - sign extend a 12 bit quantity. + (Delay_Slot): Rename from SL. + + * gencode.c (tab): Update/simplify. + + * gencode.c (gensim): Better formatting of output code. + (gensim): Replace 10 with constant MAX_NR_STUFF- define as 15. + (tab): Sort alphabetically. Break `stuff' into multiple lines. + +Fri Jun 13 22:10:13 1997 J"orn Rennecke + + * gencode.c (braf, bsrf): Fix branch destination calculation to + be in accordance with the documentation. + +Fri Jun 13 15:33:53 1997 J"orn Rennecke + + * interp.c (init_pointers): Fix little endian test. + +start-sanitize-sh4 +Thu Jun 5 12:56:08 1997 J"orn Rennecke + + * interp.c (init_pointers): SH4 hardware is always WORDS_BIT_ENDIAN. + * gencode (fmov from/to memory): take endian_mismatch into account + for 32 bit moves too. + +end-sanitize-sh4 +Wed May 28 23:42:35 1997 J"orn Rennecke + + * gencode.c (swap.b): Fix treatment of high word. + +start-sanitize-sh4 +Wed May 28 23:42:35 1997 J"orn Rennecke + + * sh/gencode.c, + * interp.c: experimental SH4 support. Lacks sanitation. + DFmode moves are probaly broken for target little endian. + +end-sanitize-sh4 Tue May 20 10:23:28 1997 Andrew Cagney * interp.c (sim_open): Add callback argument. diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c index a1874c0013..75a6eae09a 100644 --- a/sim/sh/gencode.c +++ b/sim/sh/gencode.c @@ -31,13 +31,15 @@ #include +#define MAX_NR_STUFF 20 + typedef struct { -char *defs; -char *refs; + char *defs; + char *refs; char *name; char *code; - char *stuff[10]; + char *stuff[MAX_NR_STUFF]; int index; } @@ -47,210 +49,1316 @@ op; op tab[] = { - {"n","","add #,", "0111nnnni8*1....", "R[n] += SEXT(i);if (i == 0) { UNDEF(n); break; } "}, - {"n","mn","add ,", "0011nnnnmmmm1100", "R[n] += R[m];"}, - {"n","mn","addc ,", "0011nnnnmmmm1110", - "ult=R[n]+T;T=ult,", "0011nnnnmmmm1111", - "ult = R[n] + R[m]; T = ((~(R[n] ^ R[m]) & (ult ^ R[n])) >> 31); R[n] = ult;"}, - {"0","","and #,R0", "11001001i8*1....", ";R0&=i;"}, - {"n","nm","and ,", "0010nnnnmmmm1001", " R[n]&=R[m];"}, - {"","0","and.b #,@(R0,GBR)", "11001101i8*1....", ";WBAT(GBR+R0, RBAT(GBR+R0) & i);"}, - - {"","","bra ", "1010i12.........", "ult = PC; PC=PC+(i<<1)+2;SL(ult+2);"}, - {"","","bsr ", "1011i12.........", "PR = PC + 4; PC=PC+(i<<1)+2;SL(PR-2);"}, - {"","","bt ", "10001001i8p1....", "if(T) {PC+=(SEXT(i)<<1)+2;C+=2;}"}, - {"","","bf ", "10001011i8p1....", "if(T==0) {PC+=(SEXT(i)<<1)+2;C+=2;}"}, - {"","","bt.s ", "10001101i8p1....","if(T) {ult = PC; PC+=(SEXT(i)<<1)+2;C+=2;SL(ult+2);}"}, - {"","","bf.s ", "10001111i8p1....","if(!T) {ult = PC; PC+=(SEXT(i)<<1)+2;C+=2;SL(ult+2);}"}, - {"","","clrmac", "0000000000101000", "MACH = MACL = 0;"}, - {"","","clrs", "0000000001001000", "S= 0;"}, - {"","","clrt", "0000000000001000", "T= 0;"}, - {"","0","cmp/eq #,R0", "10001000i8*1....", ";T = R0 == SEXT(i);"}, - {"","mn","cmp/eq ,", "0011nnnnmmmm0000", "T=R[n]==R[m];"}, - {"","mn","cmp/ge ,", "0011nnnnmmmm0011", "T=R[n]>=R[m];"}, - {"","mn","cmp/gt ,", "0011nnnnmmmm0111", "T=R[n]>R[m];"}, - {"","mn","cmp/hi ,", "0011nnnnmmmm0110", "T=UR[n]>UR[m];"}, - {"","mn","cmp/hs ,", "0011nnnnmmmm0010", "T=UR[n]>=UR[m];"}, - {"","n","cmp/pl ", "0100nnnn00010101", "T = R[n]>0;"}, - {"","n","cmp/pz ", "0100nnnn00010001", "T = R[n]>=0;"}, - {"","mn","cmp/str ,", "0010nnnnmmmm1100", - "ult = R[n] ^ R[m]; T=((ult&0xff000000)==0) |((ult&0xff0000)==0) |((ult&0xff00)==0) |((ult&0xff)==0); "}, - {"","mn","div0s ,", "0010nnnnmmmm0111", "Q=(R[n]&sbit)!=0; M=(R[m]&sbit)!=0; T=M!=Q;;"}, - {"","","div0u", "0000000000011001", "M=Q=T=0;"}, - {"","","div1 ,", "0011nnnnmmmm0100", "T=div1(R,m,n,T);"}, - {"n","m","exts.b ,", "0110nnnnmmmm1110", "R[n] = SEXT(R[m]);"}, - {"n","m","exts.w ,", "0110nnnnmmmm1111", "R[n] = SEXTW(R[m]);"}, - {"n","m","extu.b ,", "0110nnnnmmmm1100", "R[n] = R[m] & 0xff;"}, - {"n","m","extu.w ,", "0110nnnnmmmm1101", "R[n] = R[m] & 0xffff;"}, - {"","n","jmp @", "0100nnnn00101011", "ult = PC; PC=R[n]-2; SL(ult+2);"}, - {"","n","jsr @", "0100nnnn00001011", "PR = PC + 4; PC=R[n]-2; if (~doprofile) gotcall(PR,PC+2);SL(PR-2);"}, - {"","n","ldc ,SR", "0100nnnn00001110", "SET_SR(R[n]);"}, - {"","n","ldc ,GBR", "0100nnnn00011110", "GBR=R[n];"}, - {"","n","ldc ,VBR", "0100nnnn00101110", "VBR=R[n];"}, - {"","n","ldc ,SSR", "0100nnnn00111110", "SSR=R[n];"}, - {"","n","ldc ,SPC", "0100nnnn01001110", "SPC=R[n];"}, - {"","n","ldc.l @+,SR", "0100nnnn00000111", "SET_SR(RLAT(R[n]));R[n]+=4;;"}, - {"","n","ldc.l @+,GBR", "0100nnnn00010111", "GBR=RLAT(R[n]);R[n]+=4;;"}, - {"","n","ldc.l @+,VBR", "0100nnnn00100111", "VBR=RLAT(R[n]);R[n]+=4;;"}, - {"","n","ldc.l @+,SSR", "0100nnnn00110111", "SSR=RLAT(R[n]);R[n]+=4;;"}, - {"","n","ldc.l @+,SPC", "0100nnnn01000111", "SPC=RLAT(R[n]);R[n]+=4;;"}, - {"","n","lds ,MACH", "0100nnnn00001010", "MACH = R[n];"}, - {"","n","lds ,MACL", "0100nnnn00011010", "MACL= R[n];"}, - {"","n","lds ,PR", "0100nnnn00101010", "PR = R[n];"}, - {"","n","lds.l @+,MACH", "0100nnnn00000110", "MACH = SEXT(RLAT(R[n]));R[n]+=4;"}, - {"","n","lds.l @+,MACL", "0100nnnn00010110", "MACL = RLAT(R[n]);R[n]+=4;"}, - {"","n","lds.l @+,PR", "0100nnnn00100110", "PR = RLAT(R[n]);R[n]+=4;;"}, - {"","","ldtlb", "0000000000111000", "/*XXX*/ abort();"}, - {"","n","mac.w @+,@+", "0100nnnnmmmm1111", "macw(R0,memory,n,m);"}, - {"n","","mov #,", "1110nnnni8*1....", "R[n] = SEXT(i);"}, - {"n","m","mov ,", "0110nnnnmmmm0011", "R[n] = R[m];"}, - {"","mn0","mov.b ,@(R0,)", "0000nnnnmmmm0100", "WBAT(R[n]+R0, R[m]);"}, - {"","nm","mov.b ,@-", "0010nnnnmmmm0100", "R[n]--; WBAT(R[n],R[m]);"}, - {"","mn","mov.b ,@", "0010nnnnmmmm0000", "WBAT(R[n], R[m]);"}, - {"0","m","mov.b @(,),R0", "10000100mmmmi4*1", "R0=RSBAT(i+R[m]);L(0);"}, - {"0","","mov.b @(,GBR),R0", "11000100i8*1....", "R0=RSBAT(i+GBR);L(0);"}, - {"n","0m","mov.b @(R0,),", "0000nnnnmmmm1100", "R[n]=RSBAT(R0+R[m]);L(n);"}, - {"n","m","mov.b @+,", "0110nnnnmmmm0100", "R[n] = RSBAT(R[m]);L(n);R[m]++;"}, - {"n","m","mov.b @,", "0110nnnnmmmm0000", "R[n]=RSBAT(R[m]);L(n);"}, - {"","m0","mov.b R0,@(,)", "10000000mmmmi4*1", "WBAT(i+R[m],R0);"}, - {"","0","mov.b R0,@(,GBR)", "11000000i8*1....", "WBAT(i+GBR,R0);"}, - {"","nm","mov.l ,@(,)", "0001nnnnmmmmi4*4", "WLAT(i+R[n],R[m]);"}, - {"","nm0","mov.l ,@(R0,)", "0000nnnnmmmm0110", "WLAT(R0+R[n],R[m]);"}, - {"","nm","mov.l ,@-", "0010nnnnmmmm0110", "R[n]-=4;WLAT(R[n],R[m]);"}, - {"","nm","mov.l ,@", "0010nnnnmmmm0010", "WLAT(R[n], R[m]);"}, - {"n","m","mov.l @(,),","0101nnnnmmmmi4*4", "R[n]=RLAT(i+R[m]);L(n);"}, - {"0","","mov.l @(,GBR),R0", "11000110i8*4....", "R0=RLAT(i+GBR);L(0);"}, - {"n","","mov.l @(,PC),", "1101nnnni8p4....", "R[n]=RLAT((i+4+PC) & ~3);L(n);"}, - {"n","m","mov.l @(R0,),", "0000nnnnmmmm1110", "R[n]=RLAT(R0+R[m]);L(n);"}, -{"nm","m","mov.l @+,", "0110nnnnmmmm0110", "R[n]=RLAT(R[m]);R[m]+=4;L(n);"}, - {"n","m","mov.l @,", "0110nnnnmmmm0010", "R[n]=RLAT(R[m]);L(n);"}, - {"","0","mov.l R0,@(,GBR)", "11000010i8*4....", "WLAT(i+GBR,R0);"}, - {"","m0n","mov.w ,@(R0,)", "0000nnnnmmmm0101", "WWAT(R0+R[n],R[m]);"}, -{"n","mn","mov.w ,@-", "0010nnnnmmmm0101", "R[n]-=2;WWAT(R[n],R[m]);"}, - {"","nm","mov.w ,@", "0010nnnnmmmm0001", "WWAT(R[n],R[m]);"}, - {"0","m","mov.w @(,),R0", "10000101mmmmi4*2", "R0=RSWAT(i+R[m]);L(0);"}, - {"0","","mov.w @(,GBR),R0", "11000101i8*2....", "R0=RSWAT(i+GBR);L(0);"}, - {"n","","mov.w @(,PC),", "1001nnnni8p2....", "R[n]=RSWAT(PC+i+4);L(n);"}, -{"n","m0","mov.w @(R0,),", "0000nnnnmmmm1101", "R[n]=RSWAT(R0+R[m]);L(n);"}, -{"nm","n","mov.w @+,", "0110nnnnmmmm0101", "R[n]=RSWAT(R[m]);R[m]+=2;L(n);"}, - {"n","m","mov.w @,", "0110nnnnmmmm0001", "R[n]=RSWAT(R[m]);L(n);"}, - {"","0m","mov.w R0,@(,)", "10000001mmmmi4*2", "WWAT(i+R[m],R0);"}, - {"","0","mov.w R0,@(,GBR)", "11000001i8*2....", "WWAT(i+GBR,R0);"}, - {"0","","mova @(,PC),R0", "11000111i8p4....", "R0=((i+4+PC) & ~0x3);"}, - {"n","","movt ", "0000nnnn00101001", "R[n]=T;"}, - {"","mn","muls ,", "0010nnnnmmmm1111","MACL=((int)(short)R[n])*((int)(short)R[m]);"}, - {"","mn","mul.l ,","0000nnnnmmmm0111","MACL=((int)R[n])*((int)R[m]);"}, - {"","mn","mulu ,", "0010nnnnmmmm1110","MACL=((unsigned int)(unsigned short)R[n])*((unsigned int)(unsigned short)R[m]);"}, - {"n","m","neg ,", "0110nnnnmmmm1011", "R[n] = - R[m];"}, - {"n","m","negc ,", "0110nnnnmmmm1010", "ult=-T;T=ult>0;R[n]=ult-R[m];T|=R[n]>ult;"}, - {"","","nop", "0000000000001001", ""}, - {"n","m","not ,", "0110nnnnmmmm0111", "R[n]=~R[m];"}, - {"0","","or #,R0", "11001011i8*1....", "R0|=i;"}, - {"n","m","or ,", "0010nnnnmmmm1011", "R[n]|=R[m];"}, - {"","0","or.b #,@(R0,GBR)", "11001111i8*1....", "WBAT(R0+GBR,RBAT(R0+GBR)|i);"}, -{"n","n","rotcl ", "0100nnnn00100100", "ult=R[n]<0;R[n]=(R[n]<<1)|T;T=ult;"}, - {"n","n","rotcr ", "0100nnnn00100101", "ult=R[n]&1;R[n]=(UR[n]>>1)|(T<<31);T=ult;"}, - {"n","n","rotl ", "0100nnnn00000100", "T=R[n]<0;R[n]<<=1;R[n]|=T;"}, - {"n","n","rotr ", "0100nnnn00000101", "T=R[n]&1;R[n] = UR[n]>> 1;R[n]|=(T<<31);"}, - {"","","rte", "0000000000101011", - "{ int tmp = PC; PC=RLAT(R[15])+2;R[15]+=4;SET_SR(RLAT(R[15]) & 0x3f3);R[15]+=4;SL(tmp+2);}"}, - {"","","rts", "0000000000001011", "ult=PC;PC=PR-2;SL(ult+2);"}, - {"","","sets", "0000000001011000", "S=1;"}, - {"","","sett", "0000000000011000", "T=1;"}, - {"n","mn","shad ,", "0100nnnnmmmm1100", - "R[n] = (R[m] < 0) ? (R[n] >> ((-R[m])&0x1f)) : (R[n] << (R[m] & 0x1f));"}, - {"n","mn","shld ,", "0100nnnnmmmm1101", - "R[n] = (R[m] < 0) ? (UR[n] >> ((-R[m])&0x1f)): (R[n] << (R[m] & 0x1f));"}, - {"n","n","shal ", "0100nnnn00100000", "T=R[n]<0; R[n]<<=1;"}, - {"n","n","shar ", "0100nnnn00100001", "T=R[n]&1; R[n] = R[n] >> 1;"}, - {"n","n","shll ", "0100nnnn00000000", "T=R[n]<0; R[n]<<=1;"}, - {"n","n","shll16 ", "0100nnnn00101000", "R[n]<<=16;"}, - {"n","n","shll2 ", "0100nnnn00001000", "R[n]<<=2;"}, - {"n","n","shll8 ", "0100nnnn00011000", "R[n]<<=8;"}, - {"n","n","shlr ", "0100nnnn00000001", "T=R[n]&1;R[n]=UR[n]>>1;"}, - {"n","n","shlr16 ", "0100nnnn00101001", "R[n]=UR[n]>>16;"}, - {"n","n","shlr2 ", "0100nnnn00001001", "R[n]=UR[n]>>2;"}, - {"n","n","shlr8 ", "0100nnnn00011001", "R[n]=UR[n]>>8;"}, - {"","","sleep", "0000000000011011", "trap(0xc3,R0,memory,maskl,maskw,little_endian);PC-=2;"}, - {"n","","stc SR,", "0000nnnn00000010", "R[n]=GET_SR();"}, - {"n","","stc GBR,", "0000nnnn00010010", "R[n]=GBR;"}, - {"n","","stc VBR,", "0000nnnn00100010", "R[n]=VBR;"}, - {"n","","stc SSR,", "0000nnnn00110010", "R[n]=SSR;"}, - {"n","","stc SPC,", "0000nnnn01000010", "R[n]=SPC;"}, - {"n","n","stc.l SR,@-", "0100nnnn00000011", "R[n]-=4;WLAT(R[n],GET_SR());"}, - {"n","n","stc.l GBR,@-", "0100nnnn00010011", "R[n]-=4;WLAT(R[n],GBR);;"}, - {"n","n","stc.l VBR,@-", "0100nnnn00100011", "R[n]-=4;WLAT(R[n],VBR);"}, - {"n","n","stc.l SSR,@-", "0100nnnn00110011", "R[n]-=4;WLAT(R[n],SSR);"}, - {"n","n","stc.l SPC,@-", "0100nnnn01000011", "R[n]-=4;WLAT(R[n],SPC);"}, - {"n","","sts MACH,", "0000nnnn00001010", "R[n]=MACH;"}, - {"n","","sts MACL,", "0000nnnn00011010", "R[n]=MACL;"}, - {"n","","sts PR,", "0000nnnn00101010", "R[n]=PR;"}, - {"n","n","sts.l MACH,@-", "0100nnnn00000010", "R[n]-=4;WLAT(R[n],MACH);"}, - {"n","n","sts.l MACL,@-", "0100nnnn00010010", "R[n]-=4;WLAT(R[n],MACL);"}, - {"n","n","sts.l PR,@-", "0100nnnn00100010", "R[n]-=4;WLAT(R[n],PR);"}, - {"n","nm","sub ,", "0011nnnnmmmm1000", "R[n]-=R[m];"}, -{"n","nm","subc ,", "0011nnnnmmmm1010", "ult=R[n]-T;T=ult>R[n];R[n]=ult-R[m];T|=R[n]>ult;"}, - {"n","nm","subv ,", "0011nnnnmmmm1011", - "ult = R[n] - R[m]; T = (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31); R[n] = ult;"}, - {"n","nm","swap.b ,", "0110nnnnmmmm1000", "R[n]=((R[m]<<8)&0xff00)|((R[m]>>8)&0x00ff);"}, - {"n","nm","swap.w ,", "0110nnnnmmmm1001", "R[n]=((R[m]<<16)&0xffff0000)|((R[m]>>16)&0x00ffff);"}, - {"","n","tas.b @", "0100nnnn00011011", "ult=RBAT(R[n]);T=ult==0;WBAT(R[n],ult|0x80);"}, - {"0","","trapa #", "11000011i8*1....", - "{ long imm = 0xff & i; if (i==0xc3) PC-=2; if (i<20||i==34||i==0xc3) trap(i,R,memory,maskl,maskw,little_endian); else { R[15]-=4; WLAT(R[15],GET_SR()); R[15]-=4;WLAT(R[15],PC+2); PC=RLAT(VBR+(imm<<2))-2;}}"}, - {"","0","tst #,R0", "11001000i8*1....", "T=(R0&i)==0;"}, - {"","mn","tst ,", "0010nnnnmmmm1000", "T=(R[n]&R[m])==0;"}, - {"","0","tst.b #,@(R0,GBR)", "11001100i8*1....", "T=(RBAT(GBR+R0)&i)==0;"}, - {"","0","xor #,R0", "11001010i8*1....", "R0^=i;"}, - {"n","mn","xor ,", "0010nnnnmmmm1010", "R[n]^=R[m];"}, - {"","0","xor.b #,@(R0,GBR)", "11001110i8*1....", "ult=RBAT(GBR+R0);ult^=i;WBAT(GBR+R0,ult);"}, - {"n","nm","xtrct ,", "0010nnnnmmmm1101", "R[n]=((R[n]>>16)&0xffff)|((R[m]<<16)&0xffff0000);"}, - {"","nm","mul.l ,", "0000nnnnmmmm0111", " MACL = R[n] * R[m];"}, - {"n","n","dt ", "0100nnnn00010000", "R[n]--; T=R[n] == 0;"}, - {"","nm","dmuls.l ,", "0011nnnnmmmm1101", "dmul(1,R[n],R[m]);"}, - {"","nm","dmulu.l ,", "0011nnnnmmmm0101", "dmul(0,R[n],R[m]);"}, - {"","nm","mac.l @+,@+", "0000nnnnmmmm1111", "abort();"}, - {"","n","braf ", "0000nnnn00100011", "ult = PC; PC+=R[n]-2;SL(ult+2);"}, - {"","n","bsrf ", "0000nnnn00000011", "PR = PC + 4; PC+=R[n]-2;SL(PR-2);"}, + { "n", "", "add #,", "0111nnnni8*1....", + "R[n] += SEXT(i);", + "if (i == 0) {", + " UNDEF(n); /* see #ifdef PARANOID */", + " break;", + "}", + }, + { "n", "mn", "add ,", "0011nnnnmmmm1100", + "R[n] += R[m];", + }, + + { "n", "mn", "addc ,", "0011nnnnmmmm1110", + "ult = R[n] + T;", + "SET_SR_T (ult < R[n]);", + "R[n] = ult + R[m];", + "SET_SR_T (T || (R[n] < ult));", + }, + + { "n", "mn", "addv ,", "0011nnnnmmmm1111", + "ult = R[n] + R[m];", + "SET_SR_T ((~(R[n] ^ R[m]) & (ult ^ R[n])) >> 31);", + "R[n] = ult;", + }, + + { "0", "", "and #,R0", "11001001i8*1....", + "R0 &= i;", + }, + { "n", "nm", "and ,", "0010nnnnmmmm1001", + "R[n] &= R[m];", + }, + { "", "0", "and.b #,@(R0,GBR)", "11001101i8*1....", + "MA (1);", + "WBAT (GBR + R0, RBAT (GBR + R0) & i);", + }, + + { "", "", "bf ", "10001011i8p1....", + "if (!T) {", + " nia = PC + 4 + (SEXT(i) * 2);", + " cycles += 2;", + "}", + }, + + { "", "", "bf.s ", "10001111i8p1....", + "if (!T) {", + " nia = PC + 4 + (SEXT (i) * 2);", + " cycles += 2;", + " Delay_Slot (PC + 2);", + "}", + }, + + { "", "", "bra ", "1010i12.........", + "nia = PC + 4 + (SEXT12 (i) * 2);", + "Delay_Slot (PC + 2);", + }, + + { "", "n", "braf ", "0000nnnn00100011", + "nia = PC + 4 + R[n];", + "Delay_Slot (PC + 2);", + }, + + { "", "", "bsr ", "1011i12.........", + "PR = PC + 4;", + "nia = PC + 4 + (SEXT12 (i) * 2);", + "Delay_Slot (PC + 2);", + }, + + { "", "n", "bsrf ", "0000nnnn00000011", + "PR = PC + 4;", + "nia = PC + 4 + R[n];", + "Delay_Slot (PC + 2);", + }, + + { "", "", "bt ", "10001001i8p1....", + "if (T) {", + " nia = PC + 4 + (SEXT (i) * 2);", + " cycles += 2;", + "}", + }, + + { "", "", "bt.s ", "10001101i8p1....", + "if (T) {", + " nia = PC + 4 + (SEXT (i) * 2);", + " cycles += 2;", + " Delay_Slot (PC + 2);", + "}", + }, + + { "", "", "clrmac", "0000000000101000", + "MACH = 0;", + "MACL = 0;", + }, + + { "", "", "clrs", "0000000001001000", + "SET_SR_S (0);", + }, + + { "", "", "clrt", "0000000000001000", + "SET_SR_T (0);", + }, + + { "", "0", "cmp/eq #,R0", "10001000i8*1....", + "SET_SR_T (R0 == SEXT (i));", + }, + { "", "mn", "cmp/eq ,", "0011nnnnmmmm0000", + "SET_SR_T (R[n] == R[m]);", + }, + { "", "mn", "cmp/ge ,", "0011nnnnmmmm0011", + "SET_SR_T (R[n] >= R[m]);", + }, + { "", "mn", "cmp/gt ,", "0011nnnnmmmm0111", + "SET_SR_T (R[n] > R[m]);", + }, + { "", "mn", "cmp/hi ,", "0011nnnnmmmm0110", + "SET_SR_T (UR[n] > UR[m]);", + }, + { "", "mn", "cmp/hs ,", "0011nnnnmmmm0010", + "SET_SR_T (UR[n] >= UR[m]);", + }, + { "", "n", "cmp/pl ", "0100nnnn00010101", + "SET_SR_T (R[n] > 0);", + }, + { "", "n", "cmp/pz ", "0100nnnn00010001", + "SET_SR_T (R[n] >= 0);", + }, + { "", "mn", "cmp/str ,", "0010nnnnmmmm1100", + "ult = R[n] ^ R[m];", + "SET_SR_T (((ult & 0xff000000) == 0)", + " | ((ult & 0xff0000) == 0)", + " | ((ult & 0xff00) == 0)", + " | ((ult & 0xff) == 0));", + }, + + { "", "mn", "div0s ,", "0010nnnnmmmm0111", + "SET_SR_Q ((R[n] & sbit) != 0);", + "SET_SR_M ((R[m] & sbit) != 0);", + "SET_SR_T (M != Q);", + }, + + { "", "", "div0u", "0000000000011001", + "SET_SR_M (0);", + "SET_SR_Q (0);", + "SET_SR_T (0);", + }, + + { "", "", "div1 ,", "0011nnnnmmmm0100", + "div1 (R, m, n/*, T*/);", + }, + + { "", "nm", "dmuls.l ,", "0011nnnnmmmm1101", + "dmul (1/*signed*/, R[n], R[m]);", + }, + + { "", "nm", "dmulu.l ,", "0011nnnnmmmm0101", + "dmul (0/*unsigned*/, R[n], R[m]);", + }, + + { "n", "n", "dt ", "0100nnnn00010000", + "R[n]--;", + "SET_SR_T (R[n] == 0);", + }, + + { "n", "m", "exts.b ,", "0110nnnnmmmm1110", + "R[n] = SEXT (R[m]);", + }, + { "n", "m", "exts.w ,", "0110nnnnmmmm1111", + "R[n] = SEXTW (R[m]);", + }, + + { "n", "m", "extu.b ,", "0110nnnnmmmm1100", + "R[n] = (R[m] & 0xff);", + }, + { "n", "m", "extu.w ,", "0110nnnnmmmm1101", + "R[n] = (R[m] & 0xffff);", + }, + + /* sh3e */ + { "", "", "fabs ", "1111nnnn01011101", + "FP_UNARY (n, fabs);", + "/* FIXME: FR(n) &= 0x7fffffff; */", + }, + + /* sh3e */ + { "", "", "fadd ,", "1111nnnnmmmm0000", + "FP_OP (n, +, m);", + }, + + /* sh3e */ + { "", "", "fcmp/eq ,", "1111nnnnmmmm0100", + "FP_CMP (n, ==, m);", + }, + /* sh3e */ + { "", "", "fcmp/gt ,", "1111nnnnmmmm0101", + "FP_CMP (n, >, m);", + }, + + /* start-sanitize-sh4 */ + { "", "", "fcnvds ,FPUL", "1111nnnn10111101", + "if (! FPSCR_PR || n & 1)", + " saved_state.asregs.exception = SIGILL;", + "else", + "{", + " char buf[4];", + " *(float *)buf = DR(n);", + " FPUL = *(int *)buf;", + "}", + }, + /* end-sanitize-sh4 */ + + /* start-sanitize-sh4 */ + { "", "", "fcnvsd FPUL,", "1111nnnn10101101", + "if (! FPSCR_PR || n & 1)", + " saved_state.asregs.exception = SIGILL;", + "else", + "{", + " char buf[4];", + " *(int *)buf = FPUL;", + " SET_DR(n, *(float *)buf);", + "}", + }, + /* end-sanitize-sh4 */ + + /* sh3e */ + { "", "", "fdiv ,", "1111nnnnmmmm0011", + "FP_OP (n, /, m);", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + + /* start-sanitize-sh4 */ + { "", "", "fipr ,", "1111nnmm11101101", + "/* FIXME: not implemented */", + "saved_state.asregs.exception = SIGILL;", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + /* end-sanitize-sh4 */ + + /* sh3e */ + { "", "", "fldi0 ", "1111nnnn10001101", + "SET_FR (n, (float)0.0);", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + + /* sh3e */ + { "", "", "fldi1 ", "1111nnnn10011101", + "SET_FR (n, (float)1.0);", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + + /* sh3e */ + { "", "", "flds ,FPUL", "1111nnnn00011101", + "char buf[4];", + "*(float *)buf = FR(n);", + "FPUL = *(int *)buf;", + }, + + /* sh3e */ + { "", "", "float FPUL,", "1111nnnn00101101", + /* start-sanitize-sh4 */ + "if (FPSCR_PR)", + " SET_DR (n, (double)FPUL);", + "else", + /* end-sanitize-sh4 */ + "{", + " SET_FR (n, (float)FPUL);", + "}", + }, + + /* sh3e */ + { "", "", "fmac ,,", "1111nnnnmmmm1110", + "SET_FR (n, FR(m) * FR(0) + FR(n));", + "/* FIXME: check for DP and (n & 1) == 0? */", + }, + + /* sh3e */ + { "", "", "fmov ,", "1111nnnnmmmm1100", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " int ni = XD_TO_XF (n);", + " int mi = XD_TO_XF (m);", + " SET_XF (ni + 0, XF (mi + 0));", + " SET_XF (ni + 1, XF (mi + 1));", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " SET_FR (n, FR (m));", + "}", + }, + /* sh3e */ + { "", "", "fmov.s ,@", "1111nnnnmmmm1010", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " WDAT (R[n], m);", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " WLAT (R[n], FI(m));", + "}", + }, + /* sh3e */ + { "", "", "fmov.s @,", "1111nnnnmmmm1000", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[m], n);", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " SET_FI(n, RLAT(R[m]));", + "}", + }, + /* sh3e */ + { "", "", "fmov.s @+,", "1111nnnnmmmm1001", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[m], n);", + " R[m] += 8;", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " SET_FI (n, RLAT (R[m]));", + " R[m] += 4;", + "}", + }, + /* sh3e */ + { "", "", "fmov.s ,@-", "1111nnnnmmmm1011", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " R[n] -= 8;", + " WDAT (R[n], m);", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " R[n] -= 4;", + " WLAT (R[n], FI(m));", + "}", + }, + /* sh3e */ + { "", "", "fmov.s @(R0,),", "1111nnnnmmmm0110", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " RDAT (R[0]+R[m], n);", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " SET_FI(n, RLAT(R[0] + R[m]));", + "}", + }, + /* sh3e */ + { "", "", "fmov.s ,@(R0,)", "1111nnnnmmmm0111", + /* start-sanitize-sh4 */ + "if (FPSCR_SZ) {", + " MA (2);", + " WDAT (R[0]+R[n], m);", + "}", + "else", + /* end-sanitize-sh4 */ + "{", + " MA (1);", + " WLAT((R[0]+R[n]), FI(m));", + "}", + }, + + /* start-sanitize-sh4 */ + /* See fmov instructions above for move to/from extended fp + registers */ + /* end-sanitize-sh4 */ + + /* sh3e */ + { "", "", "fmul ,", "1111nnnnmmmm0010", + "FP_OP(n, *, m);", + }, + + /* sh3e */ + { "", "", "fneg ", "1111nnnn01001101", + "FP_UNARY(n, -);", + }, + + /* start-sanitize-sh4 */ + { "", "", "frchg", "1111101111111101", + "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);", + }, + /* end-sanitize-sh4 */ + + /* start-sanitize-sh4 */ + { "", "", "fschg", "1111001111111101", + "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_SZ);", + }, + /* end-sanitize-sh4 */ + + /* sh3e */ + { "", "", "fsqrt ", "1111nnnn01101101", + "FP_UNARY(n, sqrt);", + }, + + /* sh3e */ + { "", "", "fsub ,", "1111nnnnmmmm0001", + "FP_OP(n, -, m);", + }, + + /* sh3e */ + { "", "", "ftrc , FPUL", "1111nnnn00111101", + /* start-sanitize-sh4 */ + "if (FPSCR_PR) {", + " if (DR(n) != DR(n)) /* NaN */", + " FPUL = 0x80000000;", + " else", + " FPUL = (int)DR(n);", + "}", + "else", + /* end-sanitize-sh4 */ + "if (FR(n) != FR(n)) /* NaN */", + " FPUL = 0x80000000;", + "else", + " FPUL = (int)FR(n);", + }, + + /* start-sanitize-sh4 */ +#if 0 + /* ftst/nan would appear to have been dropped */ + /* end-sanitize-sh4 */ + /* sh3e */ + { "", "", "ftst/nan ", "1111nnnn01111101", + "SET_SR_T (isnan (FR(n)));", + }, + /* start-sanitize-sh4 */ +#endif + /* end-sanitize-sh4 */ + + /* sh3e */ + { "", "", "fsts FPUL,", "1111nnnn00001101", + "char buf[4];", + "*(int *)buf = FPUL;", + "SET_FR (n, *(float *)buf);", + }, + + { "", "n", "jmp @", "0100nnnn00101011", + "nia = R[n];", + "Delay_Slot (PC + 2);", + }, + + { "", "n", "jsr @", "0100nnnn00001011", + "PR = PC + 4;", + "nia = R[n];", + "if (~doprofile)", + " gotcall (PR, nia);", + "Delay_Slot (PC + 2);", + }, + + { "", "n", "ldc ,GBR", "0100nnnn00011110", + "GBR = R[n];", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,SR", "0100nnnn00001110", + "SET_SR (R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,VBR", "0100nnnn00101110", + "VBR = R[n];", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,SSR", "0100nnnn00111110", + "SSR = R[n];", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,SPC", "0100nnnn01001110", + "SPC = R[n];", + "/* FIXME: user mode */", + }, + /* start-sanitize-sh4 */ +#if 0 + { "", "n", "ldc ,DBR", "0100nnnn11111010", + "DBR = R[n];", + "/* FIXME: user mode */", + }, +#endif + /* end-sanitize-sh4 */ + { "", "n", "ldc ,R0_BANK", "0100nnnn10001110", + "SET_Rn_BANK (0, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R1_BANK", "0100nnnn10011110", + "SET_Rn_BANK (1, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R2_BANK", "0100nnnn10101110", + "SET_Rn_BANK (2, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R3_BANK", "0100nnnn10111110", + "SET_Rn_BANK (3, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R4_BANK", "0100nnnn11001110", + "SET_Rn_BANK (4, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R5_BANK", "0100nnnn11011110", + "SET_Rn_BANK (5, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R6_BANK", "0100nnnn11101110", + "SET_Rn_BANK (6, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc ,R7_BANK", "0100nnnn11111110", + "SET_Rn_BANK (7, R[n]);", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,GBR", "0100nnnn00010111", + "MA (1);", + "GBR = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,SR", "0100nnnn00000111", + "MA (1);", + "SET_SR (RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,VBR", "0100nnnn00100111", + "MA (1);", + "VBR = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,SSR", "0100nnnn00110111", + "MA (1);", + "SSR = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,SPC", "0100nnnn01000111", + "MA (1);", + "SPC = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + /* start-sanitize-sh4 */ #if 0 - {"divs.l ,", "0100nnnnmmmm1110", "divl(0,R[n],R[m]);"}, - {"divu.l ,", "0100nnnnmmmm1101", "divl(0,R[n],R[m]);"}, + { "", "n", "ldc.l @+,DBR", "0100nnnn11110110", + "MA (1);", + "DBR = RLAT (R[n]);", + "R[n] += 4;", + "/* FIXME: user mode */", + }, +#endif + /* end-sanitize-sh4 */ + { "", "n", "ldc.l @+,R0_BANK", "0100nnnn10000111", + "MA (1);", + "SET_Rn_BANK (0, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R1_BANK", "0100nnnn10010111", + "MA (1);", + "SET_Rn_BANK (1, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R2_BANK", "0100nnnn10100111", + "MA (1);", + "SET_Rn_BANK (2, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R3_BANK", "0100nnnn10110111", + "MA (1);", + "SET_Rn_BANK (3, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R4_BANK", "0100nnnn11000111", + "MA (1);", + "SET_Rn_BANK (4, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R5_BANK", "0100nnnn11010111", + "MA (1);", + "SET_Rn_BANK (5, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R6_BANK", "0100nnnn11100111", + "MA (1);", + "SET_Rn_BANK (6, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + { "", "n", "ldc.l @+,R7_BANK", "0100nnnn11110111", + "MA (1);", + "SET_Rn_BANK (7, RLAT (R[n]));", + "R[n] += 4;", + "/* FIXME: user mode */", + }, + + /* sh3e */ + { "", "", "lds ,FPUL", "0100nnnn01011010", + "FPUL = R[n];", + }, + /* sh3e */ + { "", "", "lds.l @+,FPUL", "0100nnnn01010110", + "MA (1);", + "FPUL = RLAT(R[n]);", + "R[n] += 4;", + }, + /* sh3e */ + { "", "", "lds ,FPSCR", "0100nnnn01101010", + "SET_FPSCR(R[n]);", + }, + /* sh3e */ + { "", "", "lds.l @+,FPSCR", "0100nnnn01100110", + "MA (1);", + "SET_FPSCR (RLAT(R[n]));", + "R[n] += 4;", + }, + + { "", "n", "lds ,MACH", "0100nnnn00001010", + "MACH = R[n];", + }, + { "", "n", "lds ,MACL", "0100nnnn00011010", + "MACL= R[n];", + }, + { "", "n", "lds ,PR", "0100nnnn00101010", + "PR = R[n];", + }, + { "", "n", "lds.l @+,MACH", "0100nnnn00000110", + "MA (1);", + "MACH = SEXT(RLAT(R[n]));", + "R[n]+=4;", + }, + { "", "n", "lds.l @+,MACL", "0100nnnn00010110", + "MA (1);", + "MACL = RLAT(R[n]);", + "R[n]+=4;", + }, + { "", "n", "lds.l @+,PR", "0100nnnn00100110", + "MA (1);", + "PR = RLAT(R[n]);", + "R[n]+=4;;", + }, + + { "", "", "ldtlb", "0000000000111000", + "/* FIXME: XXX*/ abort();", + }, + + { "", "nm", "mac.l @+,@+", "0000nnnnmmmm1111", + "trap (255,R0,memory,maskl,maskw,little_endian);", + "/* FIXME: mac.l support */", + }, + + { "", "nm", "mac.w @+,@+", "0100nnnnmmmm1111", + "macw(R0,memory,n,m);", + }, + + { "n", "", "mov #,", "1110nnnni8*1....", + "R[n] = SEXT(i);", + }, + { "n", "m", "mov ,", "0110nnnnmmmm0011", + "R[n] = R[m];", + }, + + { "0", "", "mov.b @(,GBR),R0", "11000100i8*1....", + "MA (1);", + "R0 = RSBAT (i + GBR);", + "L (0);", + }, + { "0", "m", "mov.b @(,),R0", "10000100mmmmi4*1", + "MA (1);", + "R0 = RSBAT (i + R[m]);", + "L (0);", + }, + { "n", "0m", "mov.b @(R0,),", "0000nnnnmmmm1100", + "MA (1);", + "R[n] = RSBAT (R0 + R[m]);", + "L (n);", + }, + { "n", "m", "mov.b @+,", "0110nnnnmmmm0100", + "MA (1);", + "R[n] = RSBAT (R[m]);", + "R[m] += 1;", + "L (n);", + }, + { "", "mn", "mov.b ,@", "0010nnnnmmmm0000", + "MA (1);", + "WBAT (R[n], R[m]);", + }, + { "", "0", "mov.b R0,@(,GBR)", "11000000i8*1....", + "MA (1);", + "WBAT (i + GBR, R0);", + }, + { "", "m0", "mov.b R0,@(,)", "10000000mmmmi4*1", + "MA (1);", + "WBAT (i + R[m], R0);", + }, + { "", "mn0", "mov.b ,@(R0,)", "0000nnnnmmmm0100", + "MA (1);", + "WBAT (R[n] + R0, R[m]);", + }, + { "", "nm", "mov.b ,@-", "0010nnnnmmmm0100", + "MA (1);", + "R[n] -= 1;", + "WBAT (R[n], R[m]);", + }, + { "n", "m", "mov.b @,", "0110nnnnmmmm0000", + "MA (1);", + "R[n] = RSBAT (R[m]);", + "L (n);", + }, + + { "0", "", "mov.l @(,GBR),R0", "11000110i8*4....", + "MA (1);", + "R0 = RLAT (i + GBR);", + "L (0);", + }, + { "n", "", "mov.l @(,PC),", "1101nnnni8p4....", + "MA (1);", + "R[n] = RLAT((PC & ~3) + 4 + i);", + "L (n);", + }, + { "n", "m", "mov.l @(,),", "0101nnnnmmmmi4*4", + "MA (1);", + "R[n] = RLAT (i + R[m]);", + "L (n);", + }, + { "n", "m0", "mov.l @(R0,),", "0000nnnnmmmm1110", + "MA (1);", + "R[n] = RLAT (R0 + R[m]);", + "L (n);", + }, + { "nm", "m", "mov.l @+,", "0110nnnnmmmm0110", + "MA (1);", + "R[n] = RLAT (R[m]);", + "R[m] += 4;", + "L (n);", + }, + { "n", "m", "mov.l @,", "0110nnnnmmmm0010", + "MA (1);", + "R[n] = RLAT (R[m]);", + "L (n);", + }, + { "", "0", "mov.l R0,@(,GBR)", "11000010i8*4....", + "MA (1);", + "WLAT (i + GBR, R0);", + }, + { "", "nm", "mov.l ,@(,)", "0001nnnnmmmmi4*4", + "MA (1);", + "WLAT (i + R[n], R[m]);", + }, + { "", "nm0", "mov.l ,@(R0,)", "0000nnnnmmmm0110", + "MA (1);", + "WLAT (R0 + R[n], R[m]);", + }, + { "", "nm", "mov.l ,@-", "0010nnnnmmmm0110", + "MA (1) ;", + "R[n] -= 4;", + "WLAT (R[n], R[m]);", + }, + { "", "nm", "mov.l ,@", "0010nnnnmmmm0010", + "MA (1);", + "WLAT (R[n], R[m]);", + }, + + { "0", "", "mov.w @(,GBR),R0", "11000101i8*2....", + "MA (1)", + ";R0 = RSWAT (i + GBR);", + "L (0);", + }, + { "n", "", "mov.w @(,PC),", "1001nnnni8p2....", + "MA (1);", + "R[n] = RSWAT (PC + 4 + i);", + "L (n);", + }, + { "0", "m", "mov.w @(,),R0", "10000101mmmmi4*2", + "MA (1);", + "R0 = RSWAT (i + R[m]);", + "L (0);", + }, + { "n", "m0", "mov.w @(R0,),", "0000nnnnmmmm1101", + "MA (1);", + "R[n] = RSWAT (R0 + R[m]);", + "L (n);", + }, + { "nm", "n", "mov.w @+,", "0110nnnnmmmm0101", + "MA (1);", + "R[n] = RSWAT (R[m]);", + "R[m] += 2;", + "L (n);", + }, + { "n", "m", "mov.w @,", "0110nnnnmmmm0001", + "MA (1);", + "R[n] = RSWAT (R[m]);", + "L (n);", + }, + { "", "0", "mov.w R0,@(,GBR)", "11000001i8*2....", + "MA (1);", + "WWAT (i + GBR, R0);", + }, + { "", "0m", "mov.w R0,@(,)", "10000001mmmmi4*2", + "MA (1);", + "WWAT (i + R[m], R0);", + }, + { "", "m0n", "mov.w ,@(R0,)", "0000nnnnmmmm0101", + "MA (1);", + "WWAT (R0 + R[n], R[m]);", + }, + { "n", "mn", "mov.w ,@-", "0010nnnnmmmm0101", + "MA (1);", + "R[n] -= 2;", + "WWAT (R[n], R[m]);", + }, + { "", "nm", "mov.w ,@", "0010nnnnmmmm0001", + "MA (1);", + "WWAT (R[n], R[m]);", + }, + + { "0", "", "mova @(,PC),R0", "11000111i8p4....", + "R0 = ((i + 4 + PC) & ~0x3);", + }, + + /* start-sanitize-sh4 */ + { "0", "", "movca.l @R0, ", "0000nnnn11000011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + /* end-sanitize-sh4 */ + + { "n", "", "movt ", "0000nnnn00101001", + "R[n] = T;", + }, + + { "", "mn", "mul.l ,", "0000nnnnmmmm0111", + "MACL = ((int)R[n]) * ((int)R[m]);", + }, +#if 0 + { "", "nm", "mul.l ,", "0000nnnnmmmm0111", + "MACL = R[n] * R[m];", + }, #endif -/* start-sanitize-sh3e */ - {"", "", "fmov.s @,", "1111nnnnmmmm1000", "*(int *)buf = RLAT(R[m]);F[n] = *(float *)buf;"}, - {"", "", "fmov.s ,@", "1111nnnnmmmm1010", "*(float *)buf = F[m]; WLAT(R[n], *(int *)buf);"}, - {"", "", "fmov.s @+,", "1111nnnnmmmm1001", "*(int *)buf = RLAT(R[m]); F[n] = *(float *)buf; R[m] += 4;"}, - {"", "", "fmov.s ,@-", "1111nnnnmmmm1011", "R[n] -= 4; *(float *)buf = F[m]; WLAT(R[n], *(int *)buf);"}, - {"", "", "fmov.s @(R0,),", "1111nnnnmmmm0110", "*(int *)buf = RLAT((R[0]+R[m]));F[n] = *(float *)buf;"}, - {"", "", "fmov.s ,@(R0,)", "1111nnnnmmmm0111", "*(float *)buf = F[m]; WLAT((R[0]+R[n]), *(int *)buf);"}, - {"", "", "fmov ,", "1111nnnnmmmm1100", "F[n] = F[m];"}, - {"", "", "fldi0 ", "1111nnnn10001101", "F[n] = (float)0.0;"}, - {"", "", "fldi1 ", "1111nnnn10011101", "F[n] = (float)1.0;"}, - {"", "", "fadd ,", "1111nnnnmmmm0000","F[n] = F[n] + F[m];"}, - {"", "", "fsub ,", "1111nnnnmmmm0001","F[n] = F[n] - F[m];"}, - {"", "", "fmul ,", "1111nnnnmmmm0010","F[n] = F[n] * F[m];"}, - {"", "", "fdiv ,", "1111nnnnmmmm0011","F[n] = F[n] / F[m];"}, - {"", "", "fmac ,,", "1111nnnnmmmm1110", "F[n] = F[m] * F[0] + F[n];"}, - {"", "", "fcmp/eq ,", "1111nnnnmmmm0100", "T = F[n] == F[m] ? 1 : 0;"}, - {"", "", "fcmp/gt ,", "1111nnnnmmmm0101", "T = F[n] > F[m] ? 1 : 0;"}, - {"", "", "fneg ", "1111nnnn01001101", "F[n] = -F[n];"}, - {"", "", "fabs ", "1111nnnn01011101", "F[n] = fabs (F[n]);"}, - {"", "", "fsqrt ", "1111nnnn01101101", "F[n] = sqrt (F[n]);"}, - {"", "", "float FPUL,", "1111nnnn00101101", "F[n] = (float)FPUL;"}, - {"", "", "ftrc , FPUL", "1111nnnn00111101", "if (F[n] != F[n]) /* NaN */ FPUL = 0x80000000; else FPUL = (int)F[n];"}, - {"", "", "ftst/nan ", "1111nnnn01111101", "T = isnan (F[n]);"}, - {"", "", "fsts FPUL,", "1111nnnn00001101", "*(int *)buf = FPUL; F[n] = *(float *)buf;"}, - {"", "", "flds ,FPUL", "1111nnnn00011101", "*(float *)buf = F[n]; FPUL = *(int *)buf;"}, - {"", "", "lds ,FPUL", "0100nnnn01011010", "FPUL = R[n];"}, - {"", "", "sts FPUL,", "0000nnnn01011010", "R[n] = FPUL;"}, - {"", "", "lds ,FPSCR", "0100nnnn01101010", "*(int *)buf = R[n]; FPSCR = *(float *)buf;"}, - {"", "", "sts FPSCR,", "0000nnnn01101010", "*(float *)buf = FPSCR; R[n] = *(int *)buf;"}, - {"","","lds.l @+,FPUL", "0100nnnn01010110", "FPUL = RLAT(R[n]);R[n]+=4;"}, - {"","","lds.l @+,FPSCR", "0100nnnn01100110", "*(int *)buf = RLAT(R[n]); FPSCR = *(float *)buf; R[n]+=4;"}, - {"","","sts.l FPUL,@-", "0100nnnn01010010", "R[n]-=4;WLAT(R[n],FPUL);"}, - {"","","sts.l FPSCR,@-", "0100nnnn01100010", "R[n]-=4;*(float *)buf = FPSCR; WLAT(R[n],*(int *)buf);"}, -/* end-sanitize-sh3e */ + /* muls.w - see muls */ + { "", "mn", "muls ,", "0010nnnnmmmm1111", + "MACL = ((int)(short)R[n]) * ((int)(short)R[m]);", + }, + + /* mulu.w - see mulu */ + { "", "mn", "mulu ,", "0010nnnnmmmm1110", + "MACL = (((unsigned int)(unsigned short)R[n])", + " * ((unsigned int)(unsigned short)R[m]));", + }, + + { "n", "m", "neg ,", "0110nnnnmmmm1011", + "R[n] = - R[m];", + }, + + { "n", "m", "negc ,", "0110nnnnmmmm1010", + "ult = -T;", + "SET_SR_T (ult > 0);", + "R[n] = ult - R[m];", + "SET_SR_T (T || (R[n] > ult));", + }, + + { "", "", "nop", "0000000000001001", + "/* nop */", + }, + + { "n", "m", "not ,", "0110nnnnmmmm0111", + "R[n] = ~R[m];", + }, + + /* start-sanitize-sh4 */ + { "0", "", "ocbi @", "0000nnnn10010011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + /* end-sanitize-sh4 */ + + /* start-sanitize-sh4 */ + { "0", "", "ocbp @", "0000nnnn10100011", + "/* FIXME: Not implemented */", + "saved_state.asregs.exception = SIGILL;", + }, + /* end-sanitize-sh4 */ + + /* start-sanitize-sh4 */ + { "", "n", "ocbwb @", "0000nnnn10110011", + "RSBAT (R[n]); /* Take exceptions like byte load. */", + "/* FIXME: Cache not implemented */", + }, + /* end-sanitize-sh4 */ + + { "0", "", "or #,R0", "11001011i8*1....", + "R0 |= i;", + }, + { "n", "m", "or ,", "0010nnnnmmmm1011", + "R[n] |= R[m];", + }, + { "", "0", "or.b #,@(R0,GBR)", "11001111i8*1....", + "MA (1);", + "WBAT (R0 + GBR, (RBAT (R0 + GBR) | i));", + }, + + { "", "n", "pref @", "0000nnnn10000011", + "/* Except for the effect on the cache - which is not simulated -", + " this is like a nop. */", + }, + + { "n", "n", "rotcl ", "0100nnnn00100100", + "ult = R[n] < 0;", + "R[n] = (R[n] << 1) | T;", + "SET_SR_T (ult);", + }, + + { "n", "n", "rotcr ", "0100nnnn00100101", + "ult = R[n] & 1;", + "R[n] = (UR[n] >> 1) | (T << 31);", + "SET_SR_T (ult);", + }, + + { "n", "n", "rotl ", "0100nnnn00000100", + "SET_SR_T (R[n] < 0);", + "R[n] <<= 1;", + "R[n] |= T;", + }, + + { "n", "n", "rotr ", "0100nnnn00000101", + "SET_SR_T (R[n] & 1);", + "R[n] = UR[n] >> 1;", + "R[n] |= (T << 31);", + }, + + { "", "", "rte", "0000000000101011", +#if 0 + /* SH-[12] */ + "int tmp = PC;", + "nia = RLAT (R[15]) + 2;", + "R[15] += 4;", + "SET_SR (RLAT (R[15]) & 0x3f3);", + "R[15] += 4;", + "Delay_Slot (PC + 2);", +#else + "nia = SPC;", + "SET_SR (SSR);", + "Delay_Slot (PC + 2);", +#endif + }, + + { "", "", "rts", "0000000000001011", + "nia = PR;", + "Delay_Slot (PC + 2);", + }, + + { "", "", "sets", "0000000001011000", + "SET_SR_S (1);", + }, + + { "", "", "sett", "0000000000011000", + "SET_SR_T (1);", + }, + + { "n", "mn", "shad ,", "0100nnnnmmmm1100", + "R[n] = (R[m] < 0) ? (R[n] >> ((-R[m])&0x1f)) : (R[n] << (R[m] & 0x1f));", + }, + + { "n", "n", "shal ", "0100nnnn00100000", + "SET_SR_T (R[n] < 0);", + "R[n] <<= 1;", + }, + + { "n", "n", "shar ", "0100nnnn00100001", + "SET_SR_T (R[n] & 1);", + "R[n] = R[n] >> 1;", + }, + + { "n", "mn", "shld ,", "0100nnnnmmmm1101", + "R[n] = (R[m] < 0) ? (UR[n] >> ((-R[m])&0x1f)): (R[n] << (R[m] & 0x1f));", + }, + + { "n", "n", "shll ", "0100nnnn00000000", + "SET_SR_T (R[n] < 0);", + "R[n] <<= 1;", + }, + + { "n", "n", "shll2 ", "0100nnnn00001000", + "R[n] <<= 2;", + }, + { "n", "n", "shll8 ", "0100nnnn00011000", + "R[n] <<= 8;", + }, + { "n", "n", "shll16 ", "0100nnnn00101000", + "R[n] <<= 16;", + }, + + { "n", "n", "shlr ", "0100nnnn00000001", + "SET_SR_T (R[n] & 1);", + "R[n] = UR[n] >> 1;", + }, + + { "n", "n", "shlr2 ", "0100nnnn00001001", + "R[n] = UR[n] >> 2;", + }, + { "n", "n", "shlr8 ", "0100nnnn00011001", + "R[n] = UR[n] >> 8;", + }, + { "n", "n", "shlr16 ", "0100nnnn00101001", + "R[n] = UR[n] >> 16;", + }, + + { "", "", "sleep", "0000000000011011", + "trap (0xc3, R0, memory, maskl, maskw, little_endian);", + "nia = PC;", + }, + + { "n", "", "stc GBR,", "0000nnnn00010010", + "R[n] = GBR;", + }, + { "n", "", "stc SR,", "0000nnnn00000010", + "R[n] = GET_SR ();", + }, + { "n", "", "stc VBR,", "0000nnnn00100010", + "R[n] = VBR;", + }, + { "n", "", "stc SSR,", "0000nnnn00110010", + "R[n] = SSR;", + }, + { "n", "", "stc SPC,", "0000nnnn01000010", + "R[n] = SPC;", + }, + /* start-sanitize-sh4 */ +#if 0 + { "n", "", "stc SGR,", "0000nnnn00111010", + "R[n] = SGR;", + }, + { "n", "", "stc DBR,", "0000nnnn11111010", + "R[n] = DBR;", + }, +#endif + /* end-sanitize-sh4 */ + { "n", "", "stc R0_BANK,", "0000nnnn10000010", + "R[n] = Rn_BANK (0);", + }, + { "n", "", "stc R1_BANK,", "0000nnnn10010010", + "R[n] = Rn_BANK (1);", + }, + { "n", "", "stc R2_BANK,", "0000nnnn10100010", + "R[n] = Rn_BANK (2);", + }, + { "n", "", "stc R3_BANK,", "0000nnnn10110010", + "R[n] = Rn_BANK (3);", + }, + { "n", "", "stc R4_BANK,", "0000nnnn11000010", + "R[n] = Rn_BANK (4);", + }, + { "n", "", "stc R5_BANK,", "0000nnnn11010010", + "R[n] = Rn_BANK (5);", + }, + { "n", "", "stc R6_BANK,", "0000nnnn11100010", + "R[n] = Rn_BANK (6);", + }, + { "n", "", "stc R7_BANK,", "0000nnnn11110010", + "R[n] = Rn_BANK (7);", + }, + { "n", "n", "stc.l GBR,@-", "0100nnnn00010011", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], GBR);;", + }, + { "n", "n", "stc.l SR,@-", "0100nnnn00000011", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], GET_SR());", + }, + { "n", "n", "stc.l VBR,@-", "0100nnnn00100011", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], VBR);", + }, + { "n", "n", "stc.l SSR,@-", "0100nnnn00110011", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], SSR);", + }, + { "n", "n", "stc.l SPC,@-", "0100nnnn01000011", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], SPC);", + }, + /* start-sanitize-sh4 */ +#if 0 + { "n", "n", "stc.l SGR,@-", "0100nnnn00110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], SGR);", + }, + { "n", "n", "stc.l DBR,@-", "0100nnnn11110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], DBR);", + }, +#endif + /* end-sanitize-sh4 */ + { "n", "", "stc R0_BANK,@-", "0100nnnn10000010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (0));", + }, + { "n", "", "stc R1_BANK,@-", "0100nnnn10010010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (1));", + }, + { "n", "", "stc R2_BANK,@-", "0100nnnn10100010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (2));", + }, + { "n", "", "stc R3_BANK,@-", "0100nnnn10110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (3));", + }, + { "n", "", "stc R4_BANK,@-", "0100nnnn11000010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (4));", + }, + { "n", "", "stc R5_BANK,@-", "0100nnnn11010010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (5));", + }, + { "n", "", "stc R6_BANK,@-", "0100nnnn11100010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (6));", + }, + { "n", "", "stc R7_BANK,@-", "0100nnnn11110010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], Rn_BANK (7));", + }, + + /* sh3e */ + { "", "", "sts FPUL,", "0000nnnn01011010", + "R[n] = FPUL;", + }, + /* sh3e */ + { "", "", "sts.l FPUL,@-", "0100nnnn01010010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], FPUL);", + }, + /* sh3e */ + { "", "", "sts FPSCR,", "0000nnnn01101010", + "R[n] = GET_FPSCR ();", + }, + /* sh3e */ + { "", "", "sts.l FPSCR,@-", "0100nnnn01100010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], GET_FPSCR ());", + }, + + { "n", "", "sts MACH,", "0000nnnn00001010", + "R[n] = MACH;", + }, + { "n", "", "sts MACL,", "0000nnnn00011010", + "R[n] = MACL;", + }, + { "n", "", "sts PR,", "0000nnnn00101010", + "R[n] = PR;", + }, + { "n", "n", "sts.l MACH,@-", "0100nnnn00000010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], MACH);", + }, + { "n", "n", "sts.l MACL,@-", "0100nnnn00010010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], MACL);", + }, + { "n", "n", "sts.l PR,@-", "0100nnnn00100010", + "MA (1);", + "R[n] -= 4;", + "WLAT (R[n], PR);", + }, + + { "n", "nm", "sub ,", "0011nnnnmmmm1000", + "R[n] -= R[m];", + }, + + { "n", "nm", "subc ,", "0011nnnnmmmm1010", + "ult = R[n] - T;", + "SET_SR_T (ult > R[n]);", + "R[n] = ult - R[m];", + "SET_SR_T (T || (R[n] > ult));", + }, + + { "n", "nm", "subv ,", "0011nnnnmmmm1011", + "ult = R[n] - R[m];", + "SET_SR_T (((R[n] ^ R[m]) & (ult ^ R[n])) >> 31);", + "R[n] = ult;", + }, + + { "n", "nm", "swap.b ,", "0110nnnnmmmm1000", + "R[n] = ((R[m] & 0xffff0000)", + " | ((R[m] << 8) & 0xff00)", + " | ((R[m] >> 8) & 0x00ff));", + }, + { "n", "nm", "swap.w ,", "0110nnnnmmmm1001", + "R[n] = (((R[m] << 16) & 0xffff0000)", + " | ((R[m] >> 16) & 0x00ffff));", + }, + + { "", "n", "tas.b @", "0100nnnn00011011", + "MA (1);", + "ult = RBAT(R[n]);", + "SET_SR_T (ult == 0);", + "WBAT(R[n],ult|0x80);", + }, + + { "0", "", "trapa #", "11000011i8*1....", +#if 0 + /* SH-[12] */ + "long imm = 0xff & i;", + "if (i==0xc3)", + " PC-=2;", + "if (i<20||i==34||i==0xc3)", + " trap(i,R,memory,maskl,maskw,little_endian);", + "else {", + " R[15]-=4;", + " WLAT(R[15],GET_SR());", + " R[15]-=4;", + " WLAT(R[15],PC+2);", + " PC=RLAT(VBR+(imm<<2))-2;", + "}", +#else + "if (i == 0xc3)", + " {", + " nia = PC;", + " trap (i, R, memory, maskl, maskw, little_endian);", + " }", + "else if (i < 20 || i==34 || i==0xc3)", + " trap (i, R, memory, maskl, maskw, little_endian);", + "else if (!SR_BL) {", + " /* FIXME: TRA = (imm << 2); */", + " SSR = GET_SR();", + " SPC = PC + 2;", + " SET_SR (GET_SR() | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);", + " /* FIXME: EXPEVT = 0x00000160; */", + " nia = VBR + 0x00000100;", + "}", +#endif + }, + + { "", "mn", "tst ,", "0010nnnnmmmm1000", + "SET_SR_T ((R[n] & R[m]) == 0);", + }, + { "", "0", "tst #,R0", "11001000i8*1....", + "SET_SR_T ((R0 & i) == 0);", + }, + { "", "0", "tst.b #,@(R0,GBR)", "11001100i8*1....", + "MA (1);", + "SET_SR_T ((RBAT (GBR+R0) & i) == 0);", + }, + + { "", "0", "xor #,R0", "11001010i8*1....", + "R0 ^= i;", + }, + { "n", "mn", "xor ,", "0010nnnnmmmm1010", + "R[n] ^= R[m];", + }, + { "", "0", "xor.b #,@(R0,GBR)", "11001110i8*1....", + "MA (1);", + "ult = RBAT (GBR+R0);", + "ult ^= i;", + "WBAT (GBR + R0, ult);", + }, + + { "n", "nm", "xtrct ,", "0010nnnnmmmm1101", + "R[n] = (((R[n] >> 16) & 0xffff)", + " | ((R[m] << 16) & 0xffff0000));", + }, + + /* start-sanitize-sh4 */ +#if 0 + { "divs.l ,", "0100nnnnmmmm1110", + "divl(0,R[n],R[m]);", + }, + { "divu.l ,", "0100nnnnmmmm1101", + "divl(0,R[n],R[m]);", + }, +#endif + /* end-sanitize-sh4 */ {0, 0}}; @@ -655,10 +1763,7 @@ gensim () int j; printf ("{\n"); -/* start-sanitize-sh3e */ - printf("char buf[4];\n"); -/* end-sanitize-sh3e */ - printf ("switch (jump_table[iword]) {\n"); + printf (" switch (jump_table[iword]) {\n"); for (p = tab; p->name; p++) { @@ -668,10 +1773,10 @@ gensim () char *s = p->code; - printf ("/* %s %s */\n", p->name, p->code); - printf ("case %d: \n", p->index); + printf (" /* %s %s */\n", p->name, p->code); + printf (" case %d: \n", p->index); - printf ("{\n"); + printf (" {\n"); while (*s) { switch (*s) @@ -682,19 +1787,19 @@ gensim () s += 4; break; case 'n': - printf ("int n = (iword >>8) & 0xf;\n"); + printf (" int n = (iword >>8) & 0xf;\n"); needn = 1; s += 4; break; case 'm': - printf ("int m = (iword >>4) & 0xf;\n"); + printf (" int m = (iword >>4) & 0xf;\n"); needm = 1; s += 4; break; case 'i': - printf ("int i = (iword & 0x"); + printf (" int i = (iword & 0x"); switch (s[1]) { @@ -729,46 +1834,58 @@ gensim () } if (sextbit > 0) { - printf ("i = (i ^ (1<<%d))-(1<<%d);\n", sextbit - 1, sextbit - 1); + printf (" i = (i ^ (1<<%d))-(1<<%d);\n", + sextbit - 1, sextbit - 1); } + if (needm && needn) - printf("TB(m,n);"); + printf (" TB(m,n);\n"); else if (needm) - printf("TL(m);"); + printf (" TL(m);\n"); else if (needn) - printf("TL(n);"); - for (j = 0; j < 10; j++) + printf (" TL(n);\n"); + + { + /* Do the refs */ + char *r; + for (r = p->refs; *r; r++) + { + if (*r == '0') printf(" CREF(0);\n"); + if (*r == 'n') printf(" CREF(n);\n"); + if (*r == 'm') printf(" CREF(m);\n"); + } + } + + printf (" {\n"); + for (j = 0; j < MAX_NR_STUFF; j++) { if (p->stuff[j]) { - printf ("%s\n", p->stuff[j]); + printf (" %s\n", p->stuff[j]); } } + printf (" }\n"); - { - /* Do the defs and refs */ + /* Do the defs */ char *r; - for (r = p->refs; *r; r++) { - if (*r == '0') printf("CREF(0);\n"); - if (*r == 'n') printf("CREF(n);\n"); - if (*r == 'm') printf("CREF(m);\n"); - - } for (r = p->defs; *r; r++) { - if (*r == '0') printf("CDEF(0);\n"); - if (*r == 'n') printf("CDEF(n);\n"); - if (*r == 'm') printf("CDEF(m);\n"); - - } - + if (*r == '0') printf(" CDEF(0);\n"); + if (*r == 'n') printf(" CDEF(n);\n"); + if (*r == 'm') printf(" CDEF(m);\n"); + } } - printf ("break;\n"); - printf ("}\n"); + + printf (" break;\n"); + printf (" }\n"); } - printf("default:\n{\nsaved_state.asregs.exception = SIGILL;\n}\n"); - printf ("}\n}\n"); + printf (" default:\n"); + printf (" {\n"); + printf (" saved_state.asregs.exception = SIGILL;\n"); + printf (" }\n"); + printf (" }\n"); + printf ("}\n"); } @@ -799,6 +1916,22 @@ main (ac, av) int ac; char **av; { + /* verify the table before anything else */ + { + op *p; + for (p = tab; p->name; p++) + { + /* check that the code field contains 16 bits */ + if (strlen (p->code) != 16) + { + fprintf (stderr, "Code `%s' length wrong (%d) for `%s'\n", + p->code, strlen (p->code), p->name); + abort (); + } + } + } + + /* now generate the requested data */ if (ac > 1) { if (strcmp (av[1], "-t") == 0) diff --git a/sim/sh/interp.c b/sim/sh/interp.c index da50d2480e..5f61244511 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -56,6 +56,92 @@ #define DEFINE_TABLE #define DISASSEMBLER_TABLE +typedef union +{ + + struct + { + + int regs[16]; + int pc; + int pr; + + int gbr; + int vbr; + int mach; + int macl; + + int sr; + + int fpul; + + int fpscr; + + /* sh3e */ + union fregs_u + { + float f[16]; + double d[8]; + int i[16]; + } + /* start-sanitize-sh4 */ +#if 1 + fregs[2]; +#else + /* end-sanitize-sh4 */ + fregs; + /* start-sanitize-sh4 */ +#endif + /* end-sanitize-sh4 */ + + int ssr; + int spc; + /* sh3 */ + int bank[2][8]; + + int ticks; + int stalls; + int memstalls; + int cycles; + int insts; + + int prevlock; + int thislock; + int exception; + + int end_of_registers; + + int msize; +#define PROFILE_FREQ 1 +#define PROFILE_SHIFT 2 + int profile; + unsigned short *profile_hist; + unsigned char *memory; + } + asregs; + int asints[28]; +} saved_state_type; + +saved_state_type saved_state; + + +/* These variables are at file scope so that functions other than + sim_resume can use the fetch/store macros */ + +static int target_little_endian; +static int host_little_endian; + +#if 1 +static int maskl = ~0; +static int maskw = ~0; +#endif + +static SIM_OPEN_KIND sim_kind; +static char *myname; + + +/* Short hand definitions of the registers */ + #define SBIT(x) ((x)&sbit) #define R0 saved_state.asregs.regs[0] #define Rn saved_state.asregs.regs[n] @@ -70,21 +156,118 @@ #define SPC saved_state.asregs.spc #define MACH saved_state.asregs.mach #define MACL saved_state.asregs.macl -#define M saved_state.asregs.sr.bits.m -#define Q saved_state.asregs.sr.bits.q -#define S saved_state.asregs.sr.bits.s -#define FPSCR saved_state.asregs.fpscr #define FPUL saved_state.asregs.fpul -#define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word) -#define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;} - #define PC pc -#define C cycles -static SIM_OPEN_KIND sim_kind; -static char *myname; -static int little_endian_p; + + +/* Alternate bank of registers r0-r6 */ + +/* Note: code controling SR handles flips between BANK0 and BANK1 */ +#define Rn_BANK(n) (saved_state.asregs.bank[!SR_RB][(n)]) +#define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[!SR_RB][(n)] = (EXP); } while (0) + + +/* Manipulate SR */ + +#define SR_MASK_M (1 << 9) +#define SR_MASK_Q (1 << 8) +#define SR_MASK_I (0xf << 4) +#define SR_MASK_S (1 << 1) +#define SR_MASK_T (1 << 0) + +#define SR_MASK_BL (1 << 28) +#define SR_MASK_RB (1 << 29) +#define SR_MASK_MD (1 << 30) + +#define M ((saved_state.asregs.sr & SR_MASK_M) != 0) +#define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0) +#define S ((saved_state.asregs.sr & SR_MASK_S) != 0) +#define T ((saved_state.asregs.sr & SR_MASK_T) != 0) + +#define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0) +#define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0) +#define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0) + +/* Note: don't use this for privileged bits */ +#define SET_SR_BIT(EXP, BIT) \ +do { \ + if ((EXP) & 1) \ + saved_state.asregs.sr |= (BIT); \ + else \ + saved_state.asregs.sr &= ~(BIT); \ +} while (0) + +#define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M) +#define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q) +#define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S) +#define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T) + +#define GET_SR() (saved_state.asregs.sr - 0) +#define SET_SR(x) set_sr (x) +static void +set_sr (new_sr) + int new_sr; +{ + /* do we need to swap banks */ + int old_gpr = (SR_MD ? !SR_RB : 0); + int new_gpr = ((new_sr & SR_MASK_MD) + ? (new_sr & SR_MASK_RB) == 0 + : 0); + if (old_gpr != new_gpr) + { + int i; + for (i = 0; i < 8; i++) + { + saved_state.asregs.bank[old_gpr][i] = saved_state.asregs.regs[i]; + saved_state.asregs.regs[i] = saved_state.asregs.bank[new_gpr][i]; + } + } +} + + +/* Manipulate FPSCR */ + +/* start-sanitize-sh4 */ +#if 1 +#define FPSCR_MASK_FR (1 << 21) +#define FPSCR_MASK_SZ (1 << 20) +#define FPSCR_MASK_PR (1 << 19) + +#define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0) +#define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0) +#define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0) + +static void +set_fpscr1 (x) + int x; +{ + int old = saved_state.asregs.fpscr; + saved_state.asregs.fpscr = (x); + /* swap the floating point register banks */ + if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR) + { + union fregs_u tmpf = saved_state.asregs.fregs[0]; + saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1]; + saved_state.asregs.fregs[1] = tmpf; + } +} + +#define GET_FPSCR() (saved_state.asregs.fpscr) +#define SET_FPSCR(x) \ +do { \ + set_fpscr1 (x); \ +} while (0) +#else +/* end-sanitize-sh4 */ +#define set_fpscr1(x) +#define SET_FPSCR(x) (saved_state.asregs.fpscr = (x)) +#define GET_FPSCR() (saved_state.asregs.fpscr) +/* start-sanitize-sh4 */ +#endif +/* end-sanitize-sh4 */ + int fail () @@ -92,6 +275,21 @@ fail () abort (); } +int +special_address (addr, bits_written, data) + void *addr; + int bits_written, data; +{ + if ((unsigned) addr >> 24 == 0xf0 && bits_written == 32 && (data & 1) == 0) + /* This invalidates (if not associative) or might invalidate + (if assiciative) an instruction cache line. This is used for + trampolines. Since we don't simulate the cache, this is a no-op + as far as the simulator is concerned. */ + return 1; + /* We can't do anything useful with the other stuff, so fail. */ + return 0; +} + /* This function exists solely for the purpose of setting a breakpoint to catch simulated bus errors when running the simulator under GDB. */ @@ -100,8 +298,18 @@ bp_holder () { } -#define BUSERROR(addr, mask) \ - if (addr & ~mask) { saved_state.asregs.exception = SIGBUS; bp_holder (); } +/* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume + being implemented by ../common/sim_resume.c and the below should + make a call to sim_engine_halt */ + +#define BUSERROR(addr, mask, bits_written, data) \ + if (addr & ~mask) \ + { \ + if (special_address (addr, bits_written, data)) \ + return; \ + saved_state.asregs.exception = SIGBUS; \ + bp_holder (); \ + } /* Define this to enable register lifetime checking. The compiler generates "add #0,rn" insns to mark registers as invalid, @@ -128,76 +336,122 @@ static int IOMEM PARAMS ((int addr, int write, int value)); static host_callback *callback; -/* These variables are at file scope so that functions other than - sim_resume can use the fetch/store macros */ - -static int little_endian; -#if 1 -static int maskl = ~0; -static int maskw = ~0; -#endif -typedef union -{ - struct - { +/* Floating point registers */ - int regs[16]; - int pc; - int pr; +/* start-sanitize-sh4 */ +#if 1 - int gbr; - int vbr; - int mach; - int macl; +#define DR(n) (get_dr (n)) +static double +get_dr (n) + int n; +{ + n = (n & ~1); + if (host_little_endian) + { + union + { + int i[2]; + double d; + } dr; + dr.i[1] = saved_state.asregs.fregs[0].i[n + 0]; + dr.i[0] = saved_state.asregs.fregs[0].i[n + 1]; + return dr.d; + } + else + return (saved_state.asregs.fregs[0].d[n >> 1]); +} - union +#define SET_DR(n, EXP) set_dr ((n), (EXP)) +static void +set_dr (n, exp) + int n; + double exp; +{ + n = (n & ~1); + if (host_little_endian) + { + union { - struct - { - unsigned int d0:22; - unsigned int m:1; - unsigned int q:1; - unsigned int i:4; - unsigned int d1:2; - unsigned int s:1; - unsigned int t:1; - } - bits; - int word; - } - sr; + int i[2]; + double d; + } dr; + dr.d = exp; + saved_state.asregs.fregs[0].i[n + 0] = dr.i[1]; + saved_state.asregs.fregs[0].i[n + 1] = dr.i[0]; + } + else + saved_state.asregs.fregs[0].d[n >> 1] = exp; +} - int fpul; - float fpscr; - float fregs[16]; +#define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP)) +#define FI(n) (saved_state.asregs.fregs[0].i[(n)]) + +#define FR(n) (saved_state.asregs.fregs[0].f[(n)]) +#define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP)) + +#define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e)) +#define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f]) +#define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP)) + + +#define FP_OP(n, OP, m) \ +{ \ + if (FPSCR_PR) \ + { \ + if (((n) & 1) || ((m) & 1)) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_DR(n, (DR(n) OP DR(m))); \ + } \ + else \ + SET_FR(n, (FR(n) OP FR(m))); \ +} while (0) + +#define FP_UNARY(n, OP) \ +{ \ + if (FPSCR_PR) \ + { \ + if ((n) & 1) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_DR(n, (OP (DR(n)))); \ + } \ + else \ + SET_FR(n, (OP (FR(n)))); \ +} while (0) + +#define FP_CMP(n, OP, m) \ +{ \ + if (FPSCR_PR) \ + { \ + if (((n) & 1) || ((m) & 1)) \ + saved_state.asregs.exception = SIGILL; \ + else \ + SET_SR_T (DR(n) OP DR(m)); \ + } \ + else \ + SET_SR_T (FR(n) OP FR(m)); \ +} while (0) - int ssr; - int spc; - int bregs[16]; +#else +/* end-sanitize-sh4 */ +#define FI(n) (saved_state.asregs.fregs.i[(n)]) +#define FR(n) (saved_state.asregs.fregs.f[(n)]) - int ticks; - int stalls; - int memstalls; - int cycles; - int insts; +#define SET_FI(n,EXP) (saved_state.asregs.fregs.i[(n)] = (EXP)) +#define SET_FR(n,EXP) (saved_state.asregs.fregs.f[(n)] = (EXP)) + +#define FP_OP(n, OP, m) (SET_FR(n, (FR(n) OP FR(m)))) +#define FP_UNARY(n, OP) (SET_FR(n, (OP (FR(n))))) +#define FP_CMP(n, OP, m) SET_SR_T(FR(n) OP FR(m)) +/* start-sanitize-sh4 */ +#endif +/* end-sanitize-sh4 */ - int prevlock; - int thislock; - int exception; - int msize; -#define PROFILE_FREQ 1 -#define PROFILE_SHIFT 2 - int profile; - unsigned short *profile_hist; - unsigned char *memory; - } - asregs; - int asints[28]; -} saved_state_type; -saved_state_type saved_state; static void INLINE wlat_little (memory, x, value, maskl) @@ -205,7 +459,7 @@ wlat_little (memory, x, value, maskl) { int v = value; unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, 32, v); p[3] = v >> 24; p[2] = v >> 16; p[1] = v >> 8; @@ -218,7 +472,7 @@ wwat_little (memory, x, value, maskw) { int v = value; unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, 16, v); p[1] = v >> 8; p[0] = v; @@ -231,7 +485,7 @@ wbat_any (memory, x, value, maskb) unsigned char *p = memory + (x & maskb); if (x > 0x5000000) IOMEM (x, 1, value); - BUSERROR(x, maskb); + BUSERROR(x, maskb, 8, value); p[0] = value; } @@ -242,7 +496,7 @@ wlat_big (memory, x, value, maskl) { int v = value; unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, 32, v); p[0] = v >> 24; p[1] = v >> 16; @@ -256,7 +510,7 @@ wwat_big (memory, x, value, maskw) { int v = value; unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, 16, v); p[0] = v >> 8; p[1] = v; @@ -267,7 +521,7 @@ wbat_big (memory, x, value, maskb) unsigned char *memory; { unsigned char *p = memory + (x & maskb); - BUSERROR(x, maskb); + BUSERROR(x, maskb, 8, value); if (x > 0x5000000) IOMEM (x, 1, value); @@ -281,7 +535,7 @@ rlat_little (memory, x, maskl) unsigned char *memory; { unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); + BUSERROR(x, maskl, -32, -1); return (p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]; } @@ -291,7 +545,7 @@ rwat_little (memory, x, maskw) unsigned char *memory; { unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, -16, -1); return (p[1] << 8) | p[0]; } @@ -301,7 +555,7 @@ rbat_any (memory, x, maskb) unsigned char *memory; { unsigned char *p = memory + ((x) & maskb); - BUSERROR(x, maskb); + BUSERROR(x, maskb, -8, -1); return p[0]; } @@ -311,7 +565,6 @@ rlat_big (memory, x, maskl) unsigned char *memory; { unsigned char *p = memory + ((x) & maskl); - BUSERROR(x, maskl); return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]; } @@ -321,7 +574,7 @@ rwat_big (memory, x, maskw) unsigned char *memory; { unsigned char *p = memory + ((x) & maskw); - BUSERROR(x, maskw); + BUSERROR(x, maskw, -16, -1); return (p[0] << 8) | p[1]; } @@ -337,12 +590,72 @@ rwat_big (memory, x, maskw) #define RSWAT(x) ((short)(RWAT(x))) #define RSBAT(x) (SEXT(RBAT(x))) -#define MA() ((pc & 3) != 0 ? ++memstalls : 0) +/* start-sanitize-sh4 */ +#define RDAT(x, n) (do_rdat (memory, (x), (n), (little_endian))) +static int +do_rdat (memory, x, n, little_endian) + char *memory; + int x; + int n; + int little_endian; +{ + int f0; + int f1; + int i = (n & 1); + int j = (n & ~1); + if (little_endian) + { + f0 = rlat_little (memory, x + 0, maskl); + f1 = rlat_little (memory, x + 4, maskl); + } + else + { + f0 = rlat_big (memory, x + 0, maskl); + f1 = rlat_big (memory, x + 4, maskl); + } + saved_state.asregs.fregs[i].i[(j + 0)] = f0; + saved_state.asregs.fregs[i].i[(j + 1)] = f1; + return 0; +} +/* end-sanitize-sh4 */ -#define SEXT(x) (((x&0xff) ^ (~0x7f))+0x80) +/* start-sanitize-sh4 */ +#define WDAT(x, n) (do_wdat (memory, (x), (n), (little_endian))) +static int +do_wdat (memory, x, n, little_endian) + char *memory; + int x; + int n; + int little_endian; +{ + int f0; + int f1; + int i = (n & 1); + int j = (n & ~1); + f0 = saved_state.asregs.fregs[i].i[(j + 0)]; + f1 = saved_state.asregs.fregs[i].i[(j + 1)]; + if (little_endian) + { + wlat_little (memory, (x + 0), f0, maskl); + wlat_little (memory, (x + 4), f1, maskl); + } + else + { + wlat_big (memory, (x + 0), f0, maskl); + wlat_big (memory, (x + 4), f1, maskl); + } + return 0; +} +/* end-sanitize-sh4 */ + + +#define MA(n) do { memstalls += (((pc & 3) != 0) ? (n) : ((n) - 1)); } while (0) + +#define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80) +#define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800) #define SEXTW(y) ((int)((short)y)) -#define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top; +#define Delay_Slot(TEMPPC) iword = RUWAT(TEMPPC); goto top; int empty[16]; @@ -421,6 +734,7 @@ swap (memory, n) unsigned char *memory; int n; { + int little_endian = target_little_endian; WLAT (0, n); } @@ -429,6 +743,7 @@ swap16 (memory, n) unsigned char *memory; int n; { + int little_endian = target_little_endian; WWAT (0, n); } @@ -627,17 +942,17 @@ control_c (sig, code, scp, addr) } static int -div1 (R, iRn2, iRn1, T) +div1 (R, iRn2, iRn1/*, T*/) int *R; int iRn1; int iRn2; - int T; + /* int T;*/ { unsigned long tmp0; unsigned char old_q, tmp1; old_q = Q; - Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0); + SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0)); R[iRn1] <<= 1; R[iRn1] |= (unsigned long) T; @@ -653,10 +968,10 @@ div1 (R, iRn2, iRn1, T) switch (Q) { case 0: - Q = tmp1; + SET_SR_Q (tmp1); break; case 1: - Q = (unsigned char) (tmp1 == 0); + SET_SR_Q ((unsigned char) (tmp1 == 0)); break; } break; @@ -667,10 +982,10 @@ div1 (R, iRn2, iRn1, T) switch (Q) { case 0: - Q = (unsigned char) (tmp1 == 0); + SET_SR_Q ((unsigned char) (tmp1 == 0)); break; case 1: - Q = tmp1; + SET_SR_Q (tmp1); break; } break; @@ -686,10 +1001,10 @@ div1 (R, iRn2, iRn1, T) switch (Q) { case 0: - Q = tmp1; + SET_SR_Q (tmp1); break; case 1: - Q = (unsigned char) (tmp1 == 0); + SET_SR_Q ((unsigned char) (tmp1 == 0)); break; } break; @@ -700,18 +1015,19 @@ div1 (R, iRn2, iRn1, T) switch (Q) { case 0: - Q = (unsigned char) (tmp1 == 0); + SET_SR_Q ((unsigned char) (tmp1 == 0)); break; case 1: - Q = tmp1; + SET_SR_Q (tmp1); break; } break; } break; } - T = (Q == M); - return T; + /*T = (Q == M);*/ + SET_SR_T (Q == M); + /*return T;*/ } static void @@ -761,6 +1077,7 @@ macw (regs, memory, n, m) unsigned char *memory; int m, n; { + int little_endian = target_little_endian; long tempm, tempn; long prod, macl, sum; @@ -822,19 +1139,12 @@ sim_size (power) } } -static void -set_static_little_endian (x) - int x; -{ - little_endian = x; -} - static void init_pointers () { - int little_endian = little_endian_p; - - set_static_little_endian (little_endian); + host_little_endian = 0; + *(char*)&host_little_endian = 1; + host_little_endian &= 1; if (saved_state.asregs.msize != 1 << sim_memory_size) { @@ -916,17 +1226,17 @@ sim_resume (sd, step, siggnal) register int thislock; register unsigned int doprofile; register int pollcount = 0; - register int little_endian = little_endian_p; + register int little_endian = target_little_endian; int tick_start = get_now (); void (*prev) (); + void (*prev_fpe) (); extern unsigned char sh_jump_table0[]; register unsigned char *jump_table = sh_jump_table0; register int *R = &(saved_state.asregs.regs[0]); - register float *F = &(saved_state.asregs.fregs[0]); - register int T; + /*register int T;*/ register int PR; register int maskb = ((saved_state.asregs.msize - 1) & ~0); @@ -936,6 +1246,7 @@ sim_resume (sd, step, siggnal) register unsigned int sbit = ((unsigned int) 1 << 31); prev = signal (SIGINT, control_c); + prev_fpe = signal (SIGFPE, SIG_IGN); init_pointers (); @@ -952,7 +1263,7 @@ sim_resume (sd, step, siggnal) pc = saved_state.asregs.pc; PR = saved_state.asregs.pr; - T = saved_state.asregs.sr.bits.t; + /*T = GET_SR () & SR_MASK_T;*/ prevlock = saved_state.asregs.prevlock; thislock = saved_state.asregs.thislock; doprofile = saved_state.asregs.profile; @@ -966,6 +1277,7 @@ sim_resume (sd, step, siggnal) { register unsigned int iword = RUWAT (pc); register unsigned int ult; + register unsigned int nia = pc + 2; #ifndef ACE_FAST insts++; #endif @@ -974,7 +1286,7 @@ sim_resume (sd, step, siggnal) #include "code.c" - pc += 2; + pc = nia; pollcount++; if (pollcount > 1000) @@ -1025,7 +1337,8 @@ sim_resume (sd, step, siggnal) saved_state.asregs.memstalls += memstalls; saved_state.asregs.insts += insts; saved_state.asregs.pc = pc; - saved_state.asregs.sr.bits.t = T; + /* restore the T and other cached SR bits */ + SET_SR (GET_SR()); saved_state.asregs.pr = PR; saved_state.asregs.prevlock = prevlock; @@ -1036,6 +1349,7 @@ sim_resume (sd, step, siggnal) dump_profile (); } + signal (SIGFPE, prev_fpe); signal (SIGINT, prev); } @@ -1081,8 +1395,14 @@ sim_store_register (sd, rn, memory) int rn; unsigned char *memory; { + int little_endian; init_pointers (); - saved_state.asregs.regs[rn] = RLAT(0); + little_endian = target_little_endian; + if (&saved_state.asints[rn] + == &saved_state.asregs.fpscr) + set_fpscr1 (RLAT(0)); + else + saved_state.asints[rn] = RLAT(0); } void @@ -1091,8 +1411,10 @@ sim_fetch_register (sd, rn, memory) int rn; unsigned char *memory; { + int little_endian; init_pointers (); - WLAT (0, saved_state.asregs.regs[rn]); + little_endian = target_little_endian; + WLAT (0, saved_state.asints[rn]); } int @@ -1197,7 +1519,7 @@ sim_open (kind, cb, abfd, argv) callback->printf_filtered (callback, "Missing argument to `-E'.\n"); return 0; } - little_endian_p = strcmp (*p, "big") != 0; + target_little_endian = strcmp (*p, "big") != 0; } else if (isdigit (**p)) parse_and_set_memory_size (*p); @@ -1248,16 +1570,18 @@ sim_load (sd, prog, abfd, from_tty) } SIM_RC -sim_create_inferior (sd, abfd, argv, env) +sim_create_inferior (sd, prog_bfd, argv, env) SIM_DESC sd; - struct _bfd *abfd; + struct _bfd *prog_bfd; char **argv; char **env; { - if (abfd != NULL) - saved_state.asregs.pc = bfd_get_start_address (abfd); - else - saved_state.asregs.pc = 0; + /* clear the registers (retaining the PC) */ + memset (&saved_state, 0, + (char*)&saved_state.asregs.end_of_registers - (char*)&saved_state); + /* set the PC */ + if (prog_bfd != NULL) + saved_state.asregs.pc = bfd_get_start_address (prog_bfd); return SIM_RC_OK; } -- 2.34.1