From 63a25ea0de6d2f6d45b26af8d9c808aa35962256 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 19 Oct 2017 11:21:44 -0700 Subject: [PATCH] RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0 These are all invalid instructions, so they should not disassemble. opcodes/ChangeLog 2017-10-24 Andrew Waterman * riscv-opc.c (match_c_addi16sp) : New function. (match_c_addi4spn): New function. (match_c_lui): Don't allow 0-immediate encodings. (riscv_opcodes) : Use the above functions. : Likewise. : Likewise. : Likewise. gas/ChangeLog 2017-10-24 Andrew Waterman * testsuite/gas/riscv/c-addi16sp-fail.d: New test. testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. testsuite/gas/riscv/riscv.exp: Add new tests. --- gas/ChangeLog | 10 ++++++++ gas/testsuite/gas/riscv/c-addi16sp-fail.d | 3 +++ gas/testsuite/gas/riscv/c-addi16sp-fail.l | 2 ++ gas/testsuite/gas/riscv/c-addi16sp-fail.s | 2 ++ gas/testsuite/gas/riscv/c-addi4spn-fail.d | 3 +++ gas/testsuite/gas/riscv/c-addi4spn-fail.l | 2 ++ gas/testsuite/gas/riscv/c-addi4spn-fail.s | 2 ++ gas/testsuite/gas/riscv/riscv.exp | 2 ++ opcodes/ChangeLog | 10 ++++++++ opcodes/riscv-opc.c | 30 +++++++++++++++++------ 10 files changed, 59 insertions(+), 7 deletions(-) create mode 100644 gas/testsuite/gas/riscv/c-addi16sp-fail.d create mode 100644 gas/testsuite/gas/riscv/c-addi16sp-fail.l create mode 100644 gas/testsuite/gas/riscv/c-addi16sp-fail.s create mode 100644 gas/testsuite/gas/riscv/c-addi4spn-fail.d create mode 100644 gas/testsuite/gas/riscv/c-addi4spn-fail.l create mode 100644 gas/testsuite/gas/riscv/c-addi4spn-fail.s diff --git a/gas/ChangeLog b/gas/ChangeLog index a0f36f01ec..833e41c0a6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,13 @@ +2017-10-24 Andrew Waterman + + * testsuite/gas/riscv/c-addi16sp-fail.d: New test. + testsuite/gas/riscv/c-addi16sp-fail.l: Likewise. + testsuite/gas/riscv/c-addi16sp-fail.s: Likewise. + testsuite/gas/riscv/c-addi4spn-fail.d: Likewise. + testsuite/gas/riscv/c-addi4spn-fail.l: Likewise. + testsuite/gas/riscv/c-addi4spn-fail.s: Likewise. + testsuite/gas/riscv/riscv.exp: Add new tests. + 2017-10-24 Andrew Waterman * testsuite/gas/riscv/c-lui-fail.d: New testcase. diff --git a/gas/testsuite/gas/riscv/c-addi16sp-fail.d b/gas/testsuite/gas/riscv/c-addi16sp-fail.d new file mode 100644 index 0000000000..cc20923daf --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi16sp-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-addi16sp-fail.s +#error-output: c-addi16sp-fail.l diff --git a/gas/testsuite/gas/riscv/c-addi16sp-fail.l b/gas/testsuite/gas/riscv/c-addi16sp-fail.l new file mode 100644 index 0000000000..15f91fd93d --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi16sp-fail.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.addi16sp x1,0' diff --git a/gas/testsuite/gas/riscv/c-addi16sp-fail.s b/gas/testsuite/gas/riscv/c-addi16sp-fail.s new file mode 100644 index 0000000000..c0d3918a7a --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi16sp-fail.s @@ -0,0 +1,2 @@ +target: + c.addi16sp x1, 0 diff --git a/gas/testsuite/gas/riscv/c-addi4spn-fail.d b/gas/testsuite/gas/riscv/c-addi4spn-fail.d new file mode 100644 index 0000000000..b3c0af44c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi4spn-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32ic +#source: c-addi4spn-fail.s +#error-output: c-addi4spn-fail.l diff --git a/gas/testsuite/gas/riscv/c-addi4spn-fail.l b/gas/testsuite/gas/riscv/c-addi4spn-fail.l new file mode 100644 index 0000000000..2a8a5935f1 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi4spn-fail.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Error: illegal operands `c.addi4spn x1,0' diff --git a/gas/testsuite/gas/riscv/c-addi4spn-fail.s b/gas/testsuite/gas/riscv/c-addi4spn-fail.s new file mode 100644 index 0000000000..6963bebf63 --- /dev/null +++ b/gas/testsuite/gas/riscv/c-addi4spn-fail.s @@ -0,0 +1,2 @@ +target: + c.addi4spn x1, 0 diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp index f411335bfb..b2eaec1f57 100644 --- a/gas/testsuite/gas/riscv/riscv.exp +++ b/gas/testsuite/gas/riscv/riscv.exp @@ -22,4 +22,6 @@ if [istarget riscv*-*-*] { run_dump_test "t_insns" run_dump_test "fmv.x" run_dump_test "c-lui-fail" + run_dump_test "c-addi4spn-fail" + run_dump_test "c-addi16sp-fail" } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e47ede5b36..89ab194b8a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2017-10-24 Andrew Waterman + + * riscv-opc.c (match_c_addi16sp) : New function. + (match_c_addi4spn): New function. + (match_c_lui): Don't allow 0-immediate encodings. + (riscv_opcodes) : Use the above functions. + : Likewise. + : Likewise. + : Likewise. + 2017-10-23 Igor Tsimbalist * i386-init.h: Regenerate diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 27b4b9fb51..84cdea8fca 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -113,10 +113,26 @@ match_c_add (const struct riscv_opcode *op, insn_t insn) return match_rd_nonzero (op, insn) && ((insn & MASK_CRS2) != 0); } +static int +match_c_addi16sp (const struct riscv_opcode *op, insn_t insn) +{ + return (match_opcode (op, insn) + && (((insn & MASK_RD) >> OP_SH_RD) == 2) + && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0); +} + static int match_c_lui (const struct riscv_opcode *op, insn_t insn) { - return match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2); + return (match_rd_nonzero (op, insn) + && (((insn & MASK_RD) >> OP_SH_RD) != 2) + && EXTRACT_RVC_LUI_IMM (insn) != 0); +} + +static int +match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0; } const struct riscv_opcode riscv_opcodes[] = @@ -188,15 +204,15 @@ const struct riscv_opcode riscv_opcodes[] = {"bnez", "C", "Cs,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS }, {"bnez", "I", "s,p", MATCH_BNE, MASK_BNE | MASK_RS2, match_opcode, INSN_ALIAS }, {"bne", "I", "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, 0 }, -{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, +{"addi", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, {"addi", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"addi", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"addi", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, 0 }, {"add", "C", "d,CU,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", "C", "d,CV,CU", MATCH_C_ADD, MASK_C_ADD, match_c_add, INSN_ALIAS }, {"add", "C", "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS }, -{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, INSN_ALIAS }, -{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, INSN_ALIAS }, +{"add", "C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS }, +{"add", "C", "Cc,Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, INSN_ALIAS }, {"add", "I", "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", "I", "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 }, {"add", "I", "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS }, @@ -628,8 +644,8 @@ const struct riscv_opcode riscv_opcodes[] = {"c.mv", "C", "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, 0 }, {"c.lui", "C", "d,Cu", MATCH_C_LUI, MASK_C_LUI, match_c_lui, 0 }, {"c.li", "C", "d,Co", MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 }, -{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 }, -{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 }, +{"c.addi4spn","C", "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, 0 }, +{"c.addi16sp","C", "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_c_addi16sp, 0 }, {"c.addi", "C", "d,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 }, {"c.add", "C", "d,CV", MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 }, {"c.sub", "C", "Cs,Ct", MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 }, -- 2.34.1