From 6b35d9dd8968d4309054d94badcc80cc6dde84a4 Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Tue, 17 Feb 1998 21:52:53 +0000 Subject: [PATCH] m32r simulator testsuite --- sim/testsuite/sim/m32r/add.cgs | 16 ++++ sim/testsuite/sim/m32r/add3.cgs | 15 ++++ sim/testsuite/sim/m32r/addi.cgs | 16 ++++ sim/testsuite/sim/m32r/addv.cgs | 11 +++ sim/testsuite/sim/m32r/addv3.cgs | 11 +++ sim/testsuite/sim/m32r/and.cgs | 11 +++ sim/testsuite/sim/m32r/and3.cgs | 11 +++ sim/testsuite/sim/m32r/bc24.cgs | 24 ++++++ sim/testsuite/sim/m32r/bc8.cgs | 23 ++++++ sim/testsuite/sim/m32r/beq.cgs | 11 +++ sim/testsuite/sim/m32r/beqz.cgs | 11 +++ sim/testsuite/sim/m32r/bgez.cgs | 11 +++ sim/testsuite/sim/m32r/bgtz.cgs | 11 +++ sim/testsuite/sim/m32r/blez.cgs | 11 +++ sim/testsuite/sim/m32r/bltz.cgs | 11 +++ sim/testsuite/sim/m32r/bnc24.cgs | 11 +++ sim/testsuite/sim/m32r/bnc8.cgs | 11 +++ sim/testsuite/sim/m32r/bne.cgs | 11 +++ sim/testsuite/sim/m32r/bnez.cgs | 11 +++ sim/testsuite/sim/m32r/bra24.cgs | 11 +++ sim/testsuite/sim/m32r/bra8.cgs | 11 +++ sim/testsuite/sim/m32r/cmp.cgs | 11 +++ sim/testsuite/sim/m32r/cmpi.cgs | 11 +++ sim/testsuite/sim/m32r/cmpu.cgs | 11 +++ sim/testsuite/sim/m32r/cmpui.cgs | 11 +++ sim/testsuite/sim/m32r/div.cgs | 11 +++ sim/testsuite/sim/m32r/divu.cgs | 11 +++ sim/testsuite/sim/m32r/hello.ms | 18 +++++ sim/testsuite/sim/m32r/ld-d.cgs | 11 +++ sim/testsuite/sim/m32r/ld-plus.cgs | 11 +++ sim/testsuite/sim/m32r/ld.cgs | 11 +++ sim/testsuite/sim/m32r/ld24.cgs | 11 +++ sim/testsuite/sim/m32r/ldb-d.cgs | 11 +++ sim/testsuite/sim/m32r/ldb.cgs | 11 +++ sim/testsuite/sim/m32r/ldh-d.cgs | 11 +++ sim/testsuite/sim/m32r/ldh.cgs | 11 +++ sim/testsuite/sim/m32r/ldi16.cgs | 11 +++ sim/testsuite/sim/m32r/ldi8.cgs | 11 +++ sim/testsuite/sim/m32r/ldub-d.cgs | 11 +++ sim/testsuite/sim/m32r/ldub.cgs | 11 +++ sim/testsuite/sim/m32r/lduh-d.cgs | 11 +++ sim/testsuite/sim/m32r/lduh.cgs | 11 +++ sim/testsuite/sim/m32r/lock.cgs | 11 +++ sim/testsuite/sim/m32r/machi.cgs | 17 +++++ sim/testsuite/sim/m32r/maclo.cgs | 17 +++++ sim/testsuite/sim/m32r/macwhi.cgs | 11 +++ sim/testsuite/sim/m32r/macwlo.cgs | 11 +++ sim/testsuite/sim/m32r/mul.cgs | 11 +++ sim/testsuite/sim/m32r/mulhi.cgs | 16 ++++ sim/testsuite/sim/m32r/mullo.cgs | 16 ++++ sim/testsuite/sim/m32r/mulwhi.cgs | 11 +++ sim/testsuite/sim/m32r/mulwlo.cgs | 11 +++ sim/testsuite/sim/m32r/mv.cgs | 11 +++ sim/testsuite/sim/m32r/mvfachi.cgs | 11 +++ sim/testsuite/sim/m32r/mvfaclo.cgs | 11 +++ sim/testsuite/sim/m32r/mvfacmi.cgs | 15 ++++ sim/testsuite/sim/m32r/mvtachi.cgs | 11 +++ sim/testsuite/sim/m32r/mvtaclo.cgs | 11 +++ sim/testsuite/sim/m32r/mvtc.cgs | 11 +++ sim/testsuite/sim/m32r/neg.cgs | 11 +++ sim/testsuite/sim/m32r/nop.cgs | 11 +++ sim/testsuite/sim/m32r/not.cgs | 11 +++ sim/testsuite/sim/m32r/or.cgs | 11 +++ sim/testsuite/sim/m32r/or3.cgs | 11 +++ sim/testsuite/sim/m32r/rac-d.cgs | 11 +++ sim/testsuite/sim/m32r/rac-ds.cgs | 11 +++ sim/testsuite/sim/m32r/rac.cgs | 23 ++++++ sim/testsuite/sim/m32r/rach-d.cgs | 11 +++ sim/testsuite/sim/m32r/rach-ds.cgs | 11 +++ sim/testsuite/sim/m32r/rach.cgs | 11 +++ sim/testsuite/sim/m32r/rem.cgs | 11 +++ sim/testsuite/sim/m32r/seth.cgs | 11 +++ sim/testsuite/sim/m32r/sll.cgs | 11 +++ sim/testsuite/sim/m32r/sll3.cgs | 11 +++ sim/testsuite/sim/m32r/slli.cgs | 11 +++ sim/testsuite/sim/m32r/sra.cgs | 11 +++ sim/testsuite/sim/m32r/sra3.cgs | 11 +++ sim/testsuite/sim/m32r/srai.cgs | 11 +++ sim/testsuite/sim/m32r/srl.cgs | 11 +++ sim/testsuite/sim/m32r/srl3.cgs | 11 +++ sim/testsuite/sim/m32r/srli.cgs | 11 +++ sim/testsuite/sim/m32r/st-d.cgs | 11 +++ sim/testsuite/sim/m32r/st-minus.cgs | 11 +++ sim/testsuite/sim/m32r/st-plus.cgs | 11 +++ sim/testsuite/sim/m32r/st.cgs | 11 +++ sim/testsuite/sim/m32r/stb-d.cgs | 11 +++ sim/testsuite/sim/m32r/stb.cgs | 11 +++ sim/testsuite/sim/m32r/sth-d.cgs | 11 +++ sim/testsuite/sim/m32r/sth.cgs | 11 +++ sim/testsuite/sim/m32r/sub.cgs | 11 +++ sim/testsuite/sim/m32r/subv.cgs | 11 +++ sim/testsuite/sim/m32r/subx.cgs | 11 +++ sim/testsuite/sim/m32r/testutils.inc | 105 +++++++++++++++++++++++++++ sim/testsuite/sim/m32r/xor3.cgs | 11 +++ 94 files changed, 1212 insertions(+) create mode 100644 sim/testsuite/sim/m32r/add.cgs create mode 100644 sim/testsuite/sim/m32r/add3.cgs create mode 100644 sim/testsuite/sim/m32r/addi.cgs create mode 100644 sim/testsuite/sim/m32r/addv.cgs create mode 100644 sim/testsuite/sim/m32r/addv3.cgs create mode 100644 sim/testsuite/sim/m32r/and.cgs create mode 100644 sim/testsuite/sim/m32r/and3.cgs create mode 100644 sim/testsuite/sim/m32r/bc24.cgs create mode 100644 sim/testsuite/sim/m32r/bc8.cgs create mode 100644 sim/testsuite/sim/m32r/beq.cgs create mode 100644 sim/testsuite/sim/m32r/beqz.cgs create mode 100644 sim/testsuite/sim/m32r/bgez.cgs create mode 100644 sim/testsuite/sim/m32r/bgtz.cgs create mode 100644 sim/testsuite/sim/m32r/blez.cgs create mode 100644 sim/testsuite/sim/m32r/bltz.cgs create mode 100644 sim/testsuite/sim/m32r/bnc24.cgs create mode 100644 sim/testsuite/sim/m32r/bnc8.cgs create mode 100644 sim/testsuite/sim/m32r/bne.cgs create mode 100644 sim/testsuite/sim/m32r/bnez.cgs create mode 100644 sim/testsuite/sim/m32r/bra24.cgs create mode 100644 sim/testsuite/sim/m32r/bra8.cgs create mode 100644 sim/testsuite/sim/m32r/cmp.cgs create mode 100644 sim/testsuite/sim/m32r/cmpi.cgs create mode 100644 sim/testsuite/sim/m32r/cmpu.cgs create mode 100644 sim/testsuite/sim/m32r/cmpui.cgs create mode 100644 sim/testsuite/sim/m32r/div.cgs create mode 100644 sim/testsuite/sim/m32r/divu.cgs create mode 100644 sim/testsuite/sim/m32r/hello.ms create mode 100644 sim/testsuite/sim/m32r/ld-d.cgs create mode 100644 sim/testsuite/sim/m32r/ld-plus.cgs create mode 100644 sim/testsuite/sim/m32r/ld.cgs create mode 100644 sim/testsuite/sim/m32r/ld24.cgs create mode 100644 sim/testsuite/sim/m32r/ldb-d.cgs create mode 100644 sim/testsuite/sim/m32r/ldb.cgs create mode 100644 sim/testsuite/sim/m32r/ldh-d.cgs create mode 100644 sim/testsuite/sim/m32r/ldh.cgs create mode 100644 sim/testsuite/sim/m32r/ldi16.cgs create mode 100644 sim/testsuite/sim/m32r/ldi8.cgs create mode 100644 sim/testsuite/sim/m32r/ldub-d.cgs create mode 100644 sim/testsuite/sim/m32r/ldub.cgs create mode 100644 sim/testsuite/sim/m32r/lduh-d.cgs create mode 100644 sim/testsuite/sim/m32r/lduh.cgs create mode 100644 sim/testsuite/sim/m32r/lock.cgs create mode 100644 sim/testsuite/sim/m32r/machi.cgs create mode 100644 sim/testsuite/sim/m32r/maclo.cgs create mode 100644 sim/testsuite/sim/m32r/macwhi.cgs create mode 100644 sim/testsuite/sim/m32r/macwlo.cgs create mode 100644 sim/testsuite/sim/m32r/mul.cgs create mode 100644 sim/testsuite/sim/m32r/mulhi.cgs create mode 100644 sim/testsuite/sim/m32r/mullo.cgs create mode 100644 sim/testsuite/sim/m32r/mulwhi.cgs create mode 100644 sim/testsuite/sim/m32r/mulwlo.cgs create mode 100644 sim/testsuite/sim/m32r/mv.cgs create mode 100644 sim/testsuite/sim/m32r/mvfachi.cgs create mode 100644 sim/testsuite/sim/m32r/mvfaclo.cgs create mode 100644 sim/testsuite/sim/m32r/mvfacmi.cgs create mode 100644 sim/testsuite/sim/m32r/mvtachi.cgs create mode 100644 sim/testsuite/sim/m32r/mvtaclo.cgs create mode 100644 sim/testsuite/sim/m32r/mvtc.cgs create mode 100644 sim/testsuite/sim/m32r/neg.cgs create mode 100644 sim/testsuite/sim/m32r/nop.cgs create mode 100644 sim/testsuite/sim/m32r/not.cgs create mode 100644 sim/testsuite/sim/m32r/or.cgs create mode 100644 sim/testsuite/sim/m32r/or3.cgs create mode 100644 sim/testsuite/sim/m32r/rac-d.cgs create mode 100644 sim/testsuite/sim/m32r/rac-ds.cgs create mode 100644 sim/testsuite/sim/m32r/rac.cgs create mode 100644 sim/testsuite/sim/m32r/rach-d.cgs create mode 100644 sim/testsuite/sim/m32r/rach-ds.cgs create mode 100644 sim/testsuite/sim/m32r/rach.cgs create mode 100644 sim/testsuite/sim/m32r/rem.cgs create mode 100644 sim/testsuite/sim/m32r/seth.cgs create mode 100644 sim/testsuite/sim/m32r/sll.cgs create mode 100644 sim/testsuite/sim/m32r/sll3.cgs create mode 100644 sim/testsuite/sim/m32r/slli.cgs create mode 100644 sim/testsuite/sim/m32r/sra.cgs create mode 100644 sim/testsuite/sim/m32r/sra3.cgs create mode 100644 sim/testsuite/sim/m32r/srai.cgs create mode 100644 sim/testsuite/sim/m32r/srl.cgs create mode 100644 sim/testsuite/sim/m32r/srl3.cgs create mode 100644 sim/testsuite/sim/m32r/srli.cgs create mode 100644 sim/testsuite/sim/m32r/st-d.cgs create mode 100644 sim/testsuite/sim/m32r/st-minus.cgs create mode 100644 sim/testsuite/sim/m32r/st-plus.cgs create mode 100644 sim/testsuite/sim/m32r/st.cgs create mode 100644 sim/testsuite/sim/m32r/stb-d.cgs create mode 100644 sim/testsuite/sim/m32r/stb.cgs create mode 100644 sim/testsuite/sim/m32r/sth-d.cgs create mode 100644 sim/testsuite/sim/m32r/sth.cgs create mode 100644 sim/testsuite/sim/m32r/sub.cgs create mode 100644 sim/testsuite/sim/m32r/subv.cgs create mode 100644 sim/testsuite/sim/m32r/subx.cgs create mode 100644 sim/testsuite/sim/m32r/testutils.inc create mode 100644 sim/testsuite/sim/m32r/xor3.cgs diff --git a/sim/testsuite/sim/m32r/add.cgs b/sim/testsuite/sim/m32r/add.cgs new file mode 100644 index 0000000000..8ed2b3a2ad --- /dev/null +++ b/sim/testsuite/sim/m32r/add.cgs @@ -0,0 +1,16 @@ +# m32r testcase for add $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add +add: + + mvi_h_gr r4, 1 + mvi_h_gr r5, 2 + add r4, r5 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/add3.cgs b/sim/testsuite/sim/m32r/add3.cgs new file mode 100644 index 0000000000..d1cc8480ad --- /dev/null +++ b/sim/testsuite/sim/m32r/add3.cgs @@ -0,0 +1,15 @@ +# m32r testcase for add3 $dr,$sr,#$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global add3 +add3: + + mvi_h_gr r5, 1 + add3 r4, r5, 2 + test_h_gr r4, 3 + + pass diff --git a/sim/testsuite/sim/m32r/addi.cgs b/sim/testsuite/sim/m32r/addi.cgs new file mode 100644 index 0000000000..1448d0d2e2 --- /dev/null +++ b/sim/testsuite/sim/m32r/addi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for addi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addi +addi: + + mvi_h_gr r5, 1 + addi r5, 2 + test_h_gr r5, 3 + + pass + diff --git a/sim/testsuite/sim/m32r/addv.cgs b/sim/testsuite/sim/m32r/addv.cgs new file mode 100644 index 0000000000..6a61ccc1c9 --- /dev/null +++ b/sim/testsuite/sim/m32r/addv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for addv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv +addv: + + pass diff --git a/sim/testsuite/sim/m32r/addv3.cgs b/sim/testsuite/sim/m32r/addv3.cgs new file mode 100644 index 0000000000..3a6c899eea --- /dev/null +++ b/sim/testsuite/sim/m32r/addv3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for addv3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global addv3 +addv3: + + pass diff --git a/sim/testsuite/sim/m32r/and.cgs b/sim/testsuite/sim/m32r/and.cgs new file mode 100644 index 0000000000..3ec7337a28 --- /dev/null +++ b/sim/testsuite/sim/m32r/and.cgs @@ -0,0 +1,11 @@ +# m32r testcase for and $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and +and: + + pass diff --git a/sim/testsuite/sim/m32r/and3.cgs b/sim/testsuite/sim/m32r/and3.cgs new file mode 100644 index 0000000000..c581cddf68 --- /dev/null +++ b/sim/testsuite/sim/m32r/and3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for and3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global and3 +and3: + + pass diff --git a/sim/testsuite/sim/m32r/bc24.cgs b/sim/testsuite/sim/m32r/bc24.cgs new file mode 100644 index 0000000000..6bb43334e8 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc24.cgs @@ -0,0 +1,24 @@ +# m32r testcase for bc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc24 +bc24: + + mvi_h_condbit 0 + bc.l test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.l test1pass + fail +test1pass: + + pass + diff --git a/sim/testsuite/sim/m32r/bc8.cgs b/sim/testsuite/sim/m32r/bc8.cgs new file mode 100644 index 0000000000..ceb622c166 --- /dev/null +++ b/sim/testsuite/sim/m32r/bc8.cgs @@ -0,0 +1,23 @@ +# m32r testcase for bc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bc8 +bc8: + + mvi_h_condbit 0 + bc.s test0fail + bra test0pass +test0fail: + fail +test0pass: + + mvi_h_condbit 1 + bc.s test1pass + fail +test1pass: + + pass diff --git a/sim/testsuite/sim/m32r/beq.cgs b/sim/testsuite/sim/m32r/beq.cgs new file mode 100644 index 0000000000..90cf470442 --- /dev/null +++ b/sim/testsuite/sim/m32r/beq.cgs @@ -0,0 +1,11 @@ +# m32r testcase for beq $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beq +beq: + + pass diff --git a/sim/testsuite/sim/m32r/beqz.cgs b/sim/testsuite/sim/m32r/beqz.cgs new file mode 100644 index 0000000000..436c2fa9f1 --- /dev/null +++ b/sim/testsuite/sim/m32r/beqz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for beqz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global beqz +beqz: + + pass diff --git a/sim/testsuite/sim/m32r/bgez.cgs b/sim/testsuite/sim/m32r/bgez.cgs new file mode 100644 index 0000000000..48f90c8dce --- /dev/null +++ b/sim/testsuite/sim/m32r/bgez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bgez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgez +bgez: + + pass diff --git a/sim/testsuite/sim/m32r/bgtz.cgs b/sim/testsuite/sim/m32r/bgtz.cgs new file mode 100644 index 0000000000..fa534e4e6d --- /dev/null +++ b/sim/testsuite/sim/m32r/bgtz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bgtz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bgtz +bgtz: + + pass diff --git a/sim/testsuite/sim/m32r/blez.cgs b/sim/testsuite/sim/m32r/blez.cgs new file mode 100644 index 0000000000..be512ceac6 --- /dev/null +++ b/sim/testsuite/sim/m32r/blez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for blez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global blez +blez: + + pass diff --git a/sim/testsuite/sim/m32r/bltz.cgs b/sim/testsuite/sim/m32r/bltz.cgs new file mode 100644 index 0000000000..a379e85d75 --- /dev/null +++ b/sim/testsuite/sim/m32r/bltz.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bltz $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bltz +bltz: + + pass diff --git a/sim/testsuite/sim/m32r/bnc24.cgs b/sim/testsuite/sim/m32r/bnc24.cgs new file mode 100644 index 0000000000..2699c10275 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnc $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc24 +bnc24: + + pass diff --git a/sim/testsuite/sim/m32r/bnc8.cgs b/sim/testsuite/sim/m32r/bnc8.cgs new file mode 100644 index 0000000000..9ed1ab1dc6 --- /dev/null +++ b/sim/testsuite/sim/m32r/bnc8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnc $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnc8 +bnc8: + + pass diff --git a/sim/testsuite/sim/m32r/bne.cgs b/sim/testsuite/sim/m32r/bne.cgs new file mode 100644 index 0000000000..598ef547cd --- /dev/null +++ b/sim/testsuite/sim/m32r/bne.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bne $src1,$src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bne +bne: + + pass diff --git a/sim/testsuite/sim/m32r/bnez.cgs b/sim/testsuite/sim/m32r/bnez.cgs new file mode 100644 index 0000000000..eb35889efa --- /dev/null +++ b/sim/testsuite/sim/m32r/bnez.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bnez $src2,$disp16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bnez +bnez: + + pass diff --git a/sim/testsuite/sim/m32r/bra24.cgs b/sim/testsuite/sim/m32r/bra24.cgs new file mode 100644 index 0000000000..3469c937a2 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bra $disp24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra24 +bra24: + + pass diff --git a/sim/testsuite/sim/m32r/bra8.cgs b/sim/testsuite/sim/m32r/bra8.cgs new file mode 100644 index 0000000000..918f1d4de6 --- /dev/null +++ b/sim/testsuite/sim/m32r/bra8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for bra $disp8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global bra8 +bra8: + + pass diff --git a/sim/testsuite/sim/m32r/cmp.cgs b/sim/testsuite/sim/m32r/cmp.cgs new file mode 100644 index 0000000000..477a5b1c93 --- /dev/null +++ b/sim/testsuite/sim/m32r/cmp.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmp $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmp +cmp: + + pass diff --git a/sim/testsuite/sim/m32r/cmpi.cgs b/sim/testsuite/sim/m32r/cmpi.cgs new file mode 100644 index 0000000000..add2a4334f --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpi $src2,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpi +cmpi: + + pass diff --git a/sim/testsuite/sim/m32r/cmpu.cgs b/sim/testsuite/sim/m32r/cmpu.cgs new file mode 100644 index 0000000000..d959a3b90b --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpu.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpu $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpu +cmpu: + + pass diff --git a/sim/testsuite/sim/m32r/cmpui.cgs b/sim/testsuite/sim/m32r/cmpui.cgs new file mode 100644 index 0000000000..760663b15d --- /dev/null +++ b/sim/testsuite/sim/m32r/cmpui.cgs @@ -0,0 +1,11 @@ +# m32r testcase for cmpui $src2,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global cmpui +cmpui: + + pass diff --git a/sim/testsuite/sim/m32r/div.cgs b/sim/testsuite/sim/m32r/div.cgs new file mode 100644 index 0000000000..05fe82217b --- /dev/null +++ b/sim/testsuite/sim/m32r/div.cgs @@ -0,0 +1,11 @@ +# m32r testcase for div $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global div +div: + + pass diff --git a/sim/testsuite/sim/m32r/divu.cgs b/sim/testsuite/sim/m32r/divu.cgs new file mode 100644 index 0000000000..5b241dc1c8 --- /dev/null +++ b/sim/testsuite/sim/m32r/divu.cgs @@ -0,0 +1,11 @@ +# m32r testcase for divu $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global divu +divu: + + pass diff --git a/sim/testsuite/sim/m32r/hello.ms b/sim/testsuite/sim/m32r/hello.ms new file mode 100644 index 0000000000..0cd45bc4bf --- /dev/null +++ b/sim/testsuite/sim/m32r/hello.ms @@ -0,0 +1,18 @@ +# output: Hello world! + + .globl _start +_start: + +; write (hello world) + ldi8 r3,#14 + ld24 r2,#hello + ldi8 r1,#1 + ldi8 r0,#5 + trap #0 +; exit (0) + ldi8 r1,#0 + ldi8 r0,#1 + trap #0 + +length: .long 14 +hello: .ascii "Hello world!\r\n" diff --git a/sim/testsuite/sim/m32r/ld-d.cgs b/sim/testsuite/sim/m32r/ld-d.cgs new file mode 100644 index 0000000000..3ff3ff645e --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_d +ld_d: + + pass diff --git a/sim/testsuite/sim/m32r/ld-plus.cgs b/sim/testsuite/sim/m32r/ld-plus.cgs new file mode 100644 index 0000000000..fc6dfd28ed --- /dev/null +++ b/sim/testsuite/sim/m32r/ld-plus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@$sr+ +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld_plus +ld_plus: + + pass diff --git a/sim/testsuite/sim/m32r/ld.cgs b/sim/testsuite/sim/m32r/ld.cgs new file mode 100644 index 0000000000..3471aae717 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld +ld: + + pass diff --git a/sim/testsuite/sim/m32r/ld24.cgs b/sim/testsuite/sim/m32r/ld24.cgs new file mode 100644 index 0000000000..2ca8273cd7 --- /dev/null +++ b/sim/testsuite/sim/m32r/ld24.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ld24 $dr,#$uimm24 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ld24 +ld24: + + pass diff --git a/sim/testsuite/sim/m32r/ldb-d.cgs b/sim/testsuite/sim/m32r/ldb-d.cgs new file mode 100644 index 0000000000..711bb10332 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldb $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb_d +ldb_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldb.cgs b/sim/testsuite/sim/m32r/ldb.cgs new file mode 100644 index 0000000000..45245c38ef --- /dev/null +++ b/sim/testsuite/sim/m32r/ldb.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldb $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldb +ldb: + + pass diff --git a/sim/testsuite/sim/m32r/ldh-d.cgs b/sim/testsuite/sim/m32r/ldh-d.cgs new file mode 100644 index 0000000000..6b6c66f75f --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh_d +ldh_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldh.cgs b/sim/testsuite/sim/m32r/ldh.cgs new file mode 100644 index 0000000000..8539b3735a --- /dev/null +++ b/sim/testsuite/sim/m32r/ldh.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldh +ldh: + + pass diff --git a/sim/testsuite/sim/m32r/ldi16.cgs b/sim/testsuite/sim/m32r/ldi16.cgs new file mode 100644 index 0000000000..4f5682720c --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi16.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldi $dr,$slo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi16 +ldi16: + + pass diff --git a/sim/testsuite/sim/m32r/ldi8.cgs b/sim/testsuite/sim/m32r/ldi8.cgs new file mode 100644 index 0000000000..11d9566024 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldi8.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldi $dr,#$simm8 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldi8 +ldi8: + + pass diff --git a/sim/testsuite/sim/m32r/ldub-d.cgs b/sim/testsuite/sim/m32r/ldub-d.cgs new file mode 100644 index 0000000000..e3fc03dbb4 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldub $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub_d +ldub_d: + + pass diff --git a/sim/testsuite/sim/m32r/ldub.cgs b/sim/testsuite/sim/m32r/ldub.cgs new file mode 100644 index 0000000000..649c3118f5 --- /dev/null +++ b/sim/testsuite/sim/m32r/ldub.cgs @@ -0,0 +1,11 @@ +# m32r testcase for ldub $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global ldub +ldub: + + pass diff --git a/sim/testsuite/sim/m32r/lduh-d.cgs b/sim/testsuite/sim/m32r/lduh-d.cgs new file mode 100644 index 0000000000..57f8e50449 --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lduh $dr,@($slo16,$sr) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh_d +lduh_d: + + pass diff --git a/sim/testsuite/sim/m32r/lduh.cgs b/sim/testsuite/sim/m32r/lduh.cgs new file mode 100644 index 0000000000..94061d7e2c --- /dev/null +++ b/sim/testsuite/sim/m32r/lduh.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lduh $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lduh +lduh: + + pass diff --git a/sim/testsuite/sim/m32r/lock.cgs b/sim/testsuite/sim/m32r/lock.cgs new file mode 100644 index 0000000000..75ef76b4af --- /dev/null +++ b/sim/testsuite/sim/m32r/lock.cgs @@ -0,0 +1,11 @@ +# m32r testcase for lock $dr,@$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global lock +lock: + + pass diff --git a/sim/testsuite/sim/m32r/machi.cgs b/sim/testsuite/sim/m32r/machi.cgs new file mode 100644 index 0000000000..2e2ef00294 --- /dev/null +++ b/sim/testsuite/sim/m32r/machi.cgs @@ -0,0 +1,17 @@ +# m32r testcase for machi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global machi +machi: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x10123 + mvi_h_gr r5, 0x20456 + machi r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/maclo.cgs b/sim/testsuite/sim/m32r/maclo.cgs new file mode 100644 index 0000000000..5d035394dc --- /dev/null +++ b/sim/testsuite/sim/m32r/maclo.cgs @@ -0,0 +1,17 @@ +# m32r testcase for maclo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global maclo +maclo: + + mvi_h_accum0 0, 1 + mvi_h_gr r4, 0x1230001 + mvi_h_gr r5, 0x4560002 + maclo r4, r5 + test_h_accum0 0, 0x20001 + + pass diff --git a/sim/testsuite/sim/m32r/macwhi.cgs b/sim/testsuite/sim/m32r/macwhi.cgs new file mode 100644 index 0000000000..76a596d96c --- /dev/null +++ b/sim/testsuite/sim/m32r/macwhi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for macwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwhi +macwhi: + + pass diff --git a/sim/testsuite/sim/m32r/macwlo.cgs b/sim/testsuite/sim/m32r/macwlo.cgs new file mode 100644 index 0000000000..f1092a54a3 --- /dev/null +++ b/sim/testsuite/sim/m32r/macwlo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for macwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global macwlo +macwlo: + + pass diff --git a/sim/testsuite/sim/m32r/mul.cgs b/sim/testsuite/sim/m32r/mul.cgs new file mode 100644 index 0000000000..7e0ccc0b85 --- /dev/null +++ b/sim/testsuite/sim/m32r/mul.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mul $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mul +mul: + + pass diff --git a/sim/testsuite/sim/m32r/mulhi.cgs b/sim/testsuite/sim/m32r/mulhi.cgs new file mode 100644 index 0000000000..77c103d6f3 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulhi.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mulhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulhi +mulhi: + + mvi_h_gr r4, 0x40000 + mvi_h_gr r5, 0x50000 + mulhi r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mullo.cgs b/sim/testsuite/sim/m32r/mullo.cgs new file mode 100644 index 0000000000..11aadff379 --- /dev/null +++ b/sim/testsuite/sim/m32r/mullo.cgs @@ -0,0 +1,16 @@ +# m32r testcase for mullo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mullo +mullo: + + mvi_h_gr r4, 4 + mvi_h_gr r5, 5 + mullo r4, r5 + test_h_accum0 0, 0x140000 + + pass diff --git a/sim/testsuite/sim/m32r/mulwhi.cgs b/sim/testsuite/sim/m32r/mulwhi.cgs new file mode 100644 index 0000000000..766afcaa67 --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwhi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mulwhi $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwhi +mulwhi: + + pass diff --git a/sim/testsuite/sim/m32r/mulwlo.cgs b/sim/testsuite/sim/m32r/mulwlo.cgs new file mode 100644 index 0000000000..6bd267d47d --- /dev/null +++ b/sim/testsuite/sim/m32r/mulwlo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mulwlo $src1,$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mulwlo +mulwlo: + + pass diff --git a/sim/testsuite/sim/m32r/mv.cgs b/sim/testsuite/sim/m32r/mv.cgs new file mode 100644 index 0000000000..b14cbe3050 --- /dev/null +++ b/sim/testsuite/sim/m32r/mv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mv +mv: + + pass diff --git a/sim/testsuite/sim/m32r/mvfachi.cgs b/sim/testsuite/sim/m32r/mvfachi.cgs new file mode 100644 index 0000000000..380e37be1a --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfachi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvfachi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfachi +mvfachi: + + pass diff --git a/sim/testsuite/sim/m32r/mvfaclo.cgs b/sim/testsuite/sim/m32r/mvfaclo.cgs new file mode 100644 index 0000000000..0e05cf04ff --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfaclo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvfaclo $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfaclo +mvfaclo: + + pass diff --git a/sim/testsuite/sim/m32r/mvfacmi.cgs b/sim/testsuite/sim/m32r/mvfacmi.cgs new file mode 100644 index 0000000000..580bcae989 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvfacmi.cgs @@ -0,0 +1,15 @@ +# m32r testcase for mvfacmi $dr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvfacmi +mvfacmi: + + mvi_h_accum0 0x12345678, 0x87654321 + mvfacmi r4 + test_h_gr r4, 0x56788765 + + pass diff --git a/sim/testsuite/sim/m32r/mvtachi.cgs b/sim/testsuite/sim/m32r/mvtachi.cgs new file mode 100644 index 0000000000..827dc103b3 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtachi.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtachi $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtachi +mvtachi: + + pass diff --git a/sim/testsuite/sim/m32r/mvtaclo.cgs b/sim/testsuite/sim/m32r/mvtaclo.cgs new file mode 100644 index 0000000000..5f628f3d60 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtaclo.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtaclo $src1 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtaclo +mvtaclo: + + pass diff --git a/sim/testsuite/sim/m32r/mvtc.cgs b/sim/testsuite/sim/m32r/mvtc.cgs new file mode 100644 index 0000000000..9d824c9e44 --- /dev/null +++ b/sim/testsuite/sim/m32r/mvtc.cgs @@ -0,0 +1,11 @@ +# m32r testcase for mvtc $sr,$dcr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global mvtc +mvtc: + + pass diff --git a/sim/testsuite/sim/m32r/neg.cgs b/sim/testsuite/sim/m32r/neg.cgs new file mode 100644 index 0000000000..52bb44cd53 --- /dev/null +++ b/sim/testsuite/sim/m32r/neg.cgs @@ -0,0 +1,11 @@ +# m32r testcase for neg $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global neg +neg: + + pass diff --git a/sim/testsuite/sim/m32r/nop.cgs b/sim/testsuite/sim/m32r/nop.cgs new file mode 100644 index 0000000000..517d34d97e --- /dev/null +++ b/sim/testsuite/sim/m32r/nop.cgs @@ -0,0 +1,11 @@ +# m32r testcase for nop +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global nop +nop: + + pass diff --git a/sim/testsuite/sim/m32r/not.cgs b/sim/testsuite/sim/m32r/not.cgs new file mode 100644 index 0000000000..358dac546c --- /dev/null +++ b/sim/testsuite/sim/m32r/not.cgs @@ -0,0 +1,11 @@ +# m32r testcase for not $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global not +not: + + pass diff --git a/sim/testsuite/sim/m32r/or.cgs b/sim/testsuite/sim/m32r/or.cgs new file mode 100644 index 0000000000..afa629bbce --- /dev/null +++ b/sim/testsuite/sim/m32r/or.cgs @@ -0,0 +1,11 @@ +# m32r testcase for or $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or +or: + + pass diff --git a/sim/testsuite/sim/m32r/or3.cgs b/sim/testsuite/sim/m32r/or3.cgs new file mode 100644 index 0000000000..200907a016 --- /dev/null +++ b/sim/testsuite/sim/m32r/or3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for or3 $dr,$sr,#$ulo16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global or3 +or3: + + pass diff --git a/sim/testsuite/sim/m32r/rac-d.cgs b/sim/testsuite/sim/m32r/rac-d.cgs new file mode 100644 index 0000000000..201fd79c9e --- /dev/null +++ b/sim/testsuite/sim/m32r/rac-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rac $accd +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac_d +rac_d: + + pass diff --git a/sim/testsuite/sim/m32r/rac-ds.cgs b/sim/testsuite/sim/m32r/rac-ds.cgs new file mode 100644 index 0000000000..44dc4fa1de --- /dev/null +++ b/sim/testsuite/sim/m32r/rac-ds.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rac $accd,$accs +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac_ds +rac_ds: + + pass diff --git a/sim/testsuite/sim/m32r/rac.cgs b/sim/testsuite/sim/m32r/rac.cgs new file mode 100644 index 0000000000..35b9ae3cd9 --- /dev/null +++ b/sim/testsuite/sim/m32r/rac.cgs @@ -0,0 +1,23 @@ +# m32r testcase for rac +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rac +rac: + + mvi_h_accum0 1, 0x4001 + rac + test_h_accum0 2, 0x10000 + + mvi_h_accum0 0x3fff, 0xffff4000 + rac + test_h_accum0 0x7fff, 0xffff0000 + + mvi_h_accum0 0xffff8000, 0 + rac + test_h_accum0 0xffff8000, 0 + + pass diff --git a/sim/testsuite/sim/m32r/rach-d.cgs b/sim/testsuite/sim/m32r/rach-d.cgs new file mode 100644 index 0000000000..52a336a65b --- /dev/null +++ b/sim/testsuite/sim/m32r/rach-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach $accd +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach_d +rach_d: + + pass diff --git a/sim/testsuite/sim/m32r/rach-ds.cgs b/sim/testsuite/sim/m32r/rach-ds.cgs new file mode 100644 index 0000000000..c95ccf5630 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach-ds.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach $accd,$accs +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach_ds +rach_ds: + + pass diff --git a/sim/testsuite/sim/m32r/rach.cgs b/sim/testsuite/sim/m32r/rach.cgs new file mode 100644 index 0000000000..efc36d8451 --- /dev/null +++ b/sim/testsuite/sim/m32r/rach.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rach +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rach +rach: + + pass diff --git a/sim/testsuite/sim/m32r/rem.cgs b/sim/testsuite/sim/m32r/rem.cgs new file mode 100644 index 0000000000..f9416c856c --- /dev/null +++ b/sim/testsuite/sim/m32r/rem.cgs @@ -0,0 +1,11 @@ +# m32r testcase for rem $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global rem +rem: + + pass diff --git a/sim/testsuite/sim/m32r/seth.cgs b/sim/testsuite/sim/m32r/seth.cgs new file mode 100644 index 0000000000..bfe57c0927 --- /dev/null +++ b/sim/testsuite/sim/m32r/seth.cgs @@ -0,0 +1,11 @@ +# m32r testcase for seth $dr,#$hi16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global seth +seth: + + pass diff --git a/sim/testsuite/sim/m32r/sll.cgs b/sim/testsuite/sim/m32r/sll.cgs new file mode 100644 index 0000000000..492032ae7d --- /dev/null +++ b/sim/testsuite/sim/m32r/sll.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sll $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll +sll: + + pass diff --git a/sim/testsuite/sim/m32r/sll3.cgs b/sim/testsuite/sim/m32r/sll3.cgs new file mode 100644 index 0000000000..6d2747cbc7 --- /dev/null +++ b/sim/testsuite/sim/m32r/sll3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sll3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sll3 +sll3: + + pass diff --git a/sim/testsuite/sim/m32r/slli.cgs b/sim/testsuite/sim/m32r/slli.cgs new file mode 100644 index 0000000000..600d27aaa3 --- /dev/null +++ b/sim/testsuite/sim/m32r/slli.cgs @@ -0,0 +1,11 @@ +# m32r testcase for slli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global slli +slli: + + pass diff --git a/sim/testsuite/sim/m32r/sra.cgs b/sim/testsuite/sim/m32r/sra.cgs new file mode 100644 index 0000000000..3c72199e20 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sra $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra +sra: + + pass diff --git a/sim/testsuite/sim/m32r/sra3.cgs b/sim/testsuite/sim/m32r/sra3.cgs new file mode 100644 index 0000000000..837258dd70 --- /dev/null +++ b/sim/testsuite/sim/m32r/sra3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sra3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sra3 +sra3: + + pass diff --git a/sim/testsuite/sim/m32r/srai.cgs b/sim/testsuite/sim/m32r/srai.cgs new file mode 100644 index 0000000000..603c5b7cc1 --- /dev/null +++ b/sim/testsuite/sim/m32r/srai.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srai $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srai +srai: + + pass diff --git a/sim/testsuite/sim/m32r/srl.cgs b/sim/testsuite/sim/m32r/srl.cgs new file mode 100644 index 0000000000..ccbf46039f --- /dev/null +++ b/sim/testsuite/sim/m32r/srl.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srl $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl +srl: + + pass diff --git a/sim/testsuite/sim/m32r/srl3.cgs b/sim/testsuite/sim/m32r/srl3.cgs new file mode 100644 index 0000000000..d26f57195a --- /dev/null +++ b/sim/testsuite/sim/m32r/srl3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srl3 $dr,$sr,#$simm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srl3 +srl3: + + pass diff --git a/sim/testsuite/sim/m32r/srli.cgs b/sim/testsuite/sim/m32r/srli.cgs new file mode 100644 index 0000000000..5ce6d07bd4 --- /dev/null +++ b/sim/testsuite/sim/m32r/srli.cgs @@ -0,0 +1,11 @@ +# m32r testcase for srli $dr,#$uimm5 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global srli +srli: + + pass diff --git a/sim/testsuite/sim/m32r/st-d.cgs b/sim/testsuite/sim/m32r/st-d.cgs new file mode 100644 index 0000000000..29e106612c --- /dev/null +++ b/sim/testsuite/sim/m32r/st-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_d +st_d: + + pass diff --git a/sim/testsuite/sim/m32r/st-minus.cgs b/sim/testsuite/sim/m32r/st-minus.cgs new file mode 100644 index 0000000000..1aed708fd0 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-minus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@-$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_minus +st_minus: + + pass diff --git a/sim/testsuite/sim/m32r/st-plus.cgs b/sim/testsuite/sim/m32r/st-plus.cgs new file mode 100644 index 0000000000..00539d7477 --- /dev/null +++ b/sim/testsuite/sim/m32r/st-plus.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@+$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st_plus +st_plus: + + pass diff --git a/sim/testsuite/sim/m32r/st.cgs b/sim/testsuite/sim/m32r/st.cgs new file mode 100644 index 0000000000..cd2d9c5779 --- /dev/null +++ b/sim/testsuite/sim/m32r/st.cgs @@ -0,0 +1,11 @@ +# m32r testcase for st $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global st +st: + + pass diff --git a/sim/testsuite/sim/m32r/stb-d.cgs b/sim/testsuite/sim/m32r/stb-d.cgs new file mode 100644 index 0000000000..533ccf0616 --- /dev/null +++ b/sim/testsuite/sim/m32r/stb-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for stb $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb_d +stb_d: + + pass diff --git a/sim/testsuite/sim/m32r/stb.cgs b/sim/testsuite/sim/m32r/stb.cgs new file mode 100644 index 0000000000..2b5dff1c1c --- /dev/null +++ b/sim/testsuite/sim/m32r/stb.cgs @@ -0,0 +1,11 @@ +# m32r testcase for stb $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global stb +stb: + + pass diff --git a/sim/testsuite/sim/m32r/sth-d.cgs b/sim/testsuite/sim/m32r/sth-d.cgs new file mode 100644 index 0000000000..14a4711122 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth-d.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sth $src1,@($slo16,$src2) +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth_d +sth_d: + + pass diff --git a/sim/testsuite/sim/m32r/sth.cgs b/sim/testsuite/sim/m32r/sth.cgs new file mode 100644 index 0000000000..d0dd43da44 --- /dev/null +++ b/sim/testsuite/sim/m32r/sth.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sth $src1,@$src2 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sth +sth: + + pass diff --git a/sim/testsuite/sim/m32r/sub.cgs b/sim/testsuite/sim/m32r/sub.cgs new file mode 100644 index 0000000000..8dbe6b8889 --- /dev/null +++ b/sim/testsuite/sim/m32r/sub.cgs @@ -0,0 +1,11 @@ +# m32r testcase for sub $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global sub +sub: + + pass diff --git a/sim/testsuite/sim/m32r/subv.cgs b/sim/testsuite/sim/m32r/subv.cgs new file mode 100644 index 0000000000..4a46fb57f6 --- /dev/null +++ b/sim/testsuite/sim/m32r/subv.cgs @@ -0,0 +1,11 @@ +# m32r testcase for subv $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subv +subv: + + pass diff --git a/sim/testsuite/sim/m32r/subx.cgs b/sim/testsuite/sim/m32r/subx.cgs new file mode 100644 index 0000000000..597373ab3f --- /dev/null +++ b/sim/testsuite/sim/m32r/subx.cgs @@ -0,0 +1,11 @@ +# m32r testcase for subx $dr,$sr +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global subx +subx: + + pass diff --git a/sim/testsuite/sim/m32r/testutils.inc b/sim/testsuite/sim/m32r/testutils.inc new file mode 100644 index 0000000000..24d925ed1a --- /dev/null +++ b/sim/testsuite/sim/m32r/testutils.inc @@ -0,0 +1,105 @@ +# r0-r3 are used as tmps, consider them call clobbered by these macros. + + .macro start + .data +failmsg: + .ascii "fail\n" +passmsg: + .ascii "pass\n" + .text + .global _start +_start: + .endm + + .macro exit rc + ldi8 r1, \rc + ldi8 r0, #1 + trap #0 + .endm + + .macro pass + ldi8 r3, 5 + ld24 r2, passmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 0 + .endm + + .macro fail + ldi8 r3, 5 + ld24 r2, failmsg + ldi8 r1, 1 + ldi8 r0, 5 + trap #0 + exit 1 + .endm + + .macro mvi_h_gr reg, val + .if (\val >= -128) && (\val <= 127) + ldi8 \reg, \val + .else + seth \reg, high(\val) + or3 \reg, \reg, low(\val) + .endif + .endm + +# Other macros know this only clobbers r0. + .macro test_h_gr reg, val + mvi_h_gr r0, \val + beq \reg, r0, test_gr\@ + fail +test_gr\@: + .endm + + .macro mvi_h_condbit val + ldi8 r0, 0 + ldi8 r1, 1 + .if \val + cmp r0, r1 + .else + cmp r1, r0 + .endif + .endm + + .macro test_h_condbit val + .if \val + bc test_c1\@ + fail +test_c1\@: + .else + bnc test_c0\@ + fail +test_c0\@: + .endif + .endm + + .macro mvi_h_accum0 hi, lo + mvi_h_gr r0, \hi + mvtachi r0 + mvi_h_gr r0, \lo + mvtaclo r0 + .endm + + .macro test_h_accum0 hi, lo + mvfachi r1 + test_h_gr r1, \hi + mvfaclo r1 + test_h_gr r1, \lo + .endm + +# start-sanitize-m32rx + .macro mvi_h_accum1 hi, lo + mvi_h_gr r0, \hi + mvtachi r0, a1 + mvi_h_gr r0, \lo + mvtaclo r0, a1 + .endm + + .macro test_h_accum1 hi, lo + mvfachi r1, a1 + test_h_gr r1, \hi + mvfaclo r1, a1 + test_h_gr r1, \lo + .endm +# end-sanitize-m32rx diff --git a/sim/testsuite/sim/m32r/xor3.cgs b/sim/testsuite/sim/m32r/xor3.cgs new file mode 100644 index 0000000000..7e1879e393 --- /dev/null +++ b/sim/testsuite/sim/m32r/xor3.cgs @@ -0,0 +1,11 @@ +# m32r testcase for xor3 $dr,$sr,#$uimm16 +# mach(): m32r m32rx + + .include "testutils.inc" + + start + + .global xor3 +xor3: + + pass -- 2.34.1