From 7fce7ea986bc66d4af3c21d4f6ab2a987f3aac46 Mon Sep 17 00:00:00 2001 From: Przemyslaw Wirkus Date: Fri, 12 Mar 2021 14:18:59 +0000 Subject: [PATCH] aarch64: Add few missing system registers This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. --- gas/ChangeLog | 8 +++++++ gas/testsuite/gas/aarch64/illegal-sysreg-7.d | 2 ++ gas/testsuite/gas/aarch64/illegal-sysreg-7.l | 2 ++ gas/testsuite/gas/aarch64/illegal-sysreg-7.s | 2 ++ gas/testsuite/gas/aarch64/sysreg-7.d | 25 ++++++++++++++++++++ gas/testsuite/gas/aarch64/sysreg-7.s | 20 ++++++++++++++++ opcodes/ChangeLog | 5 ++++ opcodes/aarch64-opc.c | 10 ++++++++ 8 files changed, 74 insertions(+) create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.d create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.l create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg-7.s create mode 100644 gas/testsuite/gas/aarch64/sysreg-7.d create mode 100644 gas/testsuite/gas/aarch64/sysreg-7.s diff --git a/gas/ChangeLog b/gas/ChangeLog index 01161d5000..79332f0f5d 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,11 @@ +2021-03-12 Przemyslaw Wirkus + + * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. + * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. + * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. + * testsuite/gas/aarch64/sysreg-7.d: New test. + * testsuite/gas/aarch64/sysreg-7.s: New test. + 2021-03-12 Clément Chigot * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section, diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.d b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d new file mode 100644 index 0000000000..d7a11ed372 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.d @@ -0,0 +1,2 @@ +#source: illegal-sysreg-7.s +#warning_output: illegal-sysreg-7.l diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.l b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l new file mode 100644 index 0000000000..1db54b3453 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: specified register cannot be written to at operand 1 -- `msr ich_vtr_el2,x0' diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-7.s b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s new file mode 100644 index 0000000000..311e18227b --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-7.s @@ -0,0 +1,2 @@ +/* Write to R/O system registers. */ +msr ich_vtr_el2, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg-7.d b/gas/testsuite/gas/aarch64/sysreg-7.d new file mode 100644 index 0000000000..1564f530c6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg-7.d @@ -0,0 +1,25 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + +.*: d538a460 mrs x0, lorc_el1 +.*: d538a420 mrs x0, lorea_el1 +.*: d538a440 mrs x0, lorn_el1 +.*: d538a400 mrs x0, lorsa_el1 +.*: d53ecc80 mrs x0, icc_ctlr_el3 +.*: d538cca0 mrs x0, icc_sre_el1 +.*: d53cc9a0 mrs x0, icc_sre_el2 +.*: d53ecca0 mrs x0, icc_sre_el3 +.*: d53ccb20 mrs x0, ich_vtr_el2 +.*: d518a460 msr lorc_el1, x0 +.*: d518a420 msr lorea_el1, x0 +.*: d518a440 msr lorn_el1, x0 +.*: d518a400 msr lorsa_el1, x0 +.*: d51ecc80 msr icc_ctlr_el3, x0 +.*: d518cca0 msr icc_sre_el1, x0 +.*: d51cc9a0 msr icc_sre_el2, x0 +.*: d51ecca0 msr icc_sre_el3, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg-7.s b/gas/testsuite/gas/aarch64/sysreg-7.s new file mode 100644 index 0000000000..3d438d1c74 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg-7.s @@ -0,0 +1,20 @@ +/* Read from system registers. */ +mrs x0, lorc_el1 +mrs x0, lorea_el1 +mrs x0, lorn_el1 +mrs x0, lorsa_el1 +mrs x0, icc_ctlr_el3 +mrs x0, icc_sre_el1 +mrs x0, icc_sre_el2 +mrs x0, icc_sre_el3 +mrs x0, ich_vtr_el2 + +/* Write to system registers. */ +msr lorc_el1, x0 +msr lorea_el1, x0 +msr lorn_el1, x0 +msr lorsa_el1, x0 +msr icc_ctlr_el3, x0 +msr icc_sre_el1, x0 +msr icc_sre_el2, x0 +msr icc_sre_el3, x0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 893a97548e..b3390e30ba 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2021-03-12 Przemyslaw Wirkus + + * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, + icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. + 2021-03-12 Alan Modra * i386-dis.c (print_insn ): Correct typo. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 50d6412393..521ec6f9c8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4570,6 +4570,16 @@ const aarch64_sys_reg aarch64_sys_regs [] = SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0), SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ), + SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0), + SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0), + SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0), + SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0), + SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0), + SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0), + SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0), + SR_CORE ("icc_sre_el3", CPENC (3,6,C12,C12,5), 0), + SR_CORE ("ich_vtr_el2", CPENC (3,4,C12,C11,1), F_REG_READ), + SR_CORE ("brbcr_el1", CPENC (2,1,C9,C0,0), 0), SR_CORE ("brbcr_el12", CPENC (2,5,C9,C0,0), 0), SR_CORE ("brbfcr_el1", CPENC (2,1,C9,C0,1), 0), -- 2.34.1