From 9781aa8adbc13b9960b5a3a7353efc57eeb3697d Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Wed, 12 Jun 2013 09:59:59 +0100 Subject: [PATCH] ARM: l2x0: use -st dsb option for ordering writel_relaxed with unlock writel_relaxed and spin_unlock are both store operations, so we only need to enforce store ordering in the dsb. Signed-off-by: Will Deacon --- arch/arm/mm/cache-l2x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index d70e0aba0c9d..0c3fc276bd30 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -290,7 +290,7 @@ static void l2x0_disable(void) raw_spin_lock_irqsave(&l2x0_lock, flags); __l2x0_flush_all(); writel_relaxed(0, l2x0_base + L2X0_CTRL); - dsb(); + dsb(st); raw_spin_unlock_irqrestore(&l2x0_lock, flags); } -- 2.34.1