From b1d3c886aa30083236bf60c50d519bcc978139fb Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Fri, 30 Jun 2017 15:27:18 +0100 Subject: [PATCH] MIPS/opcodes: Reorder LSA and DLSA instructions Correct an issue introduced with commit 7361da2c952e ("Add support for MIPS R6.") and move the LSA and DLSA instructions back to the MSA ASE instruction block in the regular MIPS opcode table. Adjust formatting around the "MIPS r6" heading. opcodes/ * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa" entries to the MSA ASE instruction block. --- opcodes/ChangeLog | 5 +++++ opcodes/mips-opc.c | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f3c0c62b40..5392d27137 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-06-30 Maciej W. Rozycki + + * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa" + entries to the MSA ASE instruction block. + 2017-06-30 Andrew Bennett Maciej W. Rozycki diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 9c392ba32d..19fca408c9 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -3158,6 +3158,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ctcmsa", "+l,d", 0x783e0019, 0xffff003f, RD_2|CM, 0, 0, MSA, 0 }, {"cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|CM, 0, 0, MSA, 0 }, {"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, +{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, /* interAptiv MR2 instruction extensions. */ {"restore", "-m", 0x7000001f, 0xfc00603f, WR_31|NODS, MOD_SP, IAMR2, 0, 0 }, @@ -3228,10 +3230,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, {"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, {"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, -{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, -/* MIPS r6. */ +/* MIPS r6. */ {"aui", "t,s,u", 0x3c000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, {"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 }, {"daui", "t,s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, -- 2.34.1