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drm/i915: Don't use pipe_offset stuff for DPLL registers
2014-06-11  Ville Syrjälädrm/i915: Don't use pipe_offset stuff for DPLL registers
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2014-06-11  Ville Syrjälädrm/i915/chv: Force PHY clock buffers off after PLL...
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2014-06-11  Ville Syrjälädrm/i915/chv: Force clock buffer enables
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2014-06-11  Ville Syrjälädrm/i915/chv: Try to program the PHY used clock channel...
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2014-06-11  Ville Syrjälädrm/i915/chv: Skip gen6_gt_check_fifodbg() on CHV
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2014-06-11  Ville Syrjälädrm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0
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2014-06-11  Ville Syrjälädrm/i915: Keep vblank interrupts enabled while enabling...
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2014-06-05  Ville Syrjälädrm/i915: Don't WARN about ring idle bit on gen2
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2014-06-05  Ville Syrjälädrm/i915: Move the C3 LP write bit setup to gen3_init_clock_...
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2014-06-05  Ville Syrjälädrm/i915: Enable interrupt-based AGPBUSY# enable on 85x
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2014-06-05  Ville Syrjälädrm/i915: Flip the sense of AGPBUSY_DIS bit
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2014-06-05  Ville Syrjälädrm/i915: Set AGPBUSY# bit in init_clock_gating
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2014-05-22  Ville Syrjälädrm/i915: Implement WaVcpClkGateDisableForMediaReset...
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2014-05-22  Ville Syrjälädrm/i915: Fix gen2 and hsw+ scanline counter
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2014-05-22  Ville Syrjälädrm/i915: Draw a picture about video timings
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2014-05-22  Ville Syrjälädrm/i915: Improve gen3/4 frame counter
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2014-05-22  Ville Syrjälädrm/i915: Add a small adjustment to the pixel counter...
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2014-05-22  Ville Syrjälädrm/i915: Wait for pending page flips before enabling...
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2014-05-22  Ville Syrjälädrm/i915: Shuffle fifo underrun disable/enable points...
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2014-05-22  Ville Syrjälädrm/i915: Simplify the uncleared FIFO underrun detection
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2014-05-22  Ville Syrjälädrm/i915: Check for FIFO underruns at the end of modeset...
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2014-05-22  Ville Syrjälädrm/i915: Check for FIFO underuns when disabling reporting...
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2014-05-22  Ville Syrjälädrm/i915: Provide DPIO diagrams as docboox tables
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2014-05-22  Ville Syrjälädrm/i915: Add a brief description of the VLV display...
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2014-05-21  Ville Syrjälädrm/i915: Re-enable vblank irqs for already active...
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2014-05-21  Ville Syrjälädrm/i915: Move buffer pinning and ring selection to...
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2014-05-21  Ville Syrjälädrm/i915: Drop the excessive vblank waits from modeset...
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2014-05-21  Ville Syrjälädrm/i915: Wait for vblank in hsw_enable_ips()
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2014-05-21  Ville Syrjälädrm/i915: Fix mmio vs. CS flip race on ILK+
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2014-05-20  Ville Syrjälädrm: Add drm_vblank_on()
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2014-05-20  Ville Syrjälädrm: Make blocking vblank wait return when the vblank...
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2014-05-20  Ville Syrjälädrm: Make the vblank disable timer per-crtc
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2014-05-20  Ville Syrjälädrm/i915: Clear GDSR after reset on ILK
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2014-05-20  Ville Syrjälädrm/i915: Kill RMW from ILK reset code
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2014-05-20  Ville Syrjälädrm/i915: Drop /** */ comments from i915_reg.h
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2014-05-20  Ville Syrjälädrm/i915/chv: Add a bunch of pre production workarounds
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2014-05-20  Ville Syrjälädrm/i915/chv: Use RMW to toggle swing calc init
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2014-05-20  Ville Syrjälädrm/i915/chv: Don't do group access reads from TX lanes...
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2014-05-20  Ville Syrjälädrm/i915/chv: Don't use PCS group access reads
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2014-05-20  Ville Syrjälädrm/i915/chv: Set soft reset override bit for data...
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2014-05-20  Ville Syrjälädrm/i915/chv: Reset data lanes in encoder .post_disable...
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2014-05-20  Ville Syrjälädrm/i915/chv: Turn off dclkp after the PLL has been...
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2014-05-20  Ville Syrjälädrm/i915/chv: Move data lane deassert to encoder pre_enable
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2014-05-20  Ville Syrjälädrm/i915/chv: Fix CHV PLL state tracking
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2014-05-20  Ville Syrjälädrm/i915/chv: Register port D encoders and connectors
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2014-05-20  Ville Syrjälädrm/i915/chv: Fix PORT_TO_PIPE for CHV
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2014-05-20  Ville Syrjälädrm/i915/chv: Bump num_pipes to 3
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2014-05-20  Ville Syrjälädrm/i915/chv: Add cursor pipe offsets
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2014-05-20  Ville Syrjälädrm/i915/chv: Fix gmbus for port D
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2014-05-20  Ville Syrjälädrm/i915/chv: Configure crtc_mask correctly for CHV
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2014-05-20  Ville Syrjälädrm/i915/chv: Make CHV irq handler loop until all interrupts...
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2014-05-20  Ville Syrjälädrrm/i915/chv: Use valleyview_pipestat_irq_handler...
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2014-05-20  Ville Syrjälädrm/i915/chv: Clarify VLV/CHV PIPESTAT bits a bit more
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2014-05-20  Ville Syrjälädrm/i915/chv: Add some workaround notes
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaDisableSDEUnitClockGating:chv
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaDisableCSUnitClockGating:chv
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaDisableSemaphoreAndSyncFlipWait:chv
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaVSRefCountFullforceMissDisable...
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaDisableThreadStallDopClockGating:chv
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2014-05-20  Ville Syrjälädrm/i915/chv: Implement WaDisablePartialInstShootdown:chv
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2014-05-20  Ville Syrjälädrm/i915: Fix ILK GPU reset domain bits
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2014-05-20  Ville Syrjälädrm/i915: Fix ILK reset wait
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2014-05-20  Ville Syrjälädrm/i915: Drop bogus comments about display reset
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2014-05-16  Ville Syrjälädrm/i915: Convert uncleared FIFO underrun message to...
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2014-05-15  Ville Syrjälädrm/i915: Increase WM memory latency values on SNB
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2014-05-13  Ville Syrjälädrm/i915: Kill vblank waits after pipe enable on gmch...
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2014-05-13  Ville Syrjälädrm/i915: Disable/enable planes as the first/last thing...
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2014-05-13  Ville Syrjäläx86/gpu: Sprinkle const, __init and __initconst to...
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2014-05-13  Ville Syrjälädrm/i915/chv: CHV doesn't have CRT output
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2014-05-13  Ville Syrjälädrm/i915/chv: Add DPLL state readout support
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2014-05-12  Ville Syrjälädrm/i915/chv: Add DDL register defines for Cherryview
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2014-05-12  Ville Syrjäläsrm/i915/chv: Add Cherryview PCI IDs
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2014-05-12  Ville Syrjälädrm/i915/chv: Initial clock gating support for Cherryview
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2014-05-12  Ville Syrjälädrm/i915/chv: Add Cherryview interrupt registers into...
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2014-05-12  Ville Syrjälädrm/i915/chv: Preliminary interrupt support for Cherryview
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2014-05-12  Ville Syrjälädrm/i915: Convert gmch platforms over to ilk_crtc_...
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2014-05-06  Ville Syrjälädrm/i915/chv: Add DPINVGTT registers defines for Cherryview
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2014-05-06  Ville Syrjälädrm/i915/chv: Add display interrupt registers bits...
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2014-05-06  Ville Syrjälädrm/i915/chv: Add DPFLIPSTAT register bits for Cherryview
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2014-05-06  Ville Syrjälädrm/i915/chv: Add PIPESTAT register bits for Cherryview
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2014-05-06  Ville Syrjälädrm/i915/chv: Enable aliasing PPGTT for CHV
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2014-05-06  Ville Syrjälädrm/i915/chv: PPAT setup for Cherryview
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2014-05-06  Ville Syrjälädrm/i915: Remove useless checks from primary enable...
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2014-05-06  Ville Syrjälädrm/i915: Merge LP1+ watermarks in safer way
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2014-05-06  Ville Syrjälädrm/i915: Make sure computed watermarks never overflow...
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2014-05-06  Ville Syrjälädrm/i915: Add pipe update trace points
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2014-05-06  Ville Syrjälädrm/i915: Perform primary enable/disable atomically...
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2014-05-06  Ville Syrjälädrm/i915: Make sprite updates atomic
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2014-05-05  Ville Syrjälädrm/i915: Make primary_enabled match the actual hardware...
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2014-05-05  Ville Syrjälädrm/i915: Add intel_get_crtc_scanline()
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2014-05-05  Ville Syrjälädrm/i915: Fix scanout position for real
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2014-05-05  Ville Syrjälädrm/i915: Fix assert_plane warning during FDI link...
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2014-05-05  Ville Syrjälädrm/i915: Fix deadlock during driver init on ILK
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2014-04-22  Ville Syrjälädrm/i915: Allow user modes to exceed DVI 165MHz limit
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2014-04-15  Ville Syrjälädrm/i915: Disable/enable planes as the first/last thing...
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2014-04-14  Ville Syrjäläx86/gpu: Fix sign extension issue in Intel graphics...
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2014-04-09  Ville Syrjälädrm/i915/chv: Add IS_CHERRYVIEW() macro
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2014-04-09  Ville Syrjälädrm/i915/chv: IS_BROADWELL() should not be true for...
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2014-04-09  Ville Syrjälädrm/i916: Refactor WM register maximums
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2014-04-09  Ville Syrjälädrm/i915: Skip watermark merging for inactive pipes
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