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2017-10-24	Andrew Waterman	RISC-V: Fix disassembly of c.addi4spn, c.addi16sp,... 2017-10-24 Andrew Waterman <andrew@sifive.com> 2017-10-24 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-10-24	Andrew Waterman	RISC-V: Only relax to C.LUI when imm != 0 and rd !... 2017-10-24 Andrew Waterman <andrew@sifive.com> 2017-10-24 Andrew Waterman <andrew@sifive.com> 2017-10-24 Andrew Waterman <andrew@sifive.com> 2017-10-24 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-07-28	Andrew Waterman	Fix problems parsing RISCV architecture extenstions...	commit \| commitdiff \| tree
2017-06-29	Andrew Waterman	RISC-V: Fix TLS copy relocs 2017-06-29 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-06-23	Andrew Waterman	RISC-V: Fix SLTI disassembly 2017-06-23 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-06-23	Andrew Waterman	RISC-V: Error, don't warn, for shfit amounts/CSRs 2017-05-11 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-03-31	Andrew Waterman	RISC-V: Add physical memory protection CSRs 2017-03-27 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-03-14	Andrew Waterman	RISC-V: Fix [dis]assembly of srai/srli	commit \| commitdiff \| tree
2017-02-24	Andrew Waterman	bfd: RISC-V: relax to gp in more cases. 2017-02-24 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-02-24	Andrew Waterman	Add new counter-enable CSRs 2017-02-22 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-02-15	Andrew Waterman	Add SFENCE.VMA instruction 2017-02-14 Andrew Waterman <andrew@sifive.com> 2017-02-14 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-02-08	Andrew Waterman	Fix segfault when .plt section does not exist 2017-02-07 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-01-09	Andrew Waterman	RISC-V/GAS: Support more relocs against constant addresses 2017-01-09 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-01-09	Andrew Waterman	RISC-V/GAS: Improve handling of invalid relocs 2017-01-09 Andrew Waterman <andrew@sifive.com>	commit \| commitdiff \| tree
2017-01-09	Andrew Waterman	RISC-V/GAS: Correct branch relaxation for weak symbols.	commit \| commitdiff \| tree
2016-12-21	Andrew Waterman	Support aligning text section from odd addresses	commit \| commitdiff \| tree
2016-12-21	Andrew Waterman	Avoid creating symbol table entries for registers	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Correct assembler mnemonic for RISC-V aqrl AMOs	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Fix disassembly of RISC-V CSR instructions under -Mno...	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Add canonical JALR for RISC-V	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Don't define RISC-V .p2align	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Re-work RISC-V gas flags: now we just support -mabi...	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Fix an integer overflow in RISC-V relocation handling	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Rework RISC-V relocations	commit \| commitdiff \| tree
2016-12-20	Andrew Waterman	Formatting changes for RISC-V	commit \| commitdiff \| tree

GDB Binutils - Deliverables

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