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drm/i915: Move intel_dp->lane_count into pipe_config
2015-08-14  Ville Syrjälädrm/i915: Move intel_dp->lane_count into pipe_config
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2015-08-14  Ville Syrjälädrm/i915: Avoid confusion between DP and TRANS_DP_CTL...
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2015-08-14  Ville Syrjälädrm/i915: Don't pass clock to DDI PLL select functions
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2015-08-14  Ville Syrjälädrm/i915: Don't use link_bw for PLL setup
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2015-08-14  Ville Syrjälädrm/i915: Clean up DP/HDMI limited color range handling
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2015-08-14  Ville Syrjälädrm/i915: clflush on pin_to_display after pwrite to...
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2015-07-13  Ville Syrjälädrm/i915: Adjust BXT HDMI port clock limits
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2015-07-13  Ville Syrjälädrm/i915: Refactor VLV display power well init/deinit
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2015-07-13  Ville Syrjälädrm/i915: Simplify CHV pipe A power well code
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2015-07-13  Ville Syrjälädrm/i915: Apply OCD to VLV/CHV DPLL defines
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2015-07-13  Ville Syrjälädrm/i915: Keep GMCH DPLL VGA mode always disabled
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2015-07-09  Ville SyrjäläRevert "drm/i915: Allocate context objects from stolen"
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2015-07-06  Ville Syrjälädrm/i915: Disable LVDS port after the pipe on PCH
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2015-07-06  Ville Syrjälädrm/i915: Drop a spurious intel_pre_plane_update()...
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2015-07-06  Ville SyrjäläRevert "drm/i915: Disable 12bpc hdmi for now"
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2015-07-06  Ville Syrjälädrm/i915: Account for CHV/BXT DPLL clock limitations
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2015-07-06  Ville Syrjälädrm/i915: Bump HDMI min port clock to 25 MHz
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2015-07-06  Ville Syrjälädrm/i915: Fix HDMI 12bpc and pixel repeat clock readout...
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2015-06-29  Ville Syrjälädrm/i915: Zero unused WM1 watermarks on VLV/CHV
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2015-06-29  Ville Syrjälädrm/i915: Add debugfs knobs for VLVCHV memory latency...
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2015-06-29  Ville Syrjälädrm/i915: Don't do PM5/DDR DVFS with multiple pipes
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2015-06-29  Ville Syrjälädrm/i915: Try to make sure cxsr is disabled around...
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2015-06-29  Ville Syrjälädrm/i915: Use the memory latency based WM computation...
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2015-06-29  Ville Syrjälädrm/i915: Compute display FIFO split dynamically for CHV
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2015-06-29  Ville Syrjälädrm/i915: CHV DDR DVFS support and another watermark...
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2015-06-29  Ville Syrjälädrm/i915: Read wm values from hardware at init on CHV
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2015-06-29  Ville Syrjälädrm/i915: Split atomic wm update to pre and post variants
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2015-06-29  Ville Syrjälädrm/i915: POSTING_READ() in intel_set_memory_cxsr()
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2015-06-25  Ville Syrjälädrm/i915: Add debug messages for pipe enable/disable
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2015-06-25  Ville Syrjälädrm/i915: Store frontbuffer_bits in the plane
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2015-06-22  Ville Syrjälädrm/i915: Factor out p2 divider selection for pre-ilk...
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2015-06-15  Ville Syrjälädrm/i915: Drop the 64k linear scanout alignment on...
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2015-06-15  Ville Syrjälädrm/i915: Align DSPSURF to 128k on VLV/CHV
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2015-06-15  Ville Syrjälädrm/i915: Actually respect DSPSURF alignment restrictions
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2015-06-15  Ville Syrjälädrm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk
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2015-06-15  Ville Syrjälädrm/i915: Double the port clock when using double clocked...
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2015-06-15  Ville Syrjälädrm/i915: Fix hdmi clock readout with pixel repeat
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2015-06-15  Ville Syrjälädrm/i915: Check infoframe state more diligently.
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2015-06-15  Ville Syrjälädrm/i915: Disable all infoframes when turning off the...
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2015-06-15  Ville Syrjälädrm/i915: Fix 12bpc HDMI enable for IBX
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2015-06-15  Ville Syrjälädrm/i915: Fix HDMI 12bpc TRANSCONF bpc value
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2015-06-15  Ville Syrjälädrm/i915: Enable default_phase in GCP when possible
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2015-06-15  Ville Syrjälädrm/i915: Send GCP infoframes for deep color HDMI sinks
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2015-06-15  Ville Syrjälädrm/i915: Don't skip request retirement if the active...
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2015-06-15  Ville Syrjälädrm/i915: Implement WaEnableHDMI8bpcBefore12bpc:snb...
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2015-06-12  Ville Syrjälädrm/i915: BDW clock change support
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2015-06-12  Ville Syrjälädrm/i915: Add IS_BDW_ULX
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2015-06-12  Ville Syrjälädrm/i915: Don't enable IPS when pixel rate exceeds 95%
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2015-06-12  Ville Syrjälädrm/i915: Store max cdclk value in dev_priv
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2015-06-12  Ville Syrjälädrm/i915: Use cached cdclk value
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2015-06-12  Ville Syrjälädrm/i915: Cache current cdclk frequency in dev_priv
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2015-06-04  Ville Syrjälädrm/i915: Move WaBarrierPerformanceFixDisable:skl to...
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2015-06-03  Ville Syrjälädrm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs...
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2015-06-03  Ville Syrjälädrm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8...
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2015-06-03  Ville Syrjälädrm/i915: Move WaBarrierPerformanceFixDisable:skl to...
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2015-06-01  Ville Syrjälädrm/i915: Don't skip request retirement if the active...
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2015-05-29  Ville Syrjälädrm/i915: Warn when cdclk for the platforms is not...
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2015-05-29  Ville Syrjälädrm/i915: Add cdclk extraction for g33, g965gm and g4x
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2015-05-29  Ville Syrjälädrm/i915: Fix 852GM/GMV cdclk
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2015-05-29  Ville Syrjälädrm/i915: Fix i855 get_display_clock_speed
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2015-05-28  Ville Syrjälädrm/i915: Adjust sideband locking a bit for CHV/VLV
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2015-05-28  Ville Syrjälädrm/i915: s/dpio_lock/sb_lock/
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2015-05-28  Ville Syrjälädrm/i915: Kill intel_flush_primary_plane()
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2015-05-28  Ville Syrjälädrm/i915: Throw out WIP CHV power well definitions
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2015-05-28  Ville Syrjälädrm/i915: Use the default 600ns LDO programming sequence...
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2015-05-22  Ville Syrjälädrm/i915: Enable GTT caching on gen8
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2015-05-22  Ville Syrjälädrm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_g...
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2015-05-22  Ville Syrjälädrm/i915: Use ilk_init_lp_watermarks() on BDW
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2015-05-21  Ville Syrjälädrm/i915: Disable FDI RX/TX before the ports
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2015-05-21  Ville Syrjälädrm/i915: Disable CRT port after pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Disable SDVO port after the pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Disable HDMI port after the pipe on PCH platforms
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2015-05-21  Ville Syrjälädrm/i915: Fix the IBX transcoder B workarounds
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2015-05-21  Ville Syrjälädrm/i915: Write the SDVO reg twice on IBX
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2015-05-21  Ville Syrjälädrm/i915: Fix DP enhanced framing for CPT
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2015-05-21  Ville Syrjälädrm/i915: Clean up the CPT DP .get_hw_state() port...
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2015-05-21  Ville Syrjälädrm/i915: Clarfify the DP code platform checks
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2015-05-21  Ville Syrjälädrm/i915: Remove the double register write from intel_disabl...
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2015-05-21  Ville Syrjälädrm/i915: Remove a bogus 12bpc "toggle" from intel_disable_h...
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2015-05-20  Ville Syrjälädrm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV
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2015-05-20  Ville Syrjälädrm/i915: Remove excess inline keywords
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2015-05-12  Ville Syrjälädrm/edid: Add CEA modes before inferred modes
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2015-05-08  Ville Syrjälädrm/i915: Only wait for required lanes in vlv_wait_port_ready()
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2015-05-08  Ville SyrjäläRevert "drm/i915: Hack to tie both common lanes together...
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2015-05-08  Ville Syrjälädrm/i915: Work around DISPLAY_PHY_CONTROL register...
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2015-05-08  Ville Syrjälädrm/i915: Implement chv display PHY lane stagger setup
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2015-05-08  Ville Syrjälädrm/i915: Add missing POSTING_READ()s to BXT dbuf enable...
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2015-05-08  Ville Syrjälädrm/i915: s/9/intel_freq_opcode(450)/
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2015-05-08  Ville Syrjälädrm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox()
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2015-05-07  Ville Syrjälädrm/edid: Add DMT modes with ID > 0x50
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2015-05-07  Ville Syrjälädrm/edid: Add the DMT ID in the comments
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2015-05-07  Ville Syrjälädrm/edid: Fix up DMT modes
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2015-04-10  Ville Syrjälädrm/i915: Fix the VBT child device parsing for BSW
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2015-04-10  Ville Syrjälädrm/i915: Silence a sparse warning
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2015-04-02  Ville Syrjälädrm/i915: Reject the colorkey ioctls for primary and...
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2015-03-31  Ville Syrjälädrm/i915: Convert the ddi cdclk code to get_display_clock_speed
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2015-03-31  Ville Syrjälädrm/i915: Simplify ilk_get_aux_clock_divider
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2015-03-31  Ville Syrjälädrm/i915: Assume 400MHz cdclk for the rest of gen4-7
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2015-03-31  Ville Syrjälädrm/i915: ILK cdclk seems to be 450MHz
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2015-03-31  Ville Syrjälädrm/i915: Return more precise cdclk for gen2/3
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