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(parent: 25e5908) | patch
Remove riscv has_load_add_load_load_add_store implementation
authorMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Tue, 5 Mar 2024 15:10:53 +0000 (10:10 -0500)
committerMathieu Desnoyers <mathieu.desnoyers@efficios.com>
Tue, 5 Mar 2024 15:37:24 +0000 (10:37 -0500)
commit0f963443529cf64515af5f9ec90dec7b754880dc
treed7e39f795a8aa9b28fd16c27c0ca7aa99b26da19tree | snapshot
parent25e59085d045d1a13b1b140d012541b30897b531commit | diff
Remove riscv has_load_add_load_load_add_store implementation

The implementation is currently buggy: RSEQ_ASM_OP_R_DEREF_ADDV()
should increment the address _target_ as a final store, not just the
address within the temporary register.

Remove it for now.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0f2a854cec4ab5e58ea6cbb74d40ca29b256d27e
include/rseq/arch/riscv.h diff | blob | blame | history
include/rseq/arch/riscv/bits.h diff | blob | blame | history
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