mempool: Use masks to get pool range from pointer and stride for percpu offset

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I45bb460be66bc4843ead316d7b870958cd1217c2

Memory map ranges aligned on the stride

This will allow finding the range header with a mask applied on the
pointer in free().

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I25821ebb4a7333fe53658932f58c6d9cad1bd64a

percpu alloc: Introduce stride parameter

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I6469725da2610560872d2fe678128455d7ff22f1

rseq-mempool: Call set_alloc_slot() on all paths

set_alloc_slot() was not called when getting free slot from free-list.

Change-Id: I21d633ced6592039fe39e0ae121128958048f80e
Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

mempool: implement one range

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I189ee936cd11229b5770ed95c8ac32b67fede20d

Update mempool test

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I57fe799bcdb4df1d6d6fb6e605e17cf581f13197

Add mempool test to make check

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ia998f1157083df566e8e8e9c331983bab256880f

mempool test: safe iteration for free

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id5fe8f73dff0c914646a76af45738a2e80a8e2b2

Introduce mempool test

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

Rename percpu-alloc files to mempool

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0a1ba042649cf3b2224a90a05e095733e9a597fc

Update gitignore

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I55d5e3571e7115cec5d09fac52ce51fa3601c12d

percpu alloc: Remove RSEQ_POOL_ROBUST attribute

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: If90ce5767d0d2516674efda08fb0d694b4f8d1a2

percpu-alloc: Add move_pages batching

Change-Id: I5e9f40d73f45f2abeded1d1f62056a478fd8455a
Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

percpu pool: Move robust flag to atttribute

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie83fff22b71dc9be39d90e4be97d094b90542715

percpu pool: mmap set attr: return error value

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id2debf769299ee1d6624097b38e79f916b8c0f2b

percpu pool: Introduce generic attributes

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7641218c7f69b73fc998eddf2839312fcf5726e9

percpu alloc: add pool name

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I886c840f394cb1de0b5ab71b7417b99675ea1468

Fix typos in fprintf

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ic82493c649a2389391808f079d9ed58c81e61018

percpu-alloc: Add free-list check on pool destroy

Change-Id: I68bab4673aabde92dc0d8321de2d5561c5e7a11c
Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

rseq percpu: print caller ip on double-free/alloc corruption and leak

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I5b1bc7a2a5711e6c9de4bc82df92a49df5654f8b

Fix: add missing \n in fprintf

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ibbb61e3b7f66f8d9b7ed125e4123581b2c1b93d9

Implement rseq_hweight_ulong with __builtin_popcountl

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I483d53c7c5402e034b8d468e0ed2ab048184f069

Fix destroy_alloc_bitmap size

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ic53da70a6fbcbbdd87c885d01d80a5ba65befb5a

percpu alloc: Improve robust pools

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I4966965cca5143640347a4b21fef3e2c353c8366

percu-allocator: Implement robust pool validation

When set, the RSEQ_POOL_ROBUST flag will add a bitmap to the pool which
is used to track double-free and allocation leaks in the pool.

Signed-off-by: Olivier Dion <odion@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I531782ee57d33c9704b9cca44af1a9464f60cb90

percpu: remove rseq_percpu_pool_ptr_offset

The rseq_percpu_pool_ptr_offset API is now unused, and it leaks
implementation details about per-cpu pools which may prevent
implementing auto-extensible pools efficiently in the future.

Remove it.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ib62c4af34c04f9c4e5227dab2f487356478b32fa

x86-64: Implement/use load_cbne_load_add_load_add_store

Change the current load_add_load_load_add_store for a
load_cbne_load_add_load_add_store, which allows validating that the
percpu pointer did not change since it was loaded from C.

This allows precomputing the address of the percpu memory area in C and
provide it as a second pointer argument.

The comparison approach is prefered to the offset-from-pointer approach
because it does not leak implementation details of the percpu allocator.

Add missing rseq_after_asm_goto() in the static inline function.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I3fe9d57d13f7507d5af95ef37391ad36fe2221fe

Remove riscv has_load_add_load_load_add_store implementation

The implementation is currently buggy: RSEQ_ASM_OP_R_DEREF_ADDV()
should increment the address _target_ as a final store, not just the
address within the temporary register.

Remove it for now.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0f2a854cec4ab5e58ea6cbb74d40ca29b256d27e

param test: membarrier: validate total number of increments

While reviewing the riscv implementation for this test, I noticed that
the final store is only incrementing the content of its register,
without ever storing it to memory.

This passes testing because the increment is effectively a no-op, and
the test never validates that any increment happen in the first place.

Introduce a validation of the increment total to eliminate those
false-positives.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie9ee1c7902509da75dd85babd07bc180ad0b9ae9

percpu allocator: Add flags argument for future extensions

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I4c507a99351c450ef2c6396af5391f019f8e3d91

percpu alloc: introduce rseq mmap attributes

Introduce rseq mmap attribute argument to pool creation, allowing
users to override the memory allocator used to allocate/free the pool
memory.

Move NUMA page move to a separate rseq_percpu_pool_init_numa() API.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie08c7250fce5f567c7a4aee469e010c5dcf39bc6

Cleanup: Remove whiteline

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I537b82707f1f9a95005da672b98196ab44875e2a

Rename RSEQ_ARCH_HAS_OFFSET_DEREF_ADDV to rseq_arch_has_load_add_load_load_add_store

Fix param test to use rseq_arch_has_load_add_load_load_add_store
rather than rseq_arch_has_load_cbne_load_add_store.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I373c91dc9178dd69ed159d568090e8c732cf4485

Revert "Introduce rseq_load_cbne_load_add_store pseudocode"

This reverts commit 3eff770448484493fa15ea90db643f86c124db6c.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

Revert "x86: Introduce rseq_load_cbne_load_add_store"

This reverts commit 18f21b27f01b9147cd95c538ece07f95c37150a2.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ieffcd50965fe6dcf2c7d067f5fddb4e9f62e82f3

Revert "rseq.h: Introduce rseq_load_cbne_load_add_store__ptr"

This is not needed anymore.

This reverts commit 040147907ff31cdc279568ffcb74197650430e4b.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

param tests: membarrier: pre-decode pointer offset

Loading "cpulist->head" outside of the rseq critical section is
unintended: loading cpulist->head loads memory from the per-cpu list
outside of the rseq critical section, which happens to work because the
memory is not actually freed in this specific test case, but would break
if memory would be reclaimed after the rseq fence.

So go back to the originally used rseq_load_add_load_load_add_store__ptr(),
and use the new rseq_percpu_pool_ptr_offset() to pre-calculate the
offset.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I5e621c724e143e38a6dfabd26bbf682a6fcc5182

percpu alloc: introduce rseq_percpu_pool_ptr_offset

Introduce rseq_percpu_pool_ptr_offset to pre-decode the offset from
all __rseq_percpu pointers for a given pool. This is useful to prepare
offsets that would need to be calculated within rseq critical sections.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I42d2669ed5ed81d74aae551b721c9cb04b25fe45

Document percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I8fa4b68e8a68c57da8ab726d0f68ee12aad2f15e

rseq percpu: Remove __rseq_percpu annotation from returned pointer

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Iea04ce173cc529612b1024393794a304b0e7e219

x86-32: ip-relative: return to post-call address

This simplifies the assembler returns to the expected (speculated)
address.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I68c59f72ac32011d37cc9399414ff328f7b8fdd0

param test: x86-32: use ip-relative addressing for RSEQ_INJECT_ASM

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id8349df846f5b0491b348b603f0423b726c55b8c

x86-32: Save ip reference for ip-relative addressing

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie95e1bf409f0ca0c271f529b694839905d4d0d91

x86-32: Use ip-relative addressing to store rseq_cs

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I294a4844bf8022be480059a028b9a17a5a2dcc4b

x86-32: work-around register pressure limitations

Use explicit register clobbers and load input values from "m" input
operands to reduce register pressure.

Note that old gcc does not support output operands for asm goto, so we
cannot simply re-use an input register as output.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I745d27f416ef303b1049e8c12b122e5b4a271f63

x86-32: Document linker warning

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I35e1db5eda78ea4b6349039ed34d739b33b81d6d

arm: work-around register pressure limitations

The recent move to percpu allocator breaks the 32-bit ARM build due to
register pressure. Fix this by using explicit register clobbers and
loading input values from "m" input operands.

Note that old gcc does not support output operands for asm goto, so we
cannot simply re-use an input register as output.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I1d546e427c7f6b62035433815806c8ec275a55f8

param tests: percpu memcpu buffer: use percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I86c975aa8578469f685dcdb4951f4af50f06b3fe

param tests: percpu buffer: use percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I49f29134679931eed4e06140a72cc56592cc12b8

param tests: percpu list: use percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie1415e33187902e76dd3d492cd8ed2fe9b980565

rseq.h: Introduce rseq_load_cbne_load_add_store__ptr

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I5011d4115d5dc0064b0d3fc359c037dcda02508c

x86: Introduce rseq_load_cbne_load_add_store

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id5d8ebfe056ef60ba38a7ab0bf1e368ca324ab25

Introduce rseq_load_cbne_load_add_store pseudocode

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I2c5099af7958591521f6e934da128b54ca3535c3

Rename rseq_load_add_load_add_store to rseq_load_add_load_load_add_store

Match the pseudo-code.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I48d60a9688cf76936fa1ba7a3b1d6b7412a77e69

param test: counter increment: use percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ia98154794a80ce917a742961c95d3aef28f7aa1e

param test: use __rseq_percpu pointer tagging

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I2735cd5d08e5f7ed085411934cc5e74938a7ca46

Add __rseq_percpu pointer tagging

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7a10ac1ad1e97aaaad947e29f377a103e380286d

Adapt spinlock param test to percpu alloc

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7602983d2aaf9f9a59209c9b3b1cce6fed4ca74d

Skip first pool

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: If07b9bbe91fa24b805d7943d4c0cb448cc89c210

percpu alloc: add missing extern C

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I3039487f8e9a130b2fbcb8e6771df449d6021087

Add missing include in percpu-alloc.h

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ic3d124544c8a651d61f69a872ed03bdfcb638232

Set errno on malloc error

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ia03a24e63e10907525042f59b1c062ca4f8fe8fc

percpu pool set malloc: start search at relevant alloc order

Start search for a pool which can accomodate the @len allocation at an
allocation order where it can fit.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ib887759416120cad78da6a3758d5a8e5781380ad

rseq-percpu: Improve documentation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ib9e850d38c7c8bac2a7b94df767275f8f659cb9c

Introduce rseq-alloc-utils.h

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I33970b558ad0d59629737d1a6c0d8531fbcf93e9

rseq percpu: Use high bits for pool index

This leaves the low bits available for pointer tagging.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7cebf88a1db4d6cdfd5d287626c67888e80ffbd2

rseq percpu alloc: Implement numa support

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I732b632f476ffef362a1ab486bcf425e4ded6644

Implement per-cpu memory allocator

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I54f43ccec743b7c5311221fac22a0b690a863377

Introduce __RSEQ_ASM_DEFINE_CS_FIELDS

The new macro __RSEQ_ASM_DEFINE_CS_FIELDS can be used by
__RSEQ_ASM_DEFINE_TABLE as well as __RSEQ_ASM_DEFINE_ABORT on
arm and mips, thus removing redundant code.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ie03f5d51d20027a3eb3b9eba636b0f5cc890c333

Introduce common generic header file

Move:

-  RSEQ_ASM_DEFINE_TABLE,
- __RSEQ_ASM_DEFINE_TABLE,
- RSEQ_ASM_DEFINE_EXIT_POINT.

to a generic common header file now that those are exact copy across all
architectures.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I1f27e8889b13d263467a1bab92b272cc80aa0743

x86: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I966b67f00bf39bd0b26f8efd6c4f40cba4caa1cf

riscv: Introduce RSEQ_ASM_U64_PTR and RSEQ_ASM_U32

These will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I9cac7076b9ef9bd7dd4a818b9ad7aae1df45ff5a

s390: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0af09a3fa3970efbe523db04154f1969241369a1

ppc: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ic476d6dfca6f714cf892f84560884157abbc0360

mips: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I5a68ce2782bc36d5fc8c030ca7716e41e925cd54

arm: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I32a0eff75998afb1f8257c3312187ab2938d59a3

aarch64: Introduce RSEQ_ASM_U32

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I4496c41d37094983b724fc8bb101688f75fefbbd

thread-pointer: suffix include guard with _H

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id35f1cb103e1d68bde10785e44c5c16104f000d4

arm: Fix big endian, introduce RSEQ_ASM_U64_PTR

Fix support for Big endian ARM by introducing RSEQ_ASM_U64_PTR.

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I6271f217b0e1463968bd7d520ddd0fb61678bb84

arm: Cleanup header codying style

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Iab1aee9103eef2179fcdc8c2171afda3d311379b

aarch64: Introduce RSEQ_ASM_U64_PTR

This will allow moving __RSEQ_ASM_DEFINE_TABLE and
RSEQ_ASM_DEFINE_EXIT_POINT to a generic common header file.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ic5470bb851be1b79bbba387a4db2ce0911bbe23d

aarch64: Cleanup header coding style

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7986cf871be81fc8bb94d0d44d9f61ee41ba0fc1

s390: Introduce code deduplication macros

Introduce RSEQ_ASM_U64_PTR() which expresses the type and instance
of the defined variable, allowing deduplication of the following macros:

- __RSEQ_ASM_DEFINE_TABLE,
- RSEQ_ASM_DEFINE_EXIT_POINT.

Separate load/store/op helper macros, RSEQ_ASM_STORE_RSEQ_CS, and
RSEQ_ASM_U64_PTR into their respective ifdef regions, as the resulting
documentation is clearer (and not duplicated).

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I37c481c9eb726b49dfdf00539c42d68bb500b2c7

ppc: Introduce code deduplication macros

Introduce RSEQ_ASM_U64_PTR() which expresses the type and instance
of the defined variable, allowing deduplication of the following macros:

- __RSEQ_ASM_DEFINE_TABLE,
- RSEQ_ASM_DEFINE_EXIT_POINT.

Separate load/store/op helper macros, RSEQ_ASM_STORE_RSEQ_CS, and
RSEQ_ASM_U64_PTR into their respective ifdef regions, as the resulting
documentation is clearer (and not duplicated).

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I7accb4925e1e294f2d65267641fd4c8dccb4837f

x86: Introduce code deduplication macros

Introduce RSEQ_ASM_U64_PTR() which expresses the type and instance
of the defined variable, allowing deduplication of the following macros:

- __RSEQ_ASM_DEFINE_TABLE,
- RSEQ_ASM_DEFINE_EXIT_POINT.

Separate RSEQ_ASM_TP_SEGMENT, RSEQ_ASM_STORE_RSEQ_CS, and
RSEQ_ASM_U64_PTR into their respective ifdef regions, as the resulting
documentation is clearer (and not duplicated).

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I13e90120f9f50bb898f99f545c3eb205fe9d8437

mips: Reorganise code deduplication macros

Introduce RSEQ_ASM_U64_PTR() which expresses the type and instance
of the defined variable.

Separate the RSEQ_ASM_LONG* macros from the 64-bit pointer types, as
those two are unrelated. Having them in the same vincinity is
misleading.

Test on RSEQ_BITS_PER_LONG rather than _MIPS_SZLONG to make it
consistent across architectures.

Use both __BYTE_ORDER and __BIG_ENDIAN to detect byte order.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I1a65210e9ab0c00a5625c9feba7971081eb34c35

Re-organise public headers

The structure is inspired by the liburcu project.

- Remove the double namespacing 'rseq/rseq-'
- Add a structured architecture support layout
- Add missing guards on arch headers
- Split the main rseq.h header into utils.h and inject.h
- Add the always_inline attribute to all static inline functions

Change-Id: I6a244e5f364d28d5d8c3d426d6039c4d8aa15a36
Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

Fix supported autotools versions in README.md

Change-Id: I07257e51544546a8c39325dd05a0a0b99b47a5e2
Signed-off-by: Michael Jeanson <mjeanson@efficios.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>

RSEQ_ASM_DEFINE_TABLE: use parentheses around parameters on all archs

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I09ad49a2eb132768d9fca4547d602240bc3d84a4

Comment s390 macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ifaeeed3e7721b9c0f758abef63c286a4d22e5268

s390: namespace public header macros under RSEQ_ASM_

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I777a7b3feb9361c9dbc5327f643fc2d09aaa238e

Comment riscv macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I4299061a38443bff9ff0701b73752153d2c3df54

riscv: Add missing "inc" parameter to RSEQ_ASM_OP_R_DEREF_ADDV

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Iff9fb8f46acef741a22065a6c0b976794c4606dd

riscv: namespace public header macros under RSEQ_ASM_

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: If8750ceaee9ca4d30309c974e675336ea4290d19

mips: Move RSEQ_ASM_DEFINE_ABORT table_label parameter to 4th argument

Makes the first 3 arguments same as other architectures.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Icf41ded4ce5860cf8c12a23dff1fe434210844b0

arm: Move RSEQ_ASM_DEFINE_ABORT table_label parameter to 4th argument

Makes the first 3 arguments same as other architectures.

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I855d645ec5e315ef19836adebfd2f9350a3763c5

Comment mips macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I6a1646a8cc18cf249b7323afc9ceb0600f001649

Comment ppc macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: I0b51030c416d875de296ba7f4490bd59ba810f72

Comment arm64 macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Id918fa702bfbee014766f949329d1068a0404340

Comment arm macros implementation

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Change-Id: Ibb74479b2219cf2da92a17034785f94cb7dba932